JP2009212364A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has a contact structure of low contact resistance formed even when the contact structure is fine, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device has an impurity region 15 formed at a surface portion of a silicon substrate 11 and a metal silicide layer 16 formed to a predetermined depth from an upper surface of the impurity region 15. An interlayer insulating film 18 is formed on the silicon substrate 11, and a contact hole 19 is formed which penetrates the interlayer insulating film 18 so that its bottom reaches the metal silicide layer 16. The contact hole 19 is an opening portion such that the area of a sidewall made of the metal silicide layer 16 is larger than the area of a bottom surface made of the metal silicide layer 16. Further, a contact plug 21 coming into contact with the sidewall and the bottom surface of the contact hole 19 which is made of the metal silicide layer 16 is buried in the contact hole 19. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a fine contact structure with a low contact resistance and a manufacturing method thereof.

  Along with the rapid integration of semiconductor devices in recent years, the minimum feature size of semiconductor devices has been rapidly reduced, and the contact structure has also been rapidly miniaturized and reduced. In a semiconductor device provided with a contact hole having a fine opening diameter, it is necessary to suppress an increase in contact resistance due to the miniaturization of the contact hole in order to increase the operation speed of the element. However, with the miniaturization of the contact hole, it is difficult to secure a contact area between the contact plug and the impurity region formed in the semiconductor substrate, and it is becoming difficult to suppress an increase in contact resistance. As countermeasures, various techniques for suppressing an increase in contact resistance even when a fine contact structure is formed have been proposed.

For example, Patent Document 1 described later discloses a technique for ensuring the area of the contact hole bottom (contact bottom area). In this conventional example, first, an impurity region to be connected to a contact structure is formed in an active region on a silicon substrate. Next, an interlayer insulating film is formed on the silicon substrate, and a contact hole reaching the impurity region is formed in the interlayer insulating film. Then, after the silicon substrate in the impurity region exposed at the bottom of the contact hole is selectively removed by etching, a metal thin film is deposited in the contact hole. Thereafter, heat treatment is performed, and metal silicide is formed in the impurity region at the bottom of the contact hole. In this technique, since the silicon substrate exposed at the bottom of the contact hole is etched, the area of the silicon substrate that is subsequently silicided at the bottom of the contact hole is increased. As a result, the contact bottom area can be secured.
JP 2003-86535 A

  However, since the silicon substrate is silicided by the metal deposited in the contact hole, the above conventional technique becomes difficult to apply as the contact hole is miniaturized. That is, when a metal for silicidation is deposited in a contact hole, a sputtering method is used, but in a fine contact structure having a high aspect ratio, a metal for forming a metal silicide at the bottom of the contact hole by the sputtering method. It is difficult to form the film with a sufficient thickness. Therefore, it becomes difficult to form a metal silicide at the contact bottom, and an increase in contact resistance cannot be suppressed.

  As a method for forming a contact structure, there is a method in which an interlayer insulating film is formed on an impurity region having a silicide layer formed on the surface, a contact hole is formed in the interlayer insulating film, and the silicide layer is exposed at the bottom. . However, in this method, the contact area between the contact plug and the silicide layer is defined by the contact bottom area, so that the contact resistance rapidly increases as the contact hole opening diameter decreases.

  The present invention has been proposed in view of the above-described conventional circumstances, and provides a semiconductor device capable of forming a contact structure having a low contact resistance even with a fine contact structure and a method for manufacturing the same. It is an object.

  In order to solve the above problems, the present invention employs the following technical means. That is, the semiconductor device according to the present invention includes an impurity layer formed on the surface portion of the semiconductor substrate, and a metal silicide layer formed from the surface of the impurity layer to a predetermined depth of the impurity layer. An insulating film is formed on the semiconductor substrate, and a contact hole penetrating through the insulating film and having the bottom reaching the metal silicide layer is formed. The contact hole is an opening in which the area of the side wall made of the metal silicide layer is larger than the area of the bottom surface made of the metal silicide layer. Further, a conductor that contacts the side wall and the bottom surface of the contact hole made of the metal silicide layer is buried in the contact hole as a contact plug.

  Another semiconductor device according to the present invention includes an impurity layer formed on a surface portion of a semiconductor substrate and a metal silicide layer formed from the surface of the impurity layer to a predetermined depth of the impurity layer. An insulating film is formed on the semiconductor substrate, and a contact hole penetrating the insulating film and the metal silicide layer is formed. The contact hole is an opening through which the impurity layer is exposed on the bottom surface. Furthermore, a conductor that contacts the side wall made of the metal silicide layer and the bottom face made of the impurity layer of the contact hole is buried in the contact hole as a contact plug.

  In the semiconductor device described above, the contact area between the metal silicide layer and the contact plug can be increased by effectively using the side wall of the contact hole. For this reason, even when a fine contact hole is formed, an increase in contact resistance can be suppressed.

  The above semiconductor device may be configured to further include a semiconductor layer formed on the impurity layer. In this case, the metal silicide layer is formed from the surface of the semiconductor layer to a predetermined depth of the impurity layer. The semiconductor layer may be made of a material that can form metal silicide. In this configuration, the area of the side wall made of metal silicide that contacts the contact plug can be easily increased, and the increase in contact resistance can be further suppressed.

  The impurity layer includes a recess formed in the surface portion of the semiconductor substrate and a conductive semiconductor layer formed in the recess with the upper surface protruding above the surface of the semiconductor substrate. You can also. Even in this configuration, the area of the side wall made of the metal silicide in contact with the contact plug can be easily increased, and the increase in contact resistance can be further suppressed.

  Furthermore, in a configuration in which the contact hole penetrates the insulating film and the metal silicide layer, it is preferable that the area of the side wall made of the metal silicide layer is larger than the area of the bottom surface made of the impurity layer. The above configuration is particularly suitable when, for example, a contact hole is formed between gate electrodes formed on the surface of a semiconductor substrate via an insulating film.

  On the other hand, in another aspect, the present invention can also provide a method for manufacturing a semiconductor device. That is, in the method for manufacturing a semiconductor device according to the present invention, first, an impurity layer is formed on the surface portion of the semiconductor substrate. Next, a metal silicide layer is formed on the surface of the impurity layer. An insulating film is formed on the semiconductor substrate on which the metal silicide layer is formed. Subsequently, a contact hole penetrating the insulating film and having the bottom reaching the metal silicide layer is formed. The contact hole is an opening in which the area of the side wall made of the metal silicide layer is larger than the area of the bottom surface made of the metal silicide layer. Then, a contact plug, which is a conductor that contacts the side wall and the bottom surface made of the metal silicide, is buried in the contact hole.

  In another method of manufacturing a semiconductor device according to the present invention, first, an impurity layer is formed on the surface portion of the semiconductor substrate. Next, a metal silicide layer is formed from the surface of the impurity layer to a predetermined depth. An insulating film is formed on the semiconductor substrate on which the metal silicide layer is formed. Subsequently, a contact hole penetrating the insulating film and the metal silicide layer is formed. The contact hole is an opening through which the impurity layer is exposed on the bottom surface. Then, a contact plug, which is a conductor that contacts the side wall made of the metal silicide layer and the bottom surface made of the impurity layer, is buried in the contact hole.

  In the above method for manufacturing a semiconductor device, the semiconductor layer can be formed on the impurity layer after the impurity layer is formed and before the metal silicide layer is formed. In this case, the metal silicide layer is formed from the surface of the semiconductor layer to a predetermined depth of the impurity layer. The impurity layer includes a step of forming a recess in the surface portion of the semiconductor substrate, and a step of forming a conductive semiconductor layer in the recess in a state where the upper surface protrudes upward from the surface of the semiconductor substrate; Can also be formed.

  According to the present invention, the contact area between the metal silicide layer and the contact plug can be increased by effectively using the side wall of the contact hole. For this reason, even when a fine contact hole is formed, an increase in contact resistance can be suppressed. Therefore, the present invention is extremely significant in achieving miniaturization, high integration, high performance, and yield improvement of semiconductor devices.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied by a semiconductor device in which two transistors are formed in a region on a semiconductor substrate (silicon substrate) divided by element isolation. In each embodiment, the contact plug electrically connected to the high-concentration impurity diffusion region through the metal silicide layer is connected to a common impurity region (for example, drain region) disposed between the gate electrodes of the transistors. Has been. Similar contacts are formed in other impurity regions (for example, the source region) of each transistor, but in the following, illustration and description of the other impurity regions and the contacts connected to the other impurity regions are omitted. ing. Each of the following drawings is a schematic diagram, and is not a diagram in which the vertical and horizontal dimensional ratios are strictly reflected.

(First embodiment)
FIG. 1 is a process cross-sectional view illustrating a manufacturing process of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1A, a silicon oxide film or silicon oxynitride is formed on the surface of a semiconductor substrate 11 made of single crystal silicon or the like on which element isolation (not shown) is formed by an STI (Shallow Trench Isolation) method or the like. A gate insulating film made of a film or the like is formed with a film thickness of several nm by RTP (Rapid Thermal Process) or the like. On the semiconductor substrate 11 on which the gate insulating film is formed, a polysilicon film is deposited with a thickness of about 120 nm by a CVD (Chemical Vapor Deposition) method or the like. By applying a known lithography technique and etching technique to the gate insulating film and the polysilicon film, two gate electrodes 12 are formed on the semiconductor substrate 11 via the gate insulating film 13 respectively. Thereafter, impurities are ion-implanted into the semiconductor substrate 11 using the gate electrode 12 as a mask to form an impurity region (not shown) to be an extension region. The gate length is about 60 nm.

  Next, an insulating film made of a silicon nitride film or the like is deposited on the semiconductor substrate 11 to a thickness of about 50 nm. By performing anisotropic etching such as argon sputter etching on the insulating film, sidewall insulating films 14 are formed on both sides of the gate electrode 12. Thereafter, using the gate electrode 12 and the sidewall insulating film 14 as a mask, an impurity having the same conductivity type as that of the extension region is ion-implanted to form an impurity region 15 (impurity layer). In this embodiment, the junction depth of the impurity region 15 (distance from the surface of the semiconductor substrate 11 to the PN junction at the bottom of the impurity region 15) is about 70 nm.

  Subsequently, as shown in FIG. 1B, a metal silicide layer 16 is formed in a self-aligned manner on the surface of the impurity region 15 and the upper surface of the gate electrode 12 by a known salicide process. Here, as the metal silicide layer 16, nickel silicide is formed with a film thickness of 25 nm. After the metal silicide layer 16 is formed, a liner layer 17 made of a silicon nitride film or the like is formed on the semiconductor substrate 11 with a film thickness of about 25 nm by a CVD method or the like. The liner layer 17 functions as an etching stopper in a contact hole forming process described later. On the liner layer 17, an insulating film 18 (hereinafter referred to as an interlayer insulating film 18) made of a silicon oxide film or the like is formed with a film thickness of about 700 nm by a CVD method or the like. A resist pattern (not shown) having an opening at a contact hole formation position is formed by a photolithography technique on the interlayer insulating film 18 whose upper surface is planarized by a CMP (Chemical Mechanical Polishing) method, an etch back method, or the like. . In this embodiment, the opening diameter of the resist pattern is about 80 nm.

  Subsequently, contact holes 19 (openings) are formed in the interlayer insulating film 18 by anisotropic etching using the resist pattern as a mask. The etching is performed under the condition that the etching rate of the interlayer insulating film 18 is larger than the etching rate of the liner layer 17. Therefore, the etching stops with the liner layer 17 exposed at the bottom of the contact hole 19. Next, the liner layer 17 exposed at the bottom of the contact hole 19 is removed by anisotropic dry etching. Further, ashing and APM (Ammonium hydroxide-hydrogen Peroxide Mixture) cleaning are performed to remove the polymer formed in the contact hole 19 by the dry etching. At this time, a silicide oxide layer 20 is formed on the surface of the metal silicide layer 16 exposed at the bottom of the contact hole 19. In the present embodiment, the silicide oxide layer 20 has a thickness of about 3 nm.

Subsequently, the silicide oxide layer 20 is removed by argon sputter etching. Here, the argon sputter etching is performed in a state where a high frequency power for plasma generation and a high frequency power for substrate bias are applied. For example, it can be performed under the condition that the substrate bias Vdc = 150V. In the present embodiment, part of the metal silicide layer 16 is removed together with the silicide oxide layer 20 in the etching step. In this case, the removal thickness is set in a range not exceeding 25 nm of the formation thickness of the metal silicide layer 16, and the area of the side wall of the contact hole 19 made of the metal silicide layer 16 is the contact hole 19 made of the metal silicide layer 16. Is set to be larger than the area of the bottom surface. Here, the metal silicide layer 16 is removed by 20 nm to leave a 5 nm metal silicide layer. Since the opening diameter R at the bottom of the contact hole 19 is smaller than the opening diameter (80 nm) at the upper end of the contact hole 19 (R <80 nm), when the metal silicide layer 16 is removed by 20 nm, the area of the side wall made of the metal silicide layer 16 (≈ .pi.R × 20) is larger than the area of the bottom surface of the contact hole ^{19 (= πR 2/4)} .

  Thereafter, the contact hole 19 is filled with a conductor made of a laminated film of titanium, a titanium nitride film, and a tungsten film, and then unnecessary conductors on the interlayer insulating film 18 are removed by the CMP method. As shown in FIG. 1C, a contact plug 21 is formed. Note that a blanket CVD method capable of embedding fine contact holes can be used for forming the tungsten film.

  As described above, in the present embodiment, in the etching for removing the silicide oxide layer 20, a part of the metal silicide layer 16 is removed at the same time. The contact area with the silicide layer 16 can be increased. Therefore, according to the present embodiment, the contact resistance of the fine contact structure can be reduced as compared with the conventional case.

  FIG. 2 is a diagram showing the relationship between the removal thickness of the metal silicide layer 16 formed with a film thickness of 25 nm and the contact resistance. Conventionally, since the contact plug is filled in the contact hole after removing only the silicide oxide layer 20, the contact removal value has a silicide removal amount of 0 nm. On the other hand, in the present embodiment, the silicide removal thickness is increased to 20 nm, so that the contact area between the contact plug 21 and the metal silicide layer 16 can be increased using the side wall made of the metal silicide layer 16. . As a result, the contact resistance can be lowered as shown in FIG.

  On the contact plug 21, an upper layer wiring or the like is formed. On the semiconductor substrate 11 on which the upper layer wiring is formed, an upper structure such as another wiring layer is formed as necessary, and the formation of the semiconductor device is completed.

  As described above, in the present embodiment, not only the silicide oxide layer 20 but also the metal silicide layer 16 therebelow is etched, and the area of the side wall made of the metal silicide layer 16 is larger than the area of the bottom surface made of the metal silicide layer 16. A large contact hole 19 is formed. For this reason, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased by effectively using the side wall made of the metal silicide layer 16, and the increase in contact resistance can be suppressed. As a result, even when a fine contact structure is formed, a low-resistance contact structure can be formed with a high yield.

(Second Embodiment)
FIG. 3 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention. In FIG. 3, the same reference numerals are assigned to parts that have the same action as the semiconductor device described in the first embodiment.

  In the present embodiment, as shown in FIG. 3A, the gate electrode 12 formed on the semiconductor substrate 11 via the gate insulating film 13 through the same process as that described in the first embodiment. Then, sidewall insulating films 14 and impurity regions 15 on both sides of the gate electrode 12 are formed. Similar to the first embodiment, the junction depth of the impurity region 15 is 70 nm.

  Next, as shown in FIG. 3B, nickel silicide as a metal silicide layer 16 is formed in a self-aligned manner with a film thickness of 25 nm on the surface of the impurity region 15 and the upper surface of the gate electrode 12 by a salicide process. . After the metal silicide layer 16 is formed, a liner layer 17 made of a silicon nitride film or the like is formed on the semiconductor substrate 11, and an interlayer insulating film 18 made of a silicon oxide film or the like is formed on the liner layer 17. A resist pattern (not shown) having an opening at a contact hole formation position is formed on the interlayer insulating film 18 whose upper surface is flattened by CMP or the like by a photolithography technique. The opening diameter of the resist pattern is about 80 nm.

  Subsequently, as in the first embodiment, a contact hole 19 is formed in the interlayer insulating film 18 by anisotropic etching using the resist pattern as a mask. Next, the liner layer 17 exposed at the bottom of the contact hole 19 is removed by anisotropic dry etching, and the polymer formed in the contact hole 19 by the dry etching is removed by ashing and APM cleaning. At this time, a silicide oxide layer 20 having a thickness of about 3 nm is formed on the surface of the metal silicide layer 16 exposed at the bottom of the contact hole 19 as in the first embodiment.

  Subsequently, the silicide oxide layer 20 is removed by argon sputter etching. Here, the argon sputter etching is performed in a state where a high frequency power for plasma generation and a high frequency power for substrate bias are applied. For example, it can be implemented under the condition that the substrate bias Vdc = 150V. In the present embodiment, unlike the first embodiment, the metal silicide layer 16 and a part of the impurity region 15 are removed together with the silicide oxide layer 20 in this step. The removal thickness in this case is set to a range that does not exceed 85% of the junction depth of the impurity region 15 while penetrating the metal silicide layer 16. This is because if it exceeds 85% of the junction depth, the junction leakage current increases significantly, which is not preferable. Here, since the junction depth of the impurity region 15 is 70 nm, the removal thickness in the etching step is set to 59.5 nm or less. The removal depth of the impurity region 15 after removing the metal silicide layer 16 is preferably at least 10 nm. This is because if the removal depth is 10 nm or less, the metal silicide layer 16 may not be completely removed due to removal variation in etching. Therefore, in the case of this embodiment, the removal thickness in the etching step is set in the range of 35 nm or more and 59.5 nm or less.

  Thereafter, as in the first embodiment, the contact hole 19 is filled with a conductor made of a laminated film of titanium, a titanium nitride film, and a tungsten film, and then unnecessary on the interlayer insulating film 18. The conductor is removed by the CMP method, and a contact plug 21 is formed as shown in FIG.

  As described above, in this embodiment, in the etching for removing the silicide oxide layer 20, the metal silicide layer 16 and a part of the impurity region 15 are simultaneously removed. For this reason, in the present embodiment, unlike the first embodiment, the contact plug 21 is in contact with the metal silicide layer 16 constituting the side wall of the contact hole 19 only on the side surface. However, in the case of a fine contact structure with a small opening diameter (for example, 80 nm or less), the structure is more compared with the conventional structure in which the contact plug is filled in the contact hole after removing only the silicide oxide layer 20. The contact area between the contact plug 21 and the metal silicide layer 16 is increased. This is because as the opening diameter of the contact hole becomes smaller, the area of the bottom surface of the contact hole becomes smaller and the contact area on the side wall of the contact hole becomes relatively larger. For example, when the planar shape of the contact hole is a circle, if the film thickness of the metal silicide layer 16 is not less than ¼ times the opening diameter of the bottom surface of the contact hole 19, the structure of this embodiment is the conventional structure. The contact area is larger than that. Therefore, according to the present embodiment, the contact resistance of the fine contact structure can be reduced as compared with the conventional case. If the area of the side wall made of the metal silicide layer 16 is at least larger than the area of the bottom surface made of the impurity region 15, the contact resistance becomes smaller than that of the conventional structure.

  On the contact plug 21, an upper layer wiring or the like is formed. On the semiconductor substrate 11 on which the upper layer wiring is formed, an upper structure such as another wiring layer is formed as necessary, and the formation of the semiconductor device is completed.

  As described above, in the present embodiment, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased by effectively using the side wall of the contact hole made of the metal silicide layer 16, and the contact resistance is increased. Can be suppressed. As a result, even when a fine contact structure is formed, a low-resistance contact structure can be formed with a high yield. Further, in this embodiment, since all the metal silicide layer exposed on the bottom surface of the contact hole is removed, the degree of freedom of the process control width is increased as compared with the configuration in which the metal silicide layer is slightly left as in the first embodiment. There is an advantage that you can.

(Third embodiment)
In the first and second embodiments, the configuration in which the metal silicide layer is formed from the surface of the semiconductor substrate to the predetermined depth of the impurity region has been described. In each of the above embodiments, the contact resistance can be reduced by increasing the thickness of the metal silicide layer. However, in recent semiconductor devices in which pattern miniaturization has progressed, since the junction depth of the impurity region is small, the metal silicide layer cannot be formed deep in the semiconductor substrate from the viewpoint of suppressing junction leakage current. . Therefore, in the present embodiment, a configuration in which the thickness of the metal silicide layer can be increased without forming the metal silicide layer deep in the semiconductor substrate will be described.

  FIG. 4 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention. In FIG. 4, the same reference numerals are assigned to the parts that exhibit the same functions as those of the semiconductor device described in the first and second embodiments.

  In the present embodiment, as shown in FIG. 4A, the gate electrode 12 formed on the semiconductor substrate 11 via the gate insulating film 13 through the same process as that described in the first embodiment. Then, sidewall insulating films 14 and impurity regions 15 on both sides of the gate electrode 12 are formed. The junction depth of the impurity region 15 is 70 nm.

  In the present embodiment, as shown in FIG. 4B, a polycrystalline silicon film 22 is formed on the semiconductor substrate 11 on which the impurity region 15 is formed by a selective epitaxial growth method. Here, a polycrystalline silicon film 22 having a thickness of 10 nm is formed on the gate electrode 12 and the impurity region 15.

  Next, as shown in FIG. 4C, a metal silicide layer 16 is formed on the surface of the polycrystalline silicon film 22 in a self-aligned manner by a known salicide process. Also in the present embodiment, nickel silicide is formed as the metal silicide layer 16 as in the first and second embodiments. However, in the present embodiment, since the polycrystalline silicon film 22 is deposited on the impurity region 15, the nickel silicide can be formed thicker than in the first and second embodiments. Here, the film thickness of nickel silicide is set to 35 nm.

  After the metal silicide layer 16 is formed, a liner layer 17 made of a silicon nitride film or the like is formed on the semiconductor substrate 11, and an interlayer insulating film 18 made of a silicon oxide film or the like is formed on the liner layer 17. A resist pattern (not shown) having an opening at a contact hole formation position is formed on the interlayer insulating film 18 whose upper surface is flattened by CMP or the like by a photolithography technique. The opening diameter of the resist pattern is about 80 nm.

  Subsequently, as in the first embodiment, a contact hole 19 is formed in the interlayer insulating film 18 by anisotropic etching using the resist pattern as a mask. Next, the liner layer 17 exposed at the bottom of the contact hole 19 is removed by anisotropic dry etching, and the polymer formed in the contact hole 19 by the dry etching is removed by ashing and APM cleaning. At this time, as in the first embodiment, a silicide oxide layer 20 having a thickness of about 3 nm is formed on the surface of the metal silicide layer 16 exposed at the bottom of the contact hole 19.

  Next, as in the first embodiment, the silicide oxide layer 20 and part of the metal silicide layer 16 are removed by argon sputter etching. Here, the argon sputter etching is performed in a state where a high frequency power for plasma generation and a high frequency power for substrate bias are applied. For example, it can be implemented under the condition that the substrate bias Vdc = 150V. Similar to the first embodiment, the thickness of the metal silicide layer 16 to be removed in this step is set in a range that does not exceed the formation thickness of 35 nm, and the area of the side wall of the contact hole 19 made of the metal silicide layer 16 is as follows. The area is set to be larger than the area of the bottom surface of the contact hole 19 made of the metal silicide layer 16. Here, the metal silicide layer 16 is removed by 30 nm to leave a 5 nm metal silicide layer.

  Thereafter, as in the first embodiment, the contact hole 19 is filled with a conductor made of a laminated film of titanium, a titanium nitride film, and a tungsten film, and then unnecessary on the interlayer insulating film 18. The conductor is removed by the CMP method, and the contact plug 21 is formed.

  As described above, in this embodiment, since the polycrystalline silicon film 22 is grown on the impurity region 15 by selective epitaxial growth, the metal silicide layer 16 is increased by the thickness of the polycrystalline silicon 22 without increasing junction leakage. Can be formed thick. That is, since the metal silicide layer 16 can be formed thick by the thickness of the polycrystalline silicon film 22, even when the metal silicide layer 16 is left with a thickness of 5 nm as in the first embodiment, the depth direction In addition, the contact area of the side wall composed of the contact plug 21 and the metal silicide layer 16 can be increased by a thickness of 10 nm. Therefore, according to the present embodiment, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased as compared with the first embodiment. As a result, the contact resistance of the fine contact structure can be further reduced.

  On the contact plug 21, an upper layer wiring or the like is formed. On the semiconductor substrate 11 on which the upper layer wiring is formed, an upper structure such as another wiring layer is formed as necessary, and the formation of the semiconductor device is completed.

  As described above, in this embodiment, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased as compared with the first embodiment without increasing the junction leakage. As a result, even when a fine contact structure is formed, a low-resistance contact structure can be formed with a high yield. In the above description, the configuration in which the bottom of the contact hole is located in the metal silicide layer has been described. However, as described in the second embodiment, the same applies to the configuration in which the contact hole penetrates the metal silicide layer. An effect can be obtained. In the above description, the polycrystalline silicon film is also formed on the gate electrode. However, it is not essential to form the polycrystalline silicon film on the gate electrode, and the polycrystalline silicon film only needs to be formed on the impurity region. . Note that the semiconductor layer that is selectively grown on the impurity region is not limited to a polycrystalline silicon film, but may be any material that can form a metal silicide layer by reaction with a refractory metal.

(Fourth embodiment)
In the third embodiment, the thickness of the metal silicide layer is increased without increasing the junction leakage current by selectively growing the semiconductor layer on the impurity region. However, the same effect can also be obtained when the impurity region is formed by a silicon germanium single crystal film. FIG. 5 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. In FIG. 5, the same reference numerals are assigned to the parts that exhibit the same functions as those of the semiconductor device described in the first to third embodiments.

  In this embodiment, as shown in FIG. 5A, a gate insulating film is formed with a thickness of several nm on the surface of a semiconductor substrate 11 made of single crystal silicon or the like on which element isolation (not shown) is formed. On the gate insulating film, a polysilicon film is formed with a thickness of about 120 nm. On the polysilicon film, a silicon oxide film is formed with a thickness of 40 nm, for example. By applying a known lithography technique and etching technique to the gate insulating film, the polysilicon film, and the silicon oxide film, two gate electrodes 12 are formed on the semiconductor substrate 11 via the gate insulating film 13, respectively. The In the present embodiment, each gate electrode 12 includes a cap insulating film 23 made of a silicon oxide film.

  After an impurity region (not shown) serving as an extension region is formed, an insulating film made of a silicon nitride film or the like is deposited on the semiconductor substrate 11 with a thickness of about 50 nm. By performing anisotropic etching on the insulating film, sidewall insulating films 14 are formed on both sides of the gate electrode 12.

  In the present embodiment, subsequently, as shown in FIG. 5B, the impurity region forming region on the surface of the semiconductor substrate 11 is removed by etching. The impurity region is an impurity region that functions as a source region or a drain region. The etching can be performed by, for example, chemical dry etching using the sidewall insulating film 14 and the cap insulating film 23 as a mask. FIG. 5B shows a state in which the recess 24 having a depth of about 60 nm is formed in the impurity region formation region by the etching. The material of the cap insulating film 23 may be any material that functions as a mask in the etching.

  Next, as shown in FIG. 5C, a silicon germanium single crystal film 25 containing an impurity having the same conductivity type as that of the extension region is formed in the recess 24 by a selective epitaxial growth method. For example, the germanium content is 20%. Here, a silicon germanium single crystal film 25 containing, for example, boron as an impurity is deposited with a thickness of 80 nm. As described above, since the depth of the recess 24 is about 60 nm, a part of the silicon germanium single crystal film 25 is formed so as to protrude upward from the surface of the semiconductor substrate 11. Since the cap insulating film 23 exists on the polysilicon film constituting the gate electrode 12, the silicon germanium single crystal film 25 does not grow on the gate electrode 12. When the deposition of the silicon germanium single crystal film 25 is completed, the cap insulating film 23 is removed by wet etching.

  Next, as shown in FIG. 5D, a metal silicide layer 16 is formed in a self-aligned manner on the surface of the silicon germanium single crystal film 25 and the upper surface of the gate electrode 12 by a known salicide process. In this embodiment, as in the third embodiment, nickel silicide is formed as a metal silicide layer 16 with a film thickness of 35 nm. In the present embodiment, the nickel silicide formed on the surface of the silicon germanium single crystal film 25 contains 20% germanium. After the metal silicide layer 16 is formed, a liner layer 17 made of a silicon nitride film or the like is formed on the semiconductor substrate 11, and an interlayer insulating film 18 made of a silicon oxide film or the like is formed on the liner layer 17. A resist pattern (not shown) having an opening at a contact hole formation position is formed on the interlayer insulating film 18 whose upper surface is flattened by CMP or the like by a photolithography technique. The opening diameter of the resist pattern is about 80 nm.

  Subsequently, as in the first embodiment, a contact hole 19 is formed in the interlayer insulating film 18 by anisotropic etching using the resist pattern as a mask. Next, the liner layer 17 exposed at the bottom of the contact hole 19 is removed by anisotropic dry etching, and the polymer formed in the contact hole 19 by the dry etching is removed by ashing and APM cleaning. At this time, as in the first embodiment, a silicide oxide layer 20 having a thickness of about 3 nm is formed on the surface of the metal silicide layer 16 exposed at the bottom of the contact hole 19.

  Next, as in the first embodiment, the silicide oxide layer 20 and part of the metal silicide layer 16 are removed by argon sputter etching. Here, the argon sputter etching is performed in a state where a high frequency power for plasma generation and a high frequency power for substrate bias are applied. For example, it can be implemented under the condition that the substrate bias Vdc = 150V. Similar to the first embodiment, the thickness of the metal silicide layer 16 to be removed in this step is set in a range that does not exceed the formation thickness of 35 nm, and the area of the side wall of the contact hole 19 made of the metal silicide layer 16 is as follows. The area is set to be larger than the area of the bottom surface of the contact hole 19 made of the metal silicide layer 16. Here, the metal silicide layer 16 is removed by 30 nm to leave a 5 nm metal silicide layer.

  Thereafter, as in the first embodiment, the contact hole 19 is filled with a conductor made of a laminated film of titanium, a titanium nitride film, and a tungsten film, and then unnecessary on the interlayer insulating film 18. The conductor is removed by the CMP method, and the contact plug 21 is formed as shown in FIG.

  As described above, in this embodiment, the impurity region is constituted by the recess 24 and the silicon germanium single crystal film 25 deposited by selective epitaxial growth. Further, between the gate electrodes 12, the upper surface of the silicon germanium single crystal film 25 is formed so as to protrude upward from the surface of the semiconductor substrate 11. Therefore, the metal silicide layer 16 can be formed as thick as the protruding silicon germanium single crystal film 25 without increasing junction leakage. Therefore, according to the present embodiment, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased as compared with the first embodiment. As a result, the contact resistance of the fine contact structure can be further reduced.

  On the contact plug 21, an upper layer wiring or the like is formed. On the semiconductor substrate 11 on which the upper layer wiring is formed, an upper structure such as another wiring layer is formed as necessary, and the formation of the semiconductor device is completed.

  As described above, in this embodiment, the contact area between the contact plug 21 and the metal silicide layer 16 can be increased as compared with the first embodiment without increasing the junction leakage. As a result, even when a fine contact structure is formed, a low-resistance contact structure can be formed with a high yield. In the above description, the configuration in which the bottom of the contact hole is located in the metal silicide layer has been described. However, as described in the second embodiment, the same applies to the configuration in which the contact hole penetrates the metal silicide layer. An effect can be obtained. The semiconductor layer selectively grown as the impurity region is not limited to a silicon germanium single crystal film, and a metal silicide layer can be formed by reaction with a refractory metal, and can be a material that can function as a source region or a drain region. I just need it.

  As described above, according to the present invention, the contact area between the metal silicide layer and the contact plug can be increased by effectively using the side wall of the contact hole. For this reason, even when a fine contact hole is formed, an increase in contact resistance can be suppressed.

  In addition, this invention is not limited to each embodiment mentioned above, A various deformation | transformation and application are possible in the range with the effect of this invention. For example, in each of the above embodiments, a case where the metal silicide layer is nickel silicide has been described as a particularly preferable case. However, as can be understood from each of the above-described embodiments, the present invention has an effect of increasing the contact area between the contact plug and the metal silicide layer as compared with the prior art. That is, the present invention can be applied to all semiconductor devices including contact plugs electrically connected to the metal silicide layer regardless of the material of the metal silicide layer. In addition, the processes described in the above embodiments can be replaced with known equivalent processes, and the materials of the respective parts exemplified in the embodiments can be replaced with known equivalent materials.

  The present invention has an effect that an increase in contact resistance can be suppressed even when a fine contact hole is formed, and is useful as a semiconductor device and a manufacturing method thereof.

Process sectional drawing which shows the manufacture process of the semiconductor device in the 1st Embodiment of this invention The figure which shows the relationship between the metal silicide removal thickness and contact resistance in the 1st Embodiment of this invention Process sectional drawing which shows the manufacture process of the semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the manufacturing process of the semiconductor device in the 3rd Embodiment of this invention Process sectional drawing which shows the manufacture process of the semiconductor device in the 4th Embodiment of this invention

Explanation of symbols

11 Semiconductor substrate 12 Gate electrode 13 Gate insulating film 14 Side wall insulating film 15 Impurity region (impurity layer)
16 Metal silicide layer 17 Liner layer 18 Interlayer insulating film (insulating film)
19 Contact hole 20 Silicide oxide layer 21 Contact plug (conductor)
22 Polycrystalline silicon film 23 Cap insulating film 24 Recess 25 Silicon germanium film

Claims (12)

An impurity layer formed on the surface portion of the semiconductor substrate;
A metal silicide layer formed from a surface of the impurity layer to a predetermined depth of the impurity layer;
An insulating film formed on the semiconductor substrate;
An opening that penetrates the insulating film and has a bottom reaching the metal silicide layer, and an area of a side wall made of the metal silicide layer is larger than an area of a bottom made of the metal silicide layer;
A conductor embedded in the opening and contacting the side wall and the bottom surface of the metal silicide layer;
A semiconductor device comprising: An impurity layer formed on the surface portion of the semiconductor substrate;
A metal silicide layer formed from a surface of the impurity layer to a predetermined depth of the impurity layer;
An insulating film formed on the semiconductor substrate;
An opening that penetrates the insulating film and the metal silicide layer and exposes the impurity layer on the bottom surface;
A conductor embedded in the opening and in contact with a sidewall made of the metal silicide layer and a bottom made of the impurity layer;
A semiconductor device comprising: A semiconductor layer formed on the impurity layer;
The semiconductor device according to claim 1, wherein the metal silicide layer is formed from a surface of the semiconductor layer to a predetermined depth of the impurity layer. A semiconductor layer formed on the impurity layer;
The semiconductor device according to claim 2, wherein the metal silicide layer is formed from a surface of the semiconductor layer to a predetermined depth of the impurity layer.   The impurity layer includes a recess formed in a surface portion of the semiconductor substrate, and a conductive semiconductor layer formed in the recess with an upper surface protruding upward from the surface of the semiconductor substrate. The semiconductor device according to claim 1.   The impurity layer includes a recess formed in a surface portion of the semiconductor substrate, and a conductive semiconductor layer formed in the recess with an upper surface protruding upward from the surface of the semiconductor substrate. The semiconductor device according to claim 2.   The semiconductor device according to claim 2, wherein an area of the side wall made of the metal silicide layer is larger than an area of a bottom surface made of the impurity layer.   The semiconductor device according to claim 1, wherein the opening is formed between gate electrodes formed on the surface of the semiconductor substrate via an insulating film. Forming an impurity layer on the surface of the semiconductor substrate;
Forming a metal silicide layer on the surface of the impurity layer;
Forming an insulating film on the semiconductor substrate on which the metal silicide layer is formed;
Forming an opening that penetrates through the insulating film so that a bottom portion reaches the metal silicide layer and an area of a side wall made of the metal silicide layer is larger than an area of a bottom surface made of the metal silicide layer;
Embedding a conductor in contact with the side wall and bottom surface of the metal silicide in the opening;
A method for manufacturing a semiconductor device, comprising: Forming an impurity layer on the surface of the semiconductor substrate;
Forming a metal silicide layer over a predetermined depth from the surface of the impurity layer;
Forming an insulating film on the semiconductor substrate on which the metal silicide layer is formed;
Forming an opening that penetrates the insulating film and the metal silicide layer and exposes the impurity layer on a bottom surface;
Burying a conductor in contact with the sidewall made of the metal silicide layer and the bottom made of the impurity layer in the opening;
A method for manufacturing a semiconductor device, comprising: A step of forming a semiconductor layer on the impurity layer between the formation of the impurity layer and the formation of the metal silicide layer;
11. The method of manufacturing a semiconductor device according to claim 9, wherein in the step of forming the metal silicide layer, a metal silicide layer is formed from a surface of the semiconductor layer to a predetermined depth of the impurity layer. Forming the impurity layer comprises:
Forming a recess in a surface portion of the semiconductor substrate;
Forming a semiconductor layer having conductivity in a state in which the upper surface protrudes above the surface of the semiconductor substrate in the recess;
The method for manufacturing a semiconductor device according to claim 9, comprising:

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