JP2004095903A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method for reducing a leak current in a source/drain region silicified by a salicide technique. <P>SOLUTION: The method for manufacturing the semiconductor device has steps of: forming a trench 4 in which the vicinity of a boundary between the wall surface and the surface of a substrate 1 is rounded as a curved surface to bury an insulating film in the trench; forming a gate electrode 11, an LDD region 12 and the side wall 13 of a gate electrode; processing the insulating film near the upper end of the trench 4 in a tapered manner so that the insulating film does not come into contact with the curved surface; forming a source/drain region 15 along the curved surface 1a; and forming a metal silicide 18 on the surface of the source/drain region containing the curved surface 1a so as to be self-adjusted in the source/drain region. Further, this semiconductor device is formed by this method. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a silicide on the surface of a source / drain region and a method of manufacturing the same, and more particularly, to a semiconductor device suitable for a logic circuit of a DRAM embedded logic LSI and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, a DRAM embedded logic LSI in which a DRAM memory circuit and a logic circuit are integrated into one chip has been actively researched and developed. The DRAM-embedded logic LSI is a high value-added LSI in which a DRAM memory and a logic function are integrated, and has an advantage that the number of chips mounted on an electronic product can be reduced.
[0003]
In a DRAM-embedded logic LSI, a silicide layer is formed in a source / drain region of a transistor of the logic circuit in a self-aligned manner in order to obtain a high-speed logic circuit (SALICIDE; self-aligned silicide). In this salicide technique, the side surface of the gate electrode is protected by a sidewall made of an insulating film such as a silicon nitride film, and the surface of the source / drain region is silicided. On the other hand, in the DRAM memory circuit, the surface of the source / drain region is not silicided, thereby suppressing junction leak and improving refresh characteristics.
[0004]
In a transistor of a logic circuit, a source / drain region contact is formed on silicide. On the other hand, a salicide technique is not applied to a DRAM memory circuit, and a bit line contact or the like is formed by a self-aligned contact technique to reduce the cell area.
[0005]
A conventional example of a DRAM embedded logic LSI will be described with reference to FIGS. FIG. 8A is a cross-sectional view showing a manufacturing process of the DRAM embedded logic LSI, and shows a state after the gate electrodes are formed in the DRAM memory circuit M and the logic circuit L, respectively.
[0006]
As shown in FIG. 8A, an element isolation region 102 is formed in a surface layer of a silicon substrate 101 by STI (shallow trench isolation). In the DRAM memory circuit M and the logic circuit L, gate electrodes 107M and 107L on which a gate oxide film 103, a polysilicon layer 104, a tungsten silicide layer 105, and an HTO (high temperature oxide) mask 106 are stacked, respectively, are formed. The width (gate length) of each of the gate electrodes 107M and 107L is, for example, 0.15 μm.
[0007]
Next, as shown in FIG. 9B, a silicon nitride film 108 is formed on the DRAM memory circuit M and the logic circuit L by chemical vapor deposition (CVD). Although not shown, before forming the silicon nitride film 108, impurity ions are implanted into the silicon substrate 101 of the DRAM memory circuit M using the gate electrode 107M as a mask to form source / drain regions. On the other hand, impurity ions are implanted into the silicon substrate 101 of the logic circuit L using the gate electrode 107L as a mask to form an LDD (lightly doped drain) region.
[0008]
Subsequently, in order to form a sidewall made of an insulating film on the gate electrode 107L of the logic circuit L, a resist 109 is formed on the DRAM memory circuit M or the like where no sidewall is formed.
Next, as shown in FIG. 9C, the silicon nitride film 108 is etched back to form a sidewall 110 on the side surface of the gate electrode 107L of the logic circuit L. After that, the resist 109 is removed. Although not shown, a self-aligned contact or the like is formed in the silicon nitride film 108 in the DRAM memory circuit M.
[0009]
In the step of forming the source / drain region of the logic circuit L and the step of silicidizing the source / drain region after the formation of the sidewall 110, the DRAM memory circuit M or the like which does not require these processes is protected by, for example, a resist. Keep it. Therefore, in the subsequent steps, only the logic circuit L is illustrated.
[0010]
As shown in FIG. 10D, after forming the side wall 110, ion implantation of impurities is performed using the side wall 110 as a mask to form a source / drain region 111. The lower part of the side wall 110 is an LDD region 112 containing impurities at a lower concentration than the source / drain region 111. Further, after a refractory metal layer such as a cobalt layer 113 is formed, a titanium nitride layer 114 is formed as a cap layer.
[0011]
Next, a first RTA (rapid thermal annealing) process is performed to form metal silicide (CoSi) in the source / drain region 111 in a self-aligned manner. Subsequently, the unnecessary metal layers (the cobalt layer 113 and the titanium nitride layer 114) remaining on the HTO mask 106, the sidewalls 110, and the element isolation regions 102, which are the insulating films, are removed using a mixed solution of sulfuric acid and hydrogen peroxide (sulfuric acid). Water).
[0012]
Thereafter, by performing a second RTA process, as shown in FIG. 10E, metal silicide (CoSi ₂ ) 115 is formed.
Next, as shown in FIG. 11F, after a silicon nitride film 116 is formed on the entire surface, an interlayer insulating film 117 is formed. A connection hole 118 reaching the metal silicide 115 is formed in the interlayer insulating film 117. In the connection hole 118, for example, a metal constituting an upper layer wiring is buried.
[0013]
As described above, techniques for mixing a DRAM memory circuit with a logic circuit include, for example, JP-A-11-3974, JP-A-11-97649, JP-A-11-163281, and JP-A-11-220036. It is disclosed in Japanese Unexamined Patent Publication No. Hei 11-340437 and Japanese Patent Laid-Open No. 2000-150665.
[0014]
[Problems to be solved by the invention]
However, according to the above-described conventional method of manufacturing a semiconductor device, as shown in FIGS. 10E and 11, the end of the silicon active layer, that is, the vicinity of the boundary between the source / drain region 111 and the element isolation region 102 is formed. , The metal silicide 115 is excessively formed, and the nodule-like silicide (CoSi ₂ ) 115a.
[0015]
In particular, when RTA is performed on the cobalt layer 113 at a relatively high temperature condition, for example, at 840 ° C. for 30 seconds, the silicide 115a in the form of a bump is easily formed. The bump-shaped silicide 115a is formed, for example, with a width of about 60 nm and a height of about 80 nm. Excessive silicidation at the edge of the silicon active layer is caused by the fact that the cobalt layer 113 is thick and the supply amount of cobalt is large, and that the silicon crystal grows at an edge other than the plane orientation (100) at the edge of the silicon active layer. It is believed to be due to.
[0016]
When such bump-like silicide 115a reaches the vicinity of the p / n junction at the interface between the source / drain region 111 and the surrounding semiconductor substrate 101, the leak current (junction leak) derived from the junction increases. . In the device of FIG. ⁺ Or n ⁺ The leakage current at the contact portion of the connection hole 118, which connects the mold source / drain region 111 and the first layer wiring thereon, increases.
[0017]
In particular, as shown in FIG. 11, in a borderless structure in which the metal of the upper layer wiring is directly connected to the source / drain region 111 (or the metal silicide 115), the leak current tends to increase, leading to a decrease in device performance and quality. . If the electrical characteristics of the logic circuit deteriorate, high quality cannot be realized even in the DRAM embedded logic LSI as a whole.
[0018]
The present invention has been made in view of the above problems, and accordingly, the present invention provides a semiconductor device capable of reducing a leak current in a source / drain region silicided by a salicide technique and a method of manufacturing the same. Aim.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate including an element formation region, and a groove formed in a surface layer of the semiconductor substrate so as to surround the element formation region, wherein a wall surface of the groove is provided. And the groove in which the vicinity of the boundary with the surface of the semiconductor substrate is a curved surface with rounded corners, and an insulating film embedded in the groove, only near the upper end of the groove so as not to contact the curved surface, The insulating film having a tapered cross section processed so as to be more distant from the element formation region upward, a gate electrode formed on a part of the element formation region via a gate insulating film, A self-aligned LDD region formed in a surface layer of the element formation region; a sidewall made of an insulating film formed on a side surface of the gate electrode; Border Along the curved surface, a source region and a drain region formed in a surface layer of the element forming region, and formed on the surface of the source region and the drain region including the curved surface in a self-aligned manner with the source region and the drain region. Metal silicide.
[0020]
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a groove in a surface layer of the semiconductor substrate so as to surround an element formation region that is a part of the semiconductor substrate, Processing the groove so that the vicinity of a boundary between the wall surface of the groove and the surface of the semiconductor substrate is a curved surface with rounded corners; embedding an insulating film in the groove; Forming a gate electrode through a gate insulating film, forming an LDD region in a surface layer of the element formation region in a self-aligned manner with the gate electrode, and forming a side surface of the gate electrode on a side surface of the gate electrode. A step of forming a wall; a step of processing the insulating film only in the vicinity of an upper end of the groove so as to be more away from the element formation region so that the insulating film is not in contact with the curved surface; Forming a source region and a drain region in the surface layer of the element forming region along the curved surface at the boundary with the groove in a self-aligned manner, and self-aligning with the source region and the drain region. Forming a metal silicide on the surface of the source region and the drain region including on a curved surface.
[0021]
Thus, excessive growth of silicide at the boundary between the source / drain region and the element isolation region can be suppressed. Therefore, leakage current due to excessive growth of silicide is suppressed, and a highly reliable circuit can be formed.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same of the present invention will be described with reference to the drawings. The following embodiment is an example of a transistor formed in a logic circuit of a DRAM embedded logic LSI.
[0023]
According to the method of manufacturing a semiconductor device of the present embodiment, first, as shown in FIG. 1A, a silicon nitride film 3 is formed on a device formation region of a silicon substrate 1 with a silicon oxide film 2 interposed therebetween. The silicon oxide film 2 reduces the difference in stress between the silicon substrate 1 and the silicon nitride film 3.
[0024]
The silicon oxide film 2 is formed by thermally oxidizing the surface of the silicon substrate 1. The silicon nitride film 3 is formed on the entire surface by low-pressure CVD (LP-CVD; low pressure CVD), and then etched using a resist as a mask to leave only on the element formation region.
[0025]
Subsequently, dry etching is performed on the silicon substrate 1 using the silicon nitride film 3 and the silicon oxide film 2 as masks to form trenches 4. At this time, the etching is continuously performed while changing the etching conditions in the middle, and the frontage 4a of the trench 4 is processed into a round shape.
[0026]
For example, using an inductively coupled plasma (ICP) type etching apparatus, first, etching is performed under the first etching condition, and the opening 3a of the silicon nitride film 3 is removed from the opening 3a of the silicon nitride film 3. 2a is in a more etched state. The first etching condition is, for example, that the gas flow rate is CHF ₃ / CF ₄ = 85/15 (sccm), pressure is 6.7 Pa, ICP source power is 600 W, bias power is 300 W, and substrate temperature is 60 ° C.
[0027]
Next, the trench 4 is formed by performing anisotropic etching on the silicon substrate 1 under the second etching condition. Under the second etching condition, the frontage 4a of the trench 4 is not processed into a round shape. The second etching condition is, for example, a gas flow rate of HBr / O ₂ = 190/10 (sccm), pressure 2Pa, ICP source power 600W, bias power 200W, substrate temperature 60 ° C.
[0028]
Next, the silicon substrate 1 is etched under the third etching condition having lower anisotropy than the second etching condition, and the opening 4a of the trench 4 is processed into a round shape. The third etching condition is, for example, that the gas flow rate is Cl ₂ / O ₂ = 150/10 (sccm), pressure is 6.7 Pa, ICP source power is 600 W, bias power is 300 W, and substrate temperature is 60 ° C. By the continuous processing as described above, the trench frontage 4a is processed into a round curved surface having a radius of curvature of about 60 nm.
[0029]
As described above, a method in which an insulating film on a silicon substrate is formed into an inversely tapered shape, etching is performed using this as a mask, and the etching condition is changed in the middle to form a trench opening with a round shape is disclosed in, for example, 2000-299374.
Also, Japanese Patent Application Laid-Open No. 2000-200829 discloses a method in which a silicon substrate is etched by using a mask having an inversely inclined shape that spreads outward as the distance from the silicon substrate increases, thereby making the upper portion of the trench circular.
[0030]
In addition to the above, a method of making the trench frontage round is known. For example, Japanese Patent Application Laid-Open No. 2000-22141 discloses that a first etching is performed under the condition that a large amount of deposits are formed on the side surface of the etching mask, and then a second etching that does not generate a deposit is performed. A loosening method is disclosed.
In the present embodiment, the trench frontage can be rounded by these known methods.
[0031]
In the above JP-A-2000-299374, JP-A-2000-200829 and JP-A-2000-22141, the trench front is rounded in order to reduce the electric field concentration at the silicon corner in contact with the trench front. It is not shown that the silicon surface is silicided or that the silicidation excessively proceeds at the corners of the silicon.
[0032]
Although not shown, in the DRAM memory circuit of the DRAM embedded logic LSI, the trench opening does not necessarily need to be processed in a round shape as described above. If the trench front is not processed in a round shape in the DRAM memory circuit, the DRAM memory circuit portion is covered with a resist, and the above-described trench is formed in the logic circuit portion. Alternatively, the trench of the DRAM memory circuit portion may be formed in parallel with the logic circuit portion, and the trench opening may have a round shape. In this case, local electric field concentration is suppressed at the silicon in contact with the trench opening.
[0033]
Next, as shown in FIG. 1B, after the silicon nitride film 3 and the silicon oxide film 2 are removed, the entire surface including the inside of the trench 4 is subjected to silicon oxide by high-density plasma (HDP) type CVD. A film 5 is deposited.
Next, as shown in FIG. 2C, the excess silicon oxide film 5 on the silicon substrate 1 is removed by chemical mechanical polishing (CMP), and the surface is flattened. Thereby, an element isolation region 6 is formed in the trench 4.
[0034]
Next, as shown in FIG. 2D, a gate electrode 11 having a structure in which a gate oxide film 7, a polysilicon layer 8, a tungsten silicide layer 9, and an HTO mask 10 are stacked on an element formation region of the silicon substrate 1 is formed. Form. The gate electrode 11 is formed by forming a gate oxide film 7 on the silicon substrate 1 by thermal oxidation or CVD, and then sequentially stacking a polysilicon layer 8, a tungsten silicide layer 9 and an HTO mask 10 on the entire surface by CVD, and using a resist as a mask. Is formed by etching each layer. Thereafter, an impurity is ion-implanted into the silicon substrate 1 using the gate electrode 11 as a mask to form an LDD region 12.
[0035]
Next, as shown in FIG. 3E, a sidewall 13 is formed on the gate electrode 11. The sidewalls 13 are formed by forming an insulating film such as a silicon nitride film on the entire surface and then performing etch back of the insulating film.
Further, a resist 14 having an opening at a boundary between the element isolation region 6 and the LDD region 12 is formed. The opening of the resist 14 is formed at a position exposed from the boundary between the element isolation region 6 and the LDD region 12 by about 60 nm on the element isolation region 6 side and about 20 nm on the LDD region 12 side.
[0036]
Next, as shown in FIG. 3F, anisotropic processing by dry etching is performed on the silicon oxide film in the element isolation region 6 using the resist 14 as a mask. For example, a two-frequency excitation parallel plate type RIE (reactive ion etching) apparatus is used for the etching. ₄ F ₈ / CO / Ar / O ₂ = 15/100/200/5 (sccm), pressure 5.3 Pa, upper electrode power 2000 W, lower electrode power 1200 W, electrode spacing 20 mm, substrate temperature 0 ° C.
[0037]
Thereby, the oxide film of the element isolation region 6 is anisotropically processed so that the taper angle (the angle between the side surface S and the surface of the silicon substrate 1) is, for example, 88 °. By setting the taper angle at about 84 to 90 °, it is possible to prevent silicide from growing like a bump in the subsequent step.
[0038]
Further, a silicon surface 1a having a round cross section is exposed at a boundary portion with the trench frontage 4a. The amount of recession of the silicon oxide film in the element isolation region 6 due to this etching is as small as 5 nm or less at maximum, so that the influence on the transistor characteristics can be ignored.
[0039]
In the subsequent steps, only one side of the gate electrode 11 among the transistors of the logic circuit is illustrated in an enlarged manner. After etching the boundary between the element isolation region 6 and the LDD region 12, the resist 14 is removed and impurities are ion-implanted into the silicon substrate 1 using the sidewalls 13 as a mask, as shown in FIG. Then, source / drain regions 15 are formed. At this time, the source / drain regions 15 are also formed along the round shape on the silicon surface 1a near the boundary with the element isolation region 6.
[0040]
Next, as shown in FIG. 5H, a high melting point metal layer such as a cobalt layer 16 is formed to a thickness of 10 nm, and then a titanium nitride layer 17 is formed to a thickness of 30 nm as a cap layer. Here, in the trench frontage 4a, the silicon active layer (source / drain region 15) has a rounded cross-sectional shape, and the end of the silicon oxide film in the element isolation region 6 is anisotropically tapered. Therefore, a step having a depth of about 50 nm is formed.
[0041]
In this step portion, the step coverage of the cobalt layer 16 and the titanium nitride layer 17 is low, and the film thickness in the step portion is about 30% of the film thickness in the flat portion. Specifically, the thickness of the cobalt layer 16 on the rounded silicon surface 1a is at least about 3 nm, and the thickness of the titanium nitride layer 17 is at least about 9 nm. In the case where the film thickness is reduced to about 30% at the step portion, the growth of the nodular silicide at the edge of the silicon active layer can be suppressed. The step coverage of the step can be controlled by adjusting the taper angle of the side surface of the silicon oxide film in the element isolation region 6 in the step shown in FIG.
[0042]
Next, a first RTA process is performed to form metal silicide (CoSi) in the source / drain region 15 in a self-aligned manner. The first RTA process is performed, for example, at 500 ° C. for 30 seconds.
Subsequently, unnecessary metal layers (the cobalt layer 16 and the titanium nitride layer 17) remaining on the HTO mask 10, the sidewalls 13, and the element isolation regions 6 which are the insulating films are removed by using a sulfuric acid / hydrogen peroxide mixture.
[0043]
Thereafter, by performing a second RTA process, as shown in FIG. 6I, metal silicide (CoSi ₂ ) 18 is formed. The second RTA process is performed, for example, at 850 ° C. for 30 seconds.
Here, since the cobalt layer 16 and the titanium nitride layer 17 are formed thin on the rounded silicon surface 1a (see FIG. 5) of the silicon active layer, the supply amount of cobalt for the silicidation reaction is relatively small. Thereby, excessive silicide (CoSi) near the trench frontage 4a is formed. ₂ ) Is suppressed. The metal silicide 18 is formed with a uniform thickness of about 35 to 40 nm on the source / drain region 15 including the round silicon surface 1a.
[0044]
According to the conventional structure and manufacturing method, as shown in FIG. When the RTA temperature is lowered to suppress the growth of the silicide 115a in the form of a knob, CoSi is changed from CoSi to CoSi. ₂ Reaction may not easily proceed, and the resistance of the source / drain region may not be sufficiently reduced.
[0045]
On the other hand, according to the present embodiment, if the heating is performed up to about 850 ° C., the formation of nodular silicide can be suppressed. Therefore, as compared with the conventional manufacturing method, the temperature of the second RTA process can be set in a wider range, and CoSi can be changed to CoSi. ₂ Reaction can proceed sufficiently. Here, the lower limit of the temperature of the second RTA process is preferably about 700 ° C. When the temperature of the second RTA process falls below 700 ° C., CoSi ₂ Is difficult to grow uniformly on the surface of the silicon active layer.
[0046]
Thereafter, as shown in FIG. 7J, a silicon nitride film 19 is formed on the entire surface, and then an interlayer insulating film 20 is formed. As the interlayer insulating film 20, for example, a silicon oxide film is formed by CVD. The interlayer insulating film 20 is etched using a resist (not shown) as a mask to form a connection hole 21. Although not shown, a contact is formed by filling the connection hole 21 with a conductor such as a metal. It is also possible to bury the connection hole 21 with a metal constituting an upper layer wiring.
[0047]
According to the structure of the semiconductor device of the present embodiment described above, the source / drain regions 15 are uniformly formed on the round silicon surface 1a at the boundary with the element isolation region 6. Therefore, even when the connection hole 21 having a borderless structure is formed on the metal silicide 18 at the boundary with the element isolation region 6 so that the upper layer wiring is directly connected, the local region of the metal silicide 18 and the source / drain region 15 can be locally formed. Unnecessary loss and thinning are prevented. Further, the metal silicide 18 does not reach the p / n junction between the source / drain region 15 and the surrounding silicon substrate 1. Therefore, the junction leak does not increase.
[0048]
For example, in the conventional structure shown in FIG. 11F, a connection hole 118 having a borderless structure is formed, but the structure shown in FIG. 11F has an area of 80,000 μm. ² Leakage current when applying 1.5 V to the TEG connected borderless to the PSD is 1.0 × 10 ^-7 (A) It reaches above.
[0049]
On the other hand, in the structure of the present embodiment, the leakage current of the corresponding portion was measured under the same measurement conditions as in the above-described conventional example. ^-9 (A) It was an order. That is, according to the structure of the present embodiment, the junction leak is significantly reduced. Further, by forming the transistor of this embodiment in a logic circuit, a highly reliable DRAM embedded logic LSI can be obtained.
[0050]
Embodiments of the semiconductor device and the method for manufacturing the same of the present invention are not limited to the above description. For example, in the above embodiment, silicide is formed using a cobalt layer, but a metal such as titanium may be used instead of cobalt.
Further, without forming the tungsten silicide layer 9 on the polysilicon layer 8, the HTO mask 10 is removed before the source / drain region 15 is silicided, and the gate is formed in the step of silicidizing the source / drain region 15. Silicide may be formed on the electrode 11 in a self-aligned manner.
In addition, various changes can be made without departing from the spirit of the present invention.
[0051]
【The invention's effect】
According to the semiconductor device and the method of manufacturing the same of the present invention, it is possible to reduce the leak current in the source / drain regions silicided by the salicide technique.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.
FIGS. 2 (c) and 2 (d) are cross-sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to the present invention, showing a step following FIG. 1 (b).
FIGS. 3 (e) and 3 (f) are cross-sectional views showing the manufacturing steps of the method for manufacturing a semiconductor device according to the present invention, and show the steps subsequent to FIG. 2 (d).
FIG. 4 (g) is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device of the present invention, and shows a step following FIG. 3 (f).
FIG. 5 (h) is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention, and shows a step following FIG. 4 (g).
FIG. 6 (i) is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device of the present invention, and shows a step following FIG. 5 (h).
FIG. 7 (j) is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device of the present invention, and shows a step following FIG. 6 (i).
FIG. 8A is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.
9 (b) and 9 (c) are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a semiconductor device, and show a step following FIG. 8 (a).
10 (d) and 10 (e) are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a semiconductor device, and show a step following FIG. 9 (c).
FIG. 11 (f) is a cross-sectional view showing a manufacturing step in a conventional method of manufacturing a semiconductor device, and shows a step following FIG. 10 (e).
[Explanation of symbols]
REFERENCE SIGNS LIST 1 silicon substrate, 1a rounded silicon surface, 2 silicon oxide film, 2a opening, 3 silicon nitride film, 3a opening, 4 trench, 4a trench opening, 5 silicon oxide film, 6 ... Element isolation region, 7 gate oxide film, 8 polysilicon layer, 9 tungsten silicide layer, 10 HTO mask, 11 gate electrode, 12 LDD region, 13 sidewall, 14 resist, 15 source / Drain region, 16: cobalt layer, 17: titanium nitride layer, 18: metal silicide (CoSi ₂ ), 19: silicon nitride film, 20: interlayer insulating film, 21: connection hole, 101: silicon substrate, 102: element isolation region, 103: gate oxide film, 104: polysilicon layer, 105: tungsten silicide layer, 106 ... HTO mask, 107M, 107L gate electrode, 108 silicon nitride film, 109 resist, 110 sidewall, 111 source / drain region, 112 LDD region, 113 cobalt layer, 114 titanium nitride layer, 115 Metal silicide, 116: silicon nitride film, 117: interlayer insulating film, 118: connection hole.

Claims (4)

A semiconductor substrate including an element formation region;
A groove formed on the surface layer of the semiconductor substrate so as to surround the element forming region, wherein the groove near the boundary between the wall surface of the groove and the surface of the semiconductor substrate has a curved surface with rounded corners;
An insulating film embedded in the groove, the insulating film having a tapered cross-section processed so as not to be in contact with the curved surface, only near the upper end of the groove, so as to be further away from the element formation region upward;
A gate electrode formed on a part of the element formation region via a gate insulating film; an LDD (lightly doped drain) region formed in a surface layer of the element formation region in a self-aligned manner with the gate electrode;
A sidewall made of an insulating film formed on a side surface of the gate electrode;
A source region and a drain region formed in a surface layer of the element formation region in a self-alignment with the sidewall and along the curved surface at a boundary with the groove;
And a metal silicide formed on the surface of the source region and the drain region including the curved surface in a self-aligned manner with the source region and the drain region. 2. The semiconductor device according to claim 1, further comprising the same metal silicide on the gate electrode as the surface of the source region and the drain region. Forming a groove in a surface layer of the semiconductor substrate so as to surround an element formation region which is a part of the semiconductor substrate, wherein a curved surface having a rounded corner near a boundary between a wall surface of the groove and a surface of the semiconductor substrate; Processing the groove so that
Burying an insulating film in the groove;
Forming a gate electrode on a part of the element formation region via a gate insulating film;
Forming an LDD region in a surface layer of the element forming region in a self-aligned manner with the gate electrode;
Forming a sidewall made of an insulating film on a side surface of the gate electrode;
Processing the insulating film in a taper shape so that only the upper end of the groove is separated from the element formation region as it goes upward, so that the insulating film does not contact the curved surface;
Forming a source region and a drain region in a surface layer of the element formation region in a self-alignment with the sidewall and along the curved surface at a boundary with the groove;
Forming a metal silicide on the surface of the source and drain regions including on the curved surface in a self-aligned manner with the source and drain regions. 4. The method according to claim 3, wherein in the step of forming metal silicide on the surface of the source region and the drain region, a metal silicide is formed also on the gate electrode.

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