JP2008140977A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the dimensional precision of gate processing in the semiconductor device using MISFETs having gate electrodes of different heights. <P>SOLUTION: With respect to a method for manufacturing semiconductor devices, an opening is so formed that its side wall SW becomes the form of a forward taper, in a portion present on a first insulating film GI1 and present in a first conductive film GM1 which are deposited on a semiconductor substrate 1. By forming a spacer SP1 on the surface of the side wall SW, the steep level difference of the opening is reduced. Thereafter, a second gate insulating film GI1, a second conductive film GM2 whose thickness is different from that of the first insulating film GI1 and the first conductive film GM1 are deposited. After successively applying a bark 3 and a photoresist 4 to the second conductive film GM2, first gate electrodes G1 of a memory array forming region M are formed by photolithography processing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to the manufacture of a semiconductor device having MIS field effect transistors (MISFETs) having different gate heights (hereinafter, MISFET: Metal Insulator Semiconductor Field Effect Transistor). It is.

  A memory cell structure using a MONOS (Metal Oxide Nitride Oxide Semiconductor) stacked structure is known as a kind of nonvolatile memory capable of electrically rewriting data.

  The MONOS type nonvolatile memory performs writing by injecting charges into the silicon nitride film (Nitride) in the stacked structure. The two-layered silicon oxide film (Oxide) sandwiching the silicon nitride film serves as a potential barrier, preventing the injected charge from escaping to the semiconductor substrate (Semiconductor) or electrode (Metal), thus maintaining the charge accumulation state. It has the feature of being. The MONOS type nonvolatile memory has an advantage that it has excellent data retention reliability and can operate with a low write / erase voltage.

  A method for manufacturing a MONOS type nonvolatile memory is disclosed in, for example, Japanese Patent Laid-Open No. 2006-156626 (Patent Document 1).

  On the other hand, semiconductor integrated circuits in which the above-described semiconductor nonvolatile memory cells are mixedly mounted on the same substrate as the logic circuit for logic are widely used in industrial equipment, home appliances, automobile mounting devices, etc. as programmable embedded microcomputers. It's being used.

  The memory / logic mixed integrated circuit as described above includes a memory area including a nonvolatile memory cell capable of storing data in a rewritable state, and a logic area including a peripheral circuit for performing memory control and logical operation. Is characterized by being mounted on one chip.

  For example, Japanese Unexamined Patent Application Publication No. 2006-54292 (Patent Document 2) describes a technique for forming a memory region including a MONOS type nonvolatile memory cell and a logic circuit region on the same substrate.

In a memory / logic mixed integrated circuit, in addition to a MISFET used in a nonvolatile memory cell, a high voltage MISFET for memory control and a low voltage MISFET for a high performance logic circuit are integrated on the same semiconductor chip. This means that the memory area and the logic area have MISFETs having different characteristics. That is, the memory / logic mixed integrated circuit has a unique manufacturing process in which MISFETs having different shapes are separately formed on one chip.
JP 2006-156626 A JP 2006-54292 A

  The present inventor has found that there are the following problems when manufacturing a semiconductor device having MISFETs having different gate electrode heights in the memory region and the logic region.

  In the memory region, a MISFET having a wide gate width and a long gate length may be used as compared with a MISFET in the logic region. Such a MISFET has a high gate height due to its scaling law. That is, the semiconductor device as described above has a feature that a MISFET having a gate electrode higher than that of the MISFET in the logic region is used in the memory region.

  FIG. 1 and FIG. 2 show a general method for separately creating MISFETs having different gate heights in the memory area and the logic area.

  As shown in FIG. 1A, on the semiconductor substrate 1, a region for forming a memory cell array MISFET is M (memory array forming region), and a region for forming peripheral logic is L (logic circuit forming region). In the logic circuit formation region L, each active region 10a isolated by STI (Shallow Trench Isolation) 2 formed by trench isolation is provided, and a logic MISFET is formed therein. Here, a process of forming a higher gate electrode in the memory array formation region M as compared with the logic circuit formation region L will be described.

  First, as shown in FIG. 1B, a first gate insulating film GI1 made of silicon oxide and a first gate conductive film GM1 made of polycrystalline silicon are sequentially deposited, and then deposited in the memory array formation region M of the deposited film. The opening 10b is formed by photolithography. Subsequently, as shown in FIG. 1C, a second gate insulating film GI2 made of silicon oxide and a second gate conductive film GM2 made of polycrystalline silicon are sequentially deposited. The total thickness of the second gate insulating film GI2 and the second gate conductive film GM2 deposited here is larger than the total thickness of the first gate insulating film GI1 and the first gate conductive film GM1 previously deposited. So as to deposit.

  Next, as shown in FIG. 2A, a base antireflection film (hereinafter referred to as BARC) 3 and a photoresist 4 are applied by spin coating for photolithography processing. To do. Then, as shown in FIG. 2B, the second gate conductive film GM2 and the second gate insulating film GI2 in the memory array formation region M are processed, and the first gate electrode G1 is formed in the memory array formation region M. Thereafter, as shown in FIG. 2C, the first gate conductive film GM1 and the first gate insulating film GI1 in the logic circuit formation region L are photolithography processed to form the second gate electrode G2 in the logic circuit formation region L. To do.

  Here, the problem found by the present inventors is caused by a steep step at the boundary between the logic circuit formation region L and the memory array formation region M.

  As described above, in the case of the technique studied by the present inventor, a conductive film for a gate electrode (hereinafter referred to as a logic gate conductive film) of a MISFET that forms a logic circuit on the main surface of the semiconductor substrate 1 in the logic circuit formation region L. First, a pattern is formed. That is, as shown in FIG. 1B, the logic circuit formation region L and the memory are already formed in a stage before depositing a gate electrode conductive film (hereinafter referred to as a memory gate conductive film) of the MISFET forming the memory. A step S1 corresponding to the gate conductive film thickness for logic is generated at the boundary with the array formation region M.

  For this reason, when the memory gate conductive film is deposited, a base step as shown in FIG. 1C is reflected at the boundary between the logic circuit formation region L and the memory array formation region M on the surface of the conductive film. The steep step S2 is formed. For this reason, when the bark 3 and the photoresist 4 are applied by spin coating in order to pattern the gate conductive film for memory, the thickness of the bark 3 is increased at the step S2 as indicated by the indicator 100 in FIG. It becomes relatively thin. When exposure processing is performed in this state, in addition to the formation of the steep step S2, the thin portion of the antireflection bark 3 is partially present. As a result, the incident exposure light LP1 is diffusely reflected at the step portion (hereinafter referred to as the stepped portion). , Described as halation). The portion of the photoresist that is originally not exposed to the reflected exposure light LP2 is exposed, and the gate electrode for the memory around the step S2 becomes thinner than the other gate electrodes of the same memory circuit. There is a problem.

  Up to now, the present inventor has selectively removed the memory gate conductive film deposited in the logic circuit formation region L before processing the memory array formation region M, so that the steep portion in the indication unit 100 in FIG. The halation due to a large step was avoided. However, an increase in the number of masks due to the introduction of such a photolithography process leads to an increase in manufacturing cost.

  An object of the present invention is to provide a technique capable of improving the processing dimensional accuracy of a gate electrode in a method for manufacturing a semiconductor device having MISFETs having different gate heights on the same semiconductor substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, an opening is formed in a part of the first insulating film and the first conductive film deposited on the semiconductor substrate so that the side wall has a forward taper shape, and a spacer is formed on the side wall surface. By depositing the second insulating film and the second conductive film so as to be thicker than the total thickness of the first insulating film and the first conductive film, and then patterning the second conductive film and the second insulating film The method includes a step of forming a second gate electrode by patterning the first gate electrode and the first conductive film and the first insulating film, respectively.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the step of leaving the first conductive film deposited on the semiconductor substrate in the first region and opening the second region, the side wall of the opening is formed in a forward taper shape, whereby a semiconductor device having a MISFET with different gate heights is formed. The processing dimensional accuracy of the gate electrode can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of modifications, details, detailed explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A manufacturing method of the MONOS type semiconductor nonvolatile memory / peripheral logic mixed integrated circuit according to the present embodiment will be described in the order of steps with reference to FIGS. In all the drawings, on a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of single crystal silicon, an area for forming a memory cell array is M (memory array formation area), and an area for forming peripheral logic is L (logic circuit formation area). ).

  First, as shown in FIG. 3, each active region 10 a that is isolated by an element isolation STI 2 made of silicon oxide or the like formed by a trench isolation method is formed on the main surface of the semiconductor substrate 1. Thereafter, a first gate insulating film (first insulating film) GI1 made of silicon oxide and a first gate conductive film (first conductive film) GM1 made of polycrystalline silicon are sequentially deposited. These have a film thickness required for the performance of the gate electrode of the MISFET necessary for forming the logic circuit. Thereafter, the deposited films GM1 and GI1 in the memory array formation region M are selectively removed, and the memory array formation region M is opened.

  At this time, as shown in FIG. 3A, the sidewall SW of the opening is processed into a so-called forward taper shape in which the opening widens from the surface of the semiconductor substrate 1 upward.

  After the above process, as shown in FIG. 3B, a silicon oxide I3 having a thickness that completely covers the step composed of the sidewall SW is deposited by a chemical vapor deposition (CVD) method. Subsequently, as shown in FIG. 3C, the silicon oxide film I3 is etched back to form a first spacer (spacer) SP1 on the side wall of the side wall SW.

  Subsequently, as shown in FIG. 4A, a second gate insulating film (second insulating film) GI2 made of silicon oxide and a second gate conductive film (second conductive film) GM2 made of polycrystalline silicon are deposited. . These have film thicknesses required for the performance of the control gate electrode constituting the MONOS type nonvolatile memory. At this time, the first conductive film GM1 and the first insulating film GI1 including the first spacer SP1 formed on the surface of the forward tapered side wall SW are buried under these deposited films in the logic circuit formation region L. It has a structure.

  Here, the total thickness of the second gate insulating film GI2 and the second gate conductive film GM2 serving as the control gate for the MONOS type memory is the first gate insulating film serving as the gate electrode of the MISFET for logic circuit deposited in the previous step. The film is deposited to be thicker than the total film thickness of GI1 and the first gate conductive film GM1.

  Subsequently, as shown in FIG. 4B, the second gate conductive film GM <b> 2 is covered with a photoresist 4 via a bark 3. Thereafter, as shown in FIG. 4C, the second gate conductive film GM2 in the memory array formation region M is processed by a photolithography method into a size corresponding to the control gate width of the MONOS type nonvolatile memory. Therefore, at this time, the second gate insulating film GI2 is exposed in other portions (not shown). Then, using the remaining photoresist (not shown) as a mask, impurities are doped by ion implantation to form an impurity diffusion region 5a that becomes a channel region of the memory gate MG of the MONOS type memory formed in a later step. The ion species to be implanted depends on the polarity of the impurity diffusion region to be formed. For example, if an n-type region is to be formed, ions of group V or group VI elements are doped. The same applies to ion species at the time of ion implantation in subsequent impurity diffusion steps.

  Next, the exposed portion of the second gate insulating film GI2 is removed by etching to form the first gate electrode G1. And the structure after removing the remaining bark 3 and the photoresist 4 is FIG.4 (c). The first gate electrode G1 will later become a control gate of the MONOS type memory.

  Subsequently, as shown in FIG. 5A, a laminated insulating film ONO (silicon oxide film / silicon nitride film (nitride) having a structure in which a silicon nitride film serving as a charge storage layer of a MONOS type memory is sandwiched between barrier layers. ) / Silicon oxide film (oxide)) is deposited by CVD. Here, the lower silicon oxide film may be formed on the semiconductor substrate 1 by an ISSG (In-Situ Steam Generation) oxidation method. Further, the upper silicon oxide film can be formed on the silicon nitride film by the ISSG oxidation method.

  Next, as shown in FIG. 5B, a memory gate MG for injecting charges into the stacked insulating film ONO is formed on the side wall of the first gate electrode G1 formed in the memory array formation region M. The memory gate MG is formed by depositing polycrystalline silicon by CVD so as to sufficiently cover the first gate electrode G1, and etching back the polycrystalline silicon and the laminated insulating film ONO below the first gate electrode. G1 side wall spacers are formed. Further, after the etch back, the two first gate electrodes G1 are paired, and the memory gate and the laminated insulating film ONO formed so as to face each other are selectively removed by photolithography, as shown in FIG. 5B. It becomes the structure shown.

  Next, as shown in FIG. 5C, by patterning the first gate conductive film GM1 and the first gate insulating film GI1 in the logic circuit formation region L by a normal photolithography method, the first MISFET for logic is formed. A two-gate electrode G2 is formed. At this time, as indicated by the boundary between the logic circuit formation region L and the memory array formation region M in the same figure, a so-called dummy gate G21 that does not function as a MISFET and is derived from the side wall SW provided with the first spacer SP1 is provided. Will remain. Then, the surface of the semiconductor substrate 1 on both sides of the memory first gate electrode G1 having the memory gate MG and the semiconductor substrate on both sides of the second gate electrode G2 of the peripheral logic MISFET via the stacked insulating film ONO for charge storage. Impurity diffusion regions 5b and 6a are formed on each of the surfaces by doping impurities by ion implantation. Since these require different performances for logic and memory, they are formed separately using a photoresist (not shown) or the like as a mask. The impurity diffusion region 5b of the memory array formation region M has the same polarity as the impurity diffusion region 5a and has a higher concentration than the impurity diffusion region 5a.

  Subsequently, as shown in FIG. 6A, a second spacer SP2 made of an insulator is formed on the sidewalls of the first gate electrode G1, the second gate electrode G2, and the memory gate MG formed in each region. These are formed by depositing an insulating film on the substrate surface by a CVD method or the like and etching back. For example, a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film or the like is used as the insulating film for the second spacer SP2. Then, in order to form a contact region between an element such as a MONOS type memory or a MISFET formed in the process so far and a wiring to be formed later, an impurity is doped by an ion implantation method, and the impurity diffusion regions 5c and 6b are formed as follows. They are formed in the memory array formation region M and the logic circuit formation region L, respectively. These are doped at a higher concentration than the impurity diffusion regions 5a, 5b and 6a formed in the previous process. The impurity diffusion region 5c in the memory array formation region M has the same polarity as the impurity diffusion regions 5a and 5b, and the impurity diffusion region 6b in the logic circuit formation region L has the same polarity as the impurity diffusion region 6a.

  In the next step, as shown in FIG. 6B, first, a silicide layer is formed for the purpose of ohmic connection between each element and the wiring. A metal (for example, cobalt) to be silicided is deposited on the substrate surface in the state of FIG. 6A by sputtering. By performing heat treatment in this state, the surfaces of the impurity diffusion regions 5c and 6a in which silicon and metal are in contact with each other without the insulating film, the surfaces of the first and second gate electrodes G1 and G2, and the surface of the memory gate MG Then, silicides (7a, 7b and 7c, respectively) are formed. Thereafter, a silicon nitride film is deposited as an insulating protective film I4 over the entire substrate surface by the CVD method. Then, a silicon oxide film is deposited by the CVD method as the interlayer insulating film I5 of the wiring layer to be formed on the substrate.

  Subsequently, as shown in FIG. 6C, after forming a contact hole in the interlayer insulating film, a metal (for example, tungsten) film is deposited, and a chemical and mechanical polishing (CMP) method is performed. The metal contact plug M3 to each element is formed by polishing the surface. Thereafter, an insulating film I6 for forming a wiring layer is deposited, and a wiring pattern is formed by photolithography. Then, a metal (for example, copper) is deposited by sputtering or the like, and the surface is polished by CMP to form a metal wiring M4 in the wiring pattern. Thereafter, the same process is repeated to form a metal wiring on the substrate.

  As described above, in this embodiment, even when gate electrodes having different heights must be formed in the memory array formation region M and the logic circuit formation region L, the sidewall SW of the opening 10b is processed into a forward taper shape. By forming the first spacer SP1 on the side wall SW, the steep step is relieved, and partial thinning of the bark 3 applied for photolithography can be suppressed. Therefore, the incident exposure light LP1 for photoresist exposure is less likely to cause halation, and is particularly effective in suppressing variations in gate dimensions at the outermost periphery of the memory region.

  Further, the forward side taper processing of the opening side wall is performed by an etching process, and the first spacer SP1 can be formed only by depositing an insulating film and etching back. That is, since the effect can be obtained without increasing the photolithography process, it is also effective in suppressing the increase in manufacturing cost.

  Further, in the present embodiment, a semiconductor device manufacturing process including both the step of processing the sidewall SW of the opening 10b into a forward taper shape and the step of forming the first spacer SP1 on the surface of the sidewall SW is shown. However, the effect can be obtained by introducing one of the steps.

  In this embodiment, a silicon oxide film deposited by the CVD method is used as the material for the first spacer SP1, but a polycrystalline silicon film deposited by the CVD method is similarly deposited by the high-density plasma CVD method. The same effect can be obtained by applying a silicon oxide film or a silicon nitride film deposited by a low pressure CVD method. In that case, in the step of forming the first spacer SP1 (FIGS. 3B and 3C), the material is deposited in place of the silicon oxide film I3 and etched back in the same manner as the first spacer SP1. It ’s fine.

  In this embodiment, a method for manufacturing a memory / logic mixed integrated circuit using a MONOS type nonvolatile memory using an electrode having a gate height higher than that of a MISFET used in peripheral logic is used. Although illustrated, the same effect can be obtained in the manufacturing process of an integrated circuit in which MISFETs using gate electrodes having different heights are mounted on the same substrate, including the case where the relationship between the gate heights is reversed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  INDUSTRIAL APPLICABILITY The present invention is effective when applied to a semiconductor device having gate electrodes of different heights, particularly a method for manufacturing a memory / logic mixed integrated circuit, and particularly a semiconductor device in which a MONOS type nonvolatile memory region and a peripheral logic circuit region are mixedly mounted. It is effective for manufacturing.

(A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device which this inventor examined. (A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device following FIG. (A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. (A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device following FIG. (A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device following FIG. (A)-(c) is principal part sectional drawing in the manufacturing process of the semiconductor device following FIG.

Explanation of symbols

1 Semiconductor substrate 2 STI
3 Bark 4 Photoresist L Logic circuit formation area M Memory array formation area LP1 Incident exposure light LP2 Reflection exposure light GI1 First gate insulating film (first insulating film)
GI2 Second gate insulating film (second insulating film)
ONO laminated insulating film GM1 first gate conductive film (first conductive film)
GM2 Second gate conductive film (second conductive film)
G1 1st gate electrode G2 2nd gate electrode G21 Dummy gate MG Memory gate SW Side wall SP1 1st spacer (spacer)
SP2 2nd spacer

Claims (5)

(A) forming a first insulating film and a first conductive film in order on the main surface of the semiconductor substrate;
(B) forming an opening in a part of the first conductive film and the first insulating film;
(C) After the step (b), a step of sequentially forming a second insulating film and a second conductive film in the opening and on the first conductive film;
(D) after the step (c), patterning the second conductive film and the second insulating film to form a first gate electrode in the opening;
(E) after the step (d), forming a second gate electrode by patterning the first conductive film and the first insulating film,
The height of the first gate electrode is different from the height of the second gate electrode,
A method of manufacturing a semiconductor device, wherein the sidewall of the opening formed in the step (b) is processed into a forward tapered shape. (A) forming a first insulating film and a first conductive film in order on the main surface of the semiconductor substrate;
(B) forming an opening in a part of the first conductive film and the first insulating film;
(C) forming a spacer on the side wall of the opening formed in the step (b);
(D) After the step (c), a step of sequentially forming a second insulating film and a second conductive film in the opening and on the first conductive film;
(E) after the step (d), patterning the second conductive film and the second insulating film to form a first gate electrode in the opening;
(F) after the step (e), patterning the first conductive film and the first insulating film to form a second gate electrode,
The height of the first gate electrode is different from the height of the second gate electrode,
A method of manufacturing a semiconductor device, wherein the sidewall of the opening formed in the step (b) is processed into a forward tapered shape. (A) forming a first insulating film and a first conductive film in order on the main surface of the semiconductor substrate;
(B) forming an opening in a part of the first conductive film and the first insulating film;
(C) forming a spacer on the side wall of the opening formed in the step (b);
(D) After the step (c), a step of sequentially forming a second insulating film and a second conductive film in the opening and on the first conductive film;
(E) after the step (d), patterning the second conductive film and the second insulating film to form a first gate electrode in the opening;
(F) after the step (e), patterning the first conductive film and the first insulating film to form a second gate electrode,
A method of manufacturing a semiconductor device, wherein the height of the first gate electrode is different from the height of the second gate electrode. In the manufacturing method of the semiconductor device of Claim 1, Claim 2 or Claim 3,
The first insulating film and the first conductive film, and the second insulating film and the second conductive film are formed so that the height of the first gate electrode is higher than that of the second gate electrode. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. In the manufacturing method of the semiconductor manufacturing apparatus of Claim 2 or Claim 3,
The method of manufacturing a semiconductor device, wherein the spacer is formed using any one of a silicon oxide film, a silicon nitride film, and a polycrystalline silicon film.

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