CN103187277A - Manufacture method of semiconductor device - Google Patents
Manufacture method of semiconductor device Download PDFInfo
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- CN103187277A CN103187277A CN2011104475951A CN201110447595A CN103187277A CN 103187277 A CN103187277 A CN 103187277A CN 2011104475951 A CN2011104475951 A CN 2011104475951A CN 201110447595 A CN201110447595 A CN 201110447595A CN 103187277 A CN103187277 A CN 103187277A
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- shape groove
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Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the steps that: a semiconductor substrate is provided; a gate structure is formed on the semiconductor substrate; side wall structures close to the gate structure are formed on the two sides of the gate structure; a sacrificial oxide layer is formed on the semiconductor substrate to cover the gate structure and the side wall structures; the sacrificial oxide layer is etched, so that oxide side walls are formed on the side wall structures; a bowl-shaped groove is formed in a source/drain region of the semiconductor substrate; the bowl-shaped groove is etched to form a sigma-shaped groove; the oxide side walls are removed; and an embedded germanium-silicon layer is formed in the sigma-shaped groove. According to the method, the maximum width of the sigma-shaped groove in a horizontal direction of the substrate can be increased, while an improvement of electrical properties of the semiconductor device is not affected by LDD (lightly doped drain) injection.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of manufacture method that forms ∑ shape germanium silicon layer.
Background technology
In advanced production process of semiconductor device, embedded germanium silicon technology can obviously strengthen the performance of PMOS.Current, the process sequence that forms embedded germanium silicon has two kinds: a kind of is to form embedded germanium silicon earlier, forms sidewall bodies in the both sides of grid then; Another kind is to form sidewall bodies in the both sides of grid earlier, forms embedded germanium silicon then.In order to obtain bigger process window and better electric property, adopt back a kind of in the above-mentioned process sequence to form embedded germanium silicon usually.
In embedded germanium silicon technology, form ∑ shape groove to be used for the embedded germanium silicon of selective epitaxial growth therein in source/drain region of PMOS usually, described ∑ shape groove can effectively shorten the length of device channel, satisfies the scaled requirement of device size.The first dry etching of the common employing etched technology of wet method again forms described ∑ shape groove, and in above-mentioned etching process procedure, the degree of depth at the tip as shown in fig. 1 101 of the final described ∑ shape groove that forms of control is very difficult.If described most advanced and sophisticated 101 the degree of depth is dark excessively, will weakens forming the LDD that implements before the side wall construction 102 and inject influence for the electric property of semiconductor device.
Therefore, need to propose a kind of method, to address the above problem.
Summary of the invention
At the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate, and be formed with the side wall construction near grid structure in the both sides of described grid structure; Form a sacrificial oxide layer in described Semiconductor substrate, to cover described grid structure and described side wall construction; The described sacrificial oxide layer of etching is to form the monoxide sidewall in described side wall construction; In the source/drain region of described Semiconductor substrate, form bowl-shape groove; The described bowl-shape groove of etching is to form ∑ shape groove; Remove described oxide side walls, and in described ∑ shape groove, form embedded germanium silicon layer.
Further, the process of the bowl-shape groove of described formation comprises: earlier source/the drain region of described Semiconductor substrate is carried out first and be etched with formation one groove, then described groove is carried out second etching.
Further, described first be etched to vertical etching of adopting dry method etch technology.
Further, described second be etched to the isotropic etching that adopts dry method etch technology.
Further, the material of described side wall construction is silicon nitride.
Further, adopt chemical vapor deposition method to form described sacrificial oxide layer.
Further, the material of described sacrificial oxide layer is HARP or LTO.
Further, the thickness of described sacrificial oxide layer is the 30-100 dust.
Further, adopt the described sacrificial oxide layer of anisotropic dry method etch technology etching.
Further, the degree of depth of described bowl-shape groove is the 300-500 dust.
Further, described formation ∑ shape groove is etched to wet etching.
Further, the degree of depth of described ∑ shape groove is greater than 700 dusts.
Further, adopt wet etching process to remove described oxide side walls.
Further, the etchant of described wet etching is the hydrofluoric acid of dilution.
Further, adopt epitaxial growth technology to form described embedded germanium silicon layer.
Further, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer that stacks gradually.
According to the present invention, can increase described ∑ shape groove in the Breadth Maximum of substrate horizontal direction, do not influence LDD and inject improvement for the electric property of semiconductor device.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.
In the accompanying drawing:
Fig. 1 is the schematic cross sectional view of formed ∑ shape groove in the technical process that forms ∑ shape germanium silicon layer;
Fig. 2 A-Fig. 2 F is the schematic cross sectional view of each step of the manufacture method of the formation ∑ shape germanium silicon layer of the present invention's proposition;
Fig. 3 is the flow chart of the manufacture method of the formation ∑ shape germanium silicon layer of the present invention's proposition.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that the manufacture method of the formation ∑ shape germanium silicon layer that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using term " to comprise " in this manual and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, be example with PMOS, the detailed step of the manufacture method of the formation ∑ shape germanium silicon layer that the present invention proposes is described with reference to Fig. 2 A-Fig. 2 F and Fig. 3.
With reference to Fig. 2 A-Fig. 2 F, wherein show the schematic cross sectional view of each step of the manufacture method of the formation ∑ shape germanium silicon layer that the present invention proposes.
At first, shown in Fig. 2 A, provide Semiconductor substrate 200, the constituent material of described Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, is doped with the monocrystalline silicon of impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, described Semiconductor substrate 200 selects for use single crystal silicon material to constitute.In described Semiconductor substrate 200, can also be formed with isolation channel, buried regions (not shown) etc.In addition, for PMOS, can also be formed with N trap (not shown) in the described Semiconductor substrate 200, and before forming grid structure, can carry out once low dose of boron to whole N trap and inject, be used for adjusting the threshold voltage V of PMOS
Th
Be formed with grid structure in described Semiconductor substrate 200, as an example, described grid structure can comprise gate dielectric, gate material layers and the grid hard masking layer that stacks gradually from bottom to top.Gate dielectric can comprise oxide, as, silicon dioxide (SiO
2) layer.Gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and the metal silicide layer, and wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; The conductive metal oxide layer can comprise yttrium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.The grid hard masking layer can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and the amorphous carbon, wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer can comprise silicon nitride (Si
3N
4) layer; Oxynitride layer can comprise silicon oxynitride (SiON) layer.As another example, described grid structure can be semiconductor-stacked grid structure of oxide-nitride thing-oxide-semiconductor (SONOS).
In addition, as example, on described Semiconductor substrate 200, also be formed with and be positioned at the grid structure both sides and near the side wall construction 201 of grid structure.Wherein, described side wall construction 201 can comprise one deck oxide skin(coating) and/or one deck nitride layer at least at least.In the present embodiment, the material of described side wall construction 201 is silicon nitride.
The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure and side wall construction is had the knack of by those skilled in the art, is described no longer in detail at this.In addition, before forming described side wall construction, also comprise LDD inject with in the source/drain region forms lightly doped drain (LDD) structure (not shown) and Halo injects to regulate threshold voltage V
tBreak-through with the source of preventing/drain depletion layer.After forming described side wall construction, also comprise source/leakage injection.
Then, shown in Fig. 2 B, adopt chemical vapor deposition method to form a sacrificial oxide layer 202 in described Semiconductor substrate 200, to cover described grid structure and described side wall construction 201.The material of described sacrificial oxide layer 202 is HARP (oxide that adopts the high-aspect-ratio processing procedure to form) or LTO (formation temperature is lower than 300 ℃ oxide), the thickness of described sacrificial oxide layer 202 is the 30-100 dust, and its concrete numerical value can be determined according to the Breadth Maximum along described Semiconductor substrate 200 horizontal directions of the follow-up ∑ shape groove that forms in source/drain region of PMOS.
Then, shown in Fig. 2 C, adopt the described sacrificial oxide layer 202 of anisotropic dry method etch technology etching, so that described sacrificial oxide layer 202 only covers described side wall construction 201, namely form the monoxide sidewall in described side wall construction 201.Described etch process adopts CF
4As main etching gas, temperature 40-60 ℃, power 100-200W, bias voltage 100-300V, etching period 10-15s.
Then, shown in Fig. 2 D, in the source/drain region of described Semiconductor substrate 200, form bowl-shape groove 203.The processing step that forms described bowl-shape groove 203 comprises: adopt dry method etch technology that described Semiconductor substrate 200 is carried out vertical etching earlier, to form a groove in the source/drain region of described Semiconductor substrate 200, adopt CF
4With HBr as main etching gas, temperature 40-60 ℃, power 200-400W, bias voltage 50-200V, etching period 10-20s; Next, adopt isotropic dry method etch technology to continue the described groove of etching, below described groove, form an oval-shaped groove, namely form described bowl-shape groove 203, adopt Cl
2And NF
3As main etching gas, temperature 40-60 ℃, power 100-500W, bias voltage 0-10V, etching period 5-50s, the degree of depth of described bowl-shape groove 203 is the 300-500 dust.Because above-mentioned etch process has very high selectivity for oxide, namely to the etch-rate of silicon substrate far above the etch-rate to oxide side walls, therefore, described oxide side walls can play a protective role to described side wall construction 201.
Then, shown in Fig. 2 E, adopt the described bowl-shape groove 203 of wet etching process etching, to form ∑ shape groove 204.Utilize the different characteristic (etch-rate in 100 and 110 crystal orientation is higher than the etch-rate in 111 crystal orientation) of the etch-rate of etchant on the different crystal orientations of the material of described Semiconductor substrate 200 of described wet etching, the described bowl-shape groove 203 of expansion etching is to form described ∑ shape groove 204.The temperature of described wet etching is 30-60 ℃, and the desired size of the described ∑ shape of basis of time groove 204 and deciding is generally 100-300s.The degree of depth of described ∑ shape groove 204 is greater than 700 dusts.
Then, shown in Fig. 2 F, adopt wet etching process to remove described oxide side walls, to expose described side wall construction 201.The etchant of described wet etching is the hydrofluoric acid of dilution.Then, adopt epitaxial growth technology in described ∑ shape groove 204, to form embedded germanium silicon layer 205.Described epitaxial growth technology can adopt a kind of in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and the molecular beam epitaxy (MBE).
So far, whole processing steps of method enforcement have according to an exemplary embodiment of the present invention been finished.Next, can finish the making of entire semiconductor device by subsequent technique, described subsequent technique and traditional process for fabricating semiconductor device are identical.According to the present invention; can increase described ∑ shape groove in the Breadth Maximum of substrate horizontal direction; do not influence LDD and inject improvement for the electric property of semiconductor device, the etched damage of adopting in the time of can protecting described grid structure side walls structure to avoid forming described ∑ shape groove simultaneously.
With reference to Fig. 3, wherein show the flow chart of the manufacture method of the formation ∑ shape germanium silicon layer that the present invention proposes, be used for schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided, be formed with grid structure in described Semiconductor substrate, and be formed with the side wall construction near grid structure in the both sides of described grid structure;
In step 302, form a sacrificial oxide layer in described Semiconductor substrate, to cover described grid structure and described side wall construction;
In step 303, the described sacrificial oxide layer of etching is to form the monoxide sidewall in described side wall construction;
In step 304, in the source/drain region of described Semiconductor substrate, form bowl-shape groove;
In step 305, the described bowl-shape groove of etching is to form ∑ shape groove;
In step 306, remove described oxide side walls, and in described ∑ shape groove, form embedded germanium silicon layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate, and be formed with the side wall construction near grid structure in the both sides of described grid structure;
Form a sacrificial oxide layer in described Semiconductor substrate, to cover described grid structure and described side wall construction;
The described sacrificial oxide layer of etching is to form the monoxide sidewall in described side wall construction;
In the source/drain region of described Semiconductor substrate, form bowl-shape groove;
The described bowl-shape groove of etching is to form ∑ shape groove;
Remove described oxide side walls, and in described ∑ shape groove, form embedded germanium silicon layer.
2. method according to claim 1 is characterized in that, the process of the bowl-shape groove of described formation comprises: earlier source/the drain region of described Semiconductor substrate is carried out first and be etched with formation one groove, then described groove is carried out second etching.
3. method according to claim 2 is characterized in that, described first is etched to vertical etching of adopting dry method etch technology.
4. method according to claim 2 is characterized in that, described second is etched to the isotropic etching that adopts dry method etch technology.
5. method according to claim 1 is characterized in that, the material of described side wall construction is silicon nitride.
6. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form described sacrificial oxide layer.
7. according to claim 1 or 6 described methods, it is characterized in that the material of described sacrificial oxide layer is HARP or LTO.
8. according to claim 1 or 6 described methods, it is characterized in that the thickness of described sacrificial oxide layer is the 30-100 dust.
9. method according to claim 1 is characterized in that, adopts the described sacrificial oxide layer of anisotropic dry method etch technology etching.
10. method according to claim 1 is characterized in that, the degree of depth of described bowl-shape groove is the 300-500 dust.
11. method according to claim 1 is characterized in that, described formation ∑ shape groove be etched to wet etching.
12. method according to claim 1 is characterized in that, the degree of depth of described ∑ shape groove is greater than 700 dusts.
13. method according to claim 1 is characterized in that, adopts wet etching process to remove described oxide side walls.
14. method according to claim 13 is characterized in that, the etchant of described wet etching is the hydrofluoric acid of dilution.
15. method according to claim 1 is characterized in that, adopts epitaxial growth technology to form described embedded germanium silicon layer.
16. method according to claim 1 is characterized in that, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer that stacks gradually.
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| CN201110447595.1A CN103187277B (en) | 2011-12-28 | 2011-12-28 | A kind of manufacture method of semiconductor device |
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| CN201110447595.1A CN103187277B (en) | 2011-12-28 | 2011-12-28 | A kind of manufacture method of semiconductor device |
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| CN103187277B CN103187277B (en) | 2016-04-06 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465626A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | ESD protective device and preparation method thereof |
| CN104716042A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN104934322A (en) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | PMOS transistor, manufacturing method therefor, and semiconductor device |
| CN105575900A (en) * | 2014-10-13 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device with semiconductor device |
| CN106910686A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107527869A (en) * | 2016-06-22 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic installation |
| CN111403283A (en) * | 2020-03-03 | 2020-07-10 | 上海华力集成电路制造有限公司 | Embedded germanium-silicon manufacturing method and embedded germanium-silicon structure |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465626A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | ESD protective device and preparation method thereof |
| CN104465626B (en) * | 2013-09-23 | 2017-06-23 | 中芯国际集成电路制造(上海)有限公司 | ESD protection device and preparation method thereof |
| CN104716042A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN104934322A (en) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | PMOS transistor, manufacturing method therefor, and semiconductor device |
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| CN105575900A (en) * | 2014-10-13 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device with semiconductor device |
| CN105575900B (en) * | 2014-10-13 | 2019-12-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN106910686A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107527869A (en) * | 2016-06-22 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic installation |
| CN111403283A (en) * | 2020-03-03 | 2020-07-10 | 上海华力集成电路制造有限公司 | Embedded germanium-silicon manufacturing method and embedded germanium-silicon structure |
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| CN103187277B (en) | 2016-04-06 |
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