CN103794546A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN103794546A CN103794546A CN201210422157.4A CN201210422157A CN103794546A CN 103794546 A CN103794546 A CN 103794546A CN 201210422157 A CN201210422157 A CN 201210422157A CN 103794546 A CN103794546 A CN 103794546A
- Authority
- CN
- China
- Prior art keywords
- layer
- sicb
- semiconductor substrate
- cap layer
- germanium silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000013078 crystal Substances 0.000 claims abstract description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 125000004432 carbon atom Chemical group C* 0.000 claims abstract 2
- 238000005516 engineering process Methods 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000001721 carbon Chemical group 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052914 metal silicate Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate, wherein grid structures are formed on the semiconductor substrate, and a sigma-shaped groove is formed in the semiconductor substrate at the two sides of the grid structures; forming a seed crystal layer at the bottom of the sigma-shaped groove; forming an embedded germanium-silicon layer on the seed crystal layer to fill the sigma-shaped groove fully; forming a SiCB cap layer on the embedded germanium-silicon layer. According to the present invention, the SiCB layer is formed on the embedded germanium-silicon layer as the cap layer, the carbon atoms in the SiCB layer can reduce the diffusion of boron atoms towards the semiconductor substrate, at the same time, the cap layer formed by the SiCB layer can improve the stability of a self-aligning metal silicide which is formed by nickel silicon and formed on the cap layer subsequently, so that the electrical property of the device can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, be formed on the method for the cap layer quality on embedded germanium silicon layer in particular to a kind of improvement.
Background technology
In advanced cmos device manufacturing process, embedded germanium silicon technology is often used the performance of the PMOS part that promotes cmos device.
The process sequences that forms embedded germanium silicon layer in the source/drain region of PMOS is: Semiconductor substrate is provided, on described semiconductor, form the side wall construction of grid structure and grid structure both sides → form groove → employing selective epitaxial growth process and in described groove, form embedded germanium silicon layer → form a cap layer (cap layer) in the Semiconductor substrate of described side wall construction both sides on described embedded germanium silicon layer, described cap layer is for forming self-aligned silicide follow-up before metal interconnected, can also avoid the release of the germanium silicon layer stress that subsequent technique causes simultaneously.If described cap layer is monocrystalline silicon layer, due to the very low decline that causes output in the unit interval of its growth rate, simultaneously due to the poor quality that affects device of its surface smoothness; If described cap layer is borosilicate (SiB) layer, monocrystalline silicon layer relatively, its growth rate is accelerated, surface smoothness is fine, self-resistance value reduces, but boron atom wherein is very easily diffused in substrate (especially channel region), causes the decline of device performance.
Therefore, need to propose a kind of method, to improve the quality that is formed on the cap layer on embedded germanium silicon layer, thereby further promote the performance of cmos device.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure, in the Semiconductor substrate of described grid structure both sides, form ∑ shape groove; Inculating crystal layer is formed on the bottom at described ∑ shape groove; On described inculating crystal layer, form embedded germanium silicon layer, to fill described ∑ shape groove completely; On described embedded germanium silicon layer, form SiCB cap layer.
Further, adopt first dry etching the more etched technique of wet method form described ∑ shape groove.
Further, described inculating crystal layer is the germanium silicon layer with low Ge content.
Further, adopt selective epitaxial growth process to form described embedded germanium silicon layer.
Further, adopt original position epitaxial growth technology to form described SiCB cap layer.
Further, in described SiCB cap layer, the dopant dose of boron atom is 5.0 × e
14-5.0 × e
20atom/cm
2.
Further, in described SiCB cap layer, the dopant dose of carbon atom is 5.0 × e
14-5.0 × e
20atom/cm
2.
Further, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually.
Further, the both sides of described grid structure are formed with the skew clearance wall structure near described grid structure.
Further, described skew clearance wall structure comprises at least one deck oxide skin(coating) and/or at least one deck nitride layer.
According to the present invention, on described embedded germanium silicon layer, form SiCB layer as cap layer, carbon atom wherein can weaken boron atom to the diffusion in described Semiconductor substrate, simultaneously, the cap layer being made up of described SiCB layer can improve the stability of the self-aligned metal silicate being made up of nisiloy forming subsequently, the thus electric property of boost device thereon.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 E is the schematic cross sectional view that improvement that the present invention proposes is formed on each step of the method for the cap layer quality on embedded germanium silicon layer;
Fig. 2 is the flow chart that improvement that the present invention proposes is formed on the method for the cap layer quality on embedded germanium silicon layer.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the improvement that explaination the present invention proposes is formed on the method for the cap layer quality on embedded germanium silicon layer.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Improvement that the present invention proposes described be formed on the detailed step of the method for the cap layer quality on embedded germanium silicon layer below, with reference to Figure 1A-Fig. 1 E and Fig. 2.
With reference to Figure 1A-Fig. 1 E, the improvement that wherein shows the present invention's proposition is formed on the schematic cross sectional view of each step of the method for the cap layer quality on embedded germanium silicon layer.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate 100, to be formed with isolation structure and various trap (well) structure, in order simplifying, in diagram, to be omitted.For PMOS, in described Semiconductor substrate 200, can also be formed with N trap (not shown), and before forming grid structure, can carry out once low dose of boron to whole N trap and inject, for adjusting the threshold voltage V of PMOS
th.
In described Semiconductor substrate 100, be formed with grid structure 101, as an example, described grid structure 101 can comprise the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.Gate dielectric can comprise oxide, as, silicon dioxide (SiO
2) layer.Gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, and wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; Conductive metal oxide layer can comprise yttrium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.Grid hard masking layer can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon, wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer can comprise silicon nitride (Si
3n
4) layer; Oxynitride layer can comprise silicon oxynitride (SiON) layer.
In addition,, as example, in described Semiconductor substrate 100, be also formed with and be positioned at described grid structure 101 both sides and the skew clearance wall structure 102 near described grid structure 101.Wherein, described skew clearance wall structure 102 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
Then, as shown in Figure 1B, the process window consisting of described skew clearance wall structure 102 forms ∑ shape groove 103 in described Semiconductor substrate 100.Conventionally adopt first dry etching the more etched technique of wet method form described ∑ shape groove 103, the concrete steps of this technique are as follows: first adopt the Semiconductor substrate 100 being offset described in the longitudinal etching of dry method etch technology between clearance wall structure 102 to form silicon groove; Adopt again silicon groove described in wet etching process etching, to form described ∑ shape groove 103.
Then, as shown in Figure 1 C, form inculating crystal layer (seed layer) 104 in the bottom of described ∑ shape groove 103.The various suitable technology that adopts those skilled in the art to have the knack of forms described inculating crystal layer 104, for example selective epitaxial growth process.Described inculating crystal layer 104 can be for having the germanium silicon layer of low Ge content.In addition, because needs are that the embedded germanium silicon layer that will form subsequently reserves enough spaces, so described inculating crystal layer 104 can not be too thick, in case fill up whole ∑ shape groove 103.
Then,, as shown in Fig. 1 D, adopt selective epitaxial growth process on described inculating crystal layer 104, to form embedded germanium silicon layer 105, to fill described ∑ shape groove 103 completely.Described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Then,, as shown in Fig. 1 E, on described embedded germanium silicon layer 105, form cap layer 106.Adopt original position epitaxial growth technology to form described cap layer 106, form described cap layer 106 epitaxial growth technology adopting and the epitaxial growth technology that the described embedded germanium silicon layer 105 of formation adopts and carry out in same reaction chamber.The monocrystalline silicon layer (SiCB layer) that described cap layer 106 is doped with boron and carbon, wherein, the dopant dose of described boron atom is 5.0 × e
14-5.0 × e
20atom/cm
2, the dopant dose of described carbon atom is 5.0 × e
14-5.0 × e
20atom/cm
2.
So far, completed whole processing steps that method is implemented according to an exemplary embodiment of the present invention, next, can complete by subsequent technique the making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention, on described embedded germanium silicon layer 105, form SiCB layer as cap layer, carbon atom wherein can weaken boron atom to the diffusion in described Semiconductor substrate 100, simultaneously, the cap layer being made up of SiCB layer can improve the stability of the self-aligned metal silicate being made up of nisiloy (NiSi) forming subsequently, the electric property of boost device thus thereon.
More than implementing whole processing steps that improvement that the present invention proposes is formed on the method for the cap layer quality on embedded germanium silicon layer describes as an example of PMOS transistor example, it will be appreciated by those skilled in the art that, the PMOS transistor here can be the transistorized PMOS part of CMOS.
With reference to Fig. 2, the improvement that wherein shows the present invention's proposition is formed on the flow chart of the method for the cap layer quality on embedded germanium silicon layer, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in described Semiconductor substrate, be formed with grid structure, in the Semiconductor substrate of described grid structure both sides, form ∑ shape groove;
In step 202, form inculating crystal layer in the bottom of described ∑ shape groove;
In step 203, on described inculating crystal layer, form embedded germanium silicon layer, to fill described ∑ shape groove completely;
In step 204, on described embedded germanium silicon layer, form SiCB cap layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure, in the Semiconductor substrate of described grid structure both sides, form ∑ shape groove;
Inculating crystal layer is formed on the bottom at described ∑ shape groove;
On described inculating crystal layer, form embedded germanium silicon layer, to fill described ∑ shape groove completely;
On described embedded germanium silicon layer, form SiCB cap layer.
2. method according to claim 1, is characterized in that, adopt first dry etching the more etched technique of wet method form described ∑ shape groove.
3. method according to claim 1, is characterized in that, described inculating crystal layer is the germanium silicon layer with low Ge content.
4. method according to claim 1, is characterized in that, adopts selective epitaxial growth process to form described embedded germanium silicon layer.
5. method according to claim 1, is characterized in that, adopts original position epitaxial growth technology to form described SiCB cap layer.
6. method according to claim 1 or 5, is characterized in that, in described SiCB cap layer, the dopant dose of boron atom is 5.0 × e
14-5.0 × e
20atom/cm
2.
7. method according to claim 1 or 5, is characterized in that, in described SiCB cap layer, the dopant dose of carbon atom is 5.0 × e
14-5.0 × e
20atom/cm
2.
8. method according to claim 1, is characterized in that, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually.
9. method according to claim 1, is characterized in that, the both sides of described grid structure are formed with the skew clearance wall structure near described grid structure.
10. method according to claim 9, is characterized in that, described skew clearance wall structure comprises at least one deck oxide skin(coating) and/or at least one deck nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422157.4A CN103794546A (en) | 2012-10-29 | 2012-10-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422157.4A CN103794546A (en) | 2012-10-29 | 2012-10-29 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103794546A true CN103794546A (en) | 2014-05-14 |
Family
ID=50670085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210422157.4A Pending CN103794546A (en) | 2012-10-29 | 2012-10-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103794546A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529247A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Preparation method of embedded silicon-germanium |
| CN105590840A (en) * | 2014-10-21 | 2016-05-18 | 上海华力微电子有限公司 | Method for preparing embedded SiGe |
| CN106558550A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008103791A1 (en) * | 2007-02-21 | 2008-08-28 | Texas Instruments Incorporated | Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial sige |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
| US20110212604A1 (en) * | 2007-10-31 | 2011-09-01 | Jusung Engineering Co., Ltd. | Method of fabricating transistor |
| WO2012037136A2 (en) * | 2010-09-13 | 2012-03-22 | Texas Instruments Incorporated | Improved lateral uniformity in silicon recess etch |
-
2012
- 2012-10-29 CN CN201210422157.4A patent/CN103794546A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008103791A1 (en) * | 2007-02-21 | 2008-08-28 | Texas Instruments Incorporated | Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial sige |
| US20110212604A1 (en) * | 2007-10-31 | 2011-09-01 | Jusung Engineering Co., Ltd. | Method of fabricating transistor |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
| WO2012037136A2 (en) * | 2010-09-13 | 2012-03-22 | Texas Instruments Incorporated | Improved lateral uniformity in silicon recess etch |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529247A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Preparation method of embedded silicon-germanium |
| CN105590840A (en) * | 2014-10-21 | 2016-05-18 | 上海华力微电子有限公司 | Method for preparing embedded SiGe |
| CN106558550A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103594370B (en) | A kind of manufacture method of semiconductor device | |
| CN103187277B (en) | A kind of manufacture method of semiconductor device | |
| CN102832128B (en) | Manufacturing method of semiconductor device | |
| CN104425375A (en) | Method for manufacturing semiconductor device | |
| CN103794546A (en) | Method for manufacturing semiconductor device | |
| CN103151264B (en) | A kind of manufacture method of semiconductor devices | |
| CN104217952A (en) | Manufacture method of semiconductor device | |
| CN102856199A (en) | Manufacturing method of semiconductor device | |
| CN102915971B (en) | Manufacturing method of semiconductor device | |
| CN103151258B (en) | A kind of manufacture method of semiconductor device | |
| CN103137451B (en) | A kind of manufacture method of semiconductor device | |
| CN105470296A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN103681333A (en) | Method for manufacturing semiconductor device | |
| CN104979291A (en) | Manufacturing method of semiconductor device | |
| CN103151311B (en) | A kind of manufacture method of semiconductor devices | |
| CN106981424A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN103903984A (en) | Method for manufacturing semiconductor device | |
| CN104934323B (en) | A kind of manufacture method of semiconductor devices | |
| CN103578994B (en) | A kind of manufacture method of semiconductor device | |
| CN104681441A (en) | Method for preventing embedded germanium silicon top cap layer from etching pollution | |
| CN103594363A (en) | A method for manufacturing a semiconductor device | |
| CN104952725B (en) | A kind of semiconductor devices and its manufacture method | |
| CN105448715A (en) | Semiconductor device manufacturing method | |
| CN104022040B (en) | The manufacture method of semiconductor devices | |
| CN103681257B (en) | A kind of manufacture method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140514 |