CN107464809A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN107464809A CN107464809A CN201610392502.2A CN201610392502A CN107464809A CN 107464809 A CN107464809 A CN 107464809A CN 201610392502 A CN201610392502 A CN 201610392502A CN 107464809 A CN107464809 A CN 107464809A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The present invention, which provides a kind of semiconductor devices and its manufacture method, electronic installation, methods described, to be included：Semiconductor substrate formed with isolation structure is provided, gate dielectric, gate material layers and dielectric layer are sequentially formed thereon；Gate dielectric, gate material layers and the dielectric layer stacked gradually is patterned, to form the capacitor stacking structure on isolation structure and the MOS transistor gate stack structure in the Semiconductor substrate between isolation structure；Side wall construction is formed in capacitor stacking structure and MOS transistor gate stack structure both sides；Connect material layer, blanket dielectric layer, side wall construction, isolation structure and Semiconductor substrate in deposition；Connect material layer in patterning, to form the first connecting layer, extended to the source electrode of MOS transistor on the capacitor stacking structure on neighbouring isolation structure by the first connecting layer.According to the present invention it is possible to effectively reduce the area in the chip active area that pseudo sram memory cell is occupied.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacture method, electronics
Device.
Background technology
Pseudo sram (Pseudo SRAM) has big memory size, low cost, high-frequency speed, low
The advantages of power consumption, its memory cell are made up of 1T (transistor)+1C (electric capacity).
When making the 1C for forming Pseudo SRAM memory cells using existing process, the area in chip active area is taken very
Greatly, the isolation structure and in chip only serves the effect that isolation forms the 1T and 1C of PseudoSRAM memory cell, is not subject to
It is further to utilize.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, formed with isolation structure in the Semiconductor substrate；Gate dielectric, grid are sequentially formed on the semiconductor substrate
Pole material layer and dielectric layer；The gate dielectric, gate material layers and the dielectric layer stacked gradually is patterned, is located at being formed
Capacitor stacking structure on the isolation structure and the MOS transistor in the Semiconductor substrate between the isolation structure
Gate stack structure；Side wall construction is formed in the capacitor stacking structure and MOS transistor gate stack structure both sides；Deposition
Interior even material layer, covers the dielectric layer, side wall construction, isolation structure and Semiconductor substrate；The interior even material layer is patterned,
To form the first connecting layer, the neighbouring isolation is extended to the source electrode of the MOS transistor by first connecting layer
On capacitor stacking structure in structure.
In one example, the gate material layers in the capacitor stacking structure, dielectric layer and first connecting layer
Form capacitor arrangement.
In one example, the material of the interior even material layer includes polysilicon, and the material of the gate material layers includes
Polysilicon.
In one example, in the step of patterning the interior even material layer, while the second connecting layer is formed, passes through institute
The second connecting layer is stated to extend to the drain electrode of the MOS transistor on the neighbouring isolation structure.
In one example, after the interior even material layer is patterned, in the MOS transistor laminated construction
Dielectric layer is removed, and the dielectric layer in the capacitor stacking structure is partially removed.
In one example, the semiconductor devices is pseudo sram.
In one example, after patterning the interior even material layer, also comprise the following steps：In the Semiconductor substrate
Upper formation interlayer dielectric layer, forms multiple contact plugs in the interlayer dielectric layer, and the bottom of the contact plug electrically connects respectively
Connect the drain electrode of the gate material layers and the MOS transistor in the capacitor stacking structure.
In one example, bottom is electrically connected with the top of the contact plug of the gate material layers in the capacitor stacking structure
End is electrically connected with earth terminal, and the top that bottom is electrically connected with the contact plug of the drain electrode of the MOS transistor is electrically connected with bit line, institute
The gate material layers of MOS transistor are stated as wordline.
In one embodiment, the present invention also provides a kind of semiconductor devices manufactured using the above method, by the electricity
The capacitor arrangement that gate material layers, dielectric layer and the first connecting layer in container laminate structure are formed is deposited as pseudo- static random
A part for access to memory memory cell, the MOS transistor is as the pseudo sram memory cell
Another part.
In one embodiment, the present invention also provides a kind of electronic installation, and the electronic installation includes the semiconductor device
Part.
According to the present invention it is possible to the chip active area that effectively reduction pseudo sram memory cell is occupied
Area.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A is the schematic cross sectional view of the Pseudo SRAM memory cells made according to prior art；
Figure 1B is the schematic cross sectional view of Pseudo SRAM memory cells proposed by the present invention；
Fig. 2A-Fig. 2 B are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of part；
Fig. 3 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one；
Fig. 4 is the schematic diagram according to the electronic installation of exemplary embodiment of the present three.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As shown in Figure 1A, it is the schematic cross sectional view according to the Pseudo SRAM memory cells of prior art making.
On a semiconductor substrate 100 formed with grid structure, the constituent material of Semiconductor substrate 100 can use undoped with
Monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, is laminated on insulator
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
As an example, grid structure includes gate dielectric 102a, gate material layers 102b and the grid being laminated from bottom to top
Extremely hard masking layer 102c.
Gate dielectric 102a includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers 102b includes more
Crystal silicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and one kind or more in metal silicide layer
Kind, wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes nitridation
Titanium (TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi)
Layer.Grid hard masking layer 102c includes the one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon,
Wherein, the constituent material of oxide skin(coating) includes boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), not
Doped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride layer bag
Include silicon nitride (Si3N4) layer；Oxynitride layer includes silicon oxynitride (SiON) layer.
Gate dielectric 102a, gate material layers 102b and grid hard masking layer 102c forming method can use this
Any prior art that art personnel are familiar with, preferably chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), PECVD
Deposit (PECVD).
On a semiconductor substrate 100 formed with positioned at grid structure both sides and against the side wall construction 103 of grid structure.Its
In, side wall construction 103 is made up of oxide, nitride or combination.Before side wall construction 103 is formed, implement LDD
Injection is injected with adjusting threshold voltage V with forming lightly doped drain (LDD) structure and HalotWith the break-through for preventing source/drain depletion layer.
After side wall construction 103 is formed, implement source drain implant to form source drain implant.It is to put it more simply, light not shown in diagram
Adulterate drain structure and source drain implant.
Formed with isolation structure 101 in Semiconductor substrate 100, as an example, isolation structure 101 is shallow trench isolation junction
Structure.The both sides of isolation structure 101 are respectively formed with MOS capacitor and MOS transistor.
On a semiconductor substrate 100 formed with interlayer dielectric layer 104, formed with multiple contacts in interlayer dielectric layer 104
Plug 105, wherein, the gate material layers 102b and drain electrode, MOS crystal of MOS capacitor is electrically connected in the bottom of contact plug 105
The source electrode of pipe and drain electrode, the top that bottom is electrically connected with the material layer 102b of MOS capacitor contact plug 105 are electrically connected with metal
The top electricity of the contact plug 105 of the drain electrode of MOS capacitor and the source electrode of MOS transistor is electrically connected in interconnection layer 110, bottom
Property the same metal interconnecting layer 111 of connection, the top that bottom is electrically connected with the contact plug 105 of the drain electrode of MOS transistor is electrically connected with
As the metal interconnecting layer 112 of bit line, the gate material layers of MOS transistor are as wordline.
1T of the MOS transistor as Pseudo SRAM memory cells, MOS capacitor is as Pseudo SRAM memory cells
1C.The area that MOS capacitor takes chip active area is very big, and isolation structure 101 only serves isolation and forms Pseudo SRAM
The 1T and 1C of memory cell effect, are not utilized further.
As shown in Figure 1B, its be Pseudo SRAM memory cells proposed by the present invention schematic cross sectional view.
On a semiconductor substrate 100 formed with isolation structure 101, as an example, isolation structure 101 is shallow trench isolation junction
Structure.The constituent material of Semiconductor substrate 100 can use undoped with monocrystalline silicon, doped with the monocrystalline silicon of impurity, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).
Formed with MOS capacitor laminated construction on isolation structure 101, the Semiconductor substrate between isolation structure 101
Formed with MOS transistor on 100.The gate stack structure of MOS transistor by the gate dielectric 102a that is laminated from bottom to top and
Gate material layers 102b is formed.
In the both sides of MOS capacitor laminated construction and MOS transistor gate stack structure formed with side wall construction 103, its
In, side wall construction 103 is made up of oxide, nitride or combination.Before side wall construction 103 is formed, implement LDD
Injection is injected with adjusting threshold voltage V with forming lightly doped drain structure and HalotWith the break-through for preventing source/drain depletion layer, in shape
Into after side wall construction 103, implement source drain implant to form source drain implant, to put it more simply, being lightly doped not shown in diagram
Drain structure and source drain implant.
The operative tip of gate material layers 102b in MOS capacitor laminated construction is formed with dielectric layer 107, in medium
Layer 107 on formed with connecting layer 106, connecting layer 106 also cover MOS transistor source electrode and drain electrode, positioned at MOS capacitor lamination
Side wall construction 103 and isolation structure 101 between structure and MOS transistor gate stack structure and neighbouring MOS transistor
The isolation structure 101 of drain electrode.Gate material layers 102b, dielectric layer 107 and the connecting layer 106 being laminated from bottom to top form MOS electricity
Container laminate structure, the 1C as Pseudo SRAM memory cells.
On a semiconductor substrate 100 formed with interlayer dielectric layer 104, formed with multiple contacts in interlayer dielectric layer 104
Plug 105, wherein, the bottom of contact plug 105 be electrically connected gate material layers 102b in MOS capacitor laminated construction and
The drain electrode of MOS transistor, bottom are electrically connected with the contact plug 105 of the gate material layers 102b in MOS capacitor laminated construction
Top is electrically connected with earth terminal, and the top that bottom is electrically connected with the contact plug 105 of the drain electrode of MOS transistor is electrically connected with bit line,
Gate material layers 102b in MOS transistor gate stack structure is as wordline.
The 1C for forming Pseudo SRAM memory cells is formed on isolation structure 101, will be made up of connecting layer 106
The 1T of Pseudo SRAM memory cells source electrode is extended on the 1C on neighbouring isolation structure 101, meanwhile, pass through connecting layer
106 extend to the drain electrode for the 1T for forming Pseudo SRAM memory cells on neighbouring isolation structure 101, can effectively reduce
The area in the chip active area that Pseudo SRAM memory cells are occupied.
As shown in figure 3, the invention provides a kind of manufacture method of semiconductor devices, it is proposed by the present invention to be formed
Pseudo SRAM memory cells, this method include：
In step 301, there is provided Semiconductor substrate, in the semiconductor substrate formed with isolation structure；
In step 302, gate dielectric, gate material layers and dielectric layer are sequentially formed on a semiconductor substrate；
In step 303, the gate dielectric stacked gradually, gate material layers and dielectric layer are patterned, is located at being formed
MOS transistor gate stack on capacitor stacking structure on isolation structure and the Semiconductor substrate between isolation structure
Structure；
In step 304, formed in capacitor stacking structure and MOS transistor gate stack structure both sides against grid
Side wall construction；
In step 305, material layer, blanket dielectric layer, side wall construction, isolation structure and Semiconductor substrate are connected in deposition；
Within step 306, material layer is connected in patterning, to form the first connecting layer, by the first connecting layer by MOS crystal
The source electrode of pipe is extended on the capacitor stacking structure on neighbouring isolation structure.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
[exemplary embodiment one]
Reference picture 2A- Fig. 2 B, the step of according to an exemplary embodiment of the present one method of illustrated therein is is implemented successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200, which can use, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), silicon (SSOI), insulator upper strata are laminated on insulator
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, at this
In embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
Formed with isolation structure 201 in Semiconductor substrate 200, as an example, isolation structure 201 is isolated for shallow trench
(STI) structure.Various traps (well) structure is also formed with Semiconductor substrate 200, to put it more simply, being omitted in diagram.
By taking fleet plough groove isolation structure as an example, hard mask layer is first formed on the substrate, using those skilled in the art institute
The various suitable technologies being familiar with form the hard mask layer, such as chemical vapor deposition method, the hard mask layer
The preferred silicon nitride of material.
The hard mask layer is patterned again, and opening for fleet plough groove isolation structure pattern is formed to be formed in the hard mask layer
Mouthful, the process includes：The photoresist layer with fleet plough groove isolation structure pattern is formed on the hard mask layer, with the photoetching
Glue-line is mask, etches the hard mask layer until exposing the substrate, and the photoresist layer is removed using cineration technics.
Then, using the hard mask layer of the patterning as mask, etched in the substrate for formed shallow trench every
From the groove of structure.Then, depositing isolation material, the isolated material are usually oxygen in the trench and on hard mask layer
Compound, preferably HARP.Next, performing chemical mechanical milling tech to grind the isolated material, described covered firmly until exposing
Film layer.
In above process, in order to ensure realizing that the zero-clearance of isolated material is filled in the trench, the isolated material
Deposition (be usually three times) completes several times, the composition of the isolated material formed each time is identical.In the deposition
Afterwards, annealing is performed, so that the isolated material densification formed, lifts its mechanical strength.After the grinding, perform another
Annealing, to repair damage of the said process to the substrate, the interface improved between fleet plough groove isolation structure and the substrate is special
Property.
It should be noted that in the examples described above, being formed before the hard mask layer, one layer of oxide thin layer can be initially formed
Thing is as cushion, to discharge the stress between the hard mask layer and the substrate；Before depositing the isolated material, in institute
State on hard mask layer and another oxide thin layer thing structure is formed on the side wall of the groove for forming fleet plough groove isolation structure and bottom
Into backing layer.
Gate dielectric 202a, gate material layers 202b and dielectric layer 207 are sequentially formed on semiconductor substrate 200.
Gate dielectric 202a constituent material includes oxide, such as silica (SiO2).Gate material layers 202b
Constituent material include polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide in one
Kind is a variety of, wherein, metal can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride includes titanium nitride (TiN)；
Conductive metal oxide includes yttrium oxide (IrO2)；Metal silicide includes titanium silicide (TiSi).The composition material of dielectric layer 207
Material includes the one or more in oxide, nitride, nitrogen oxides and amorphous carbon, wherein, oxide includes boron phosphorus silicon glass
It is glass (BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), highly dense
Spend plasma (HDP) or spin-on dielectric (SOD)；Nitride includes silicon nitride (SiN)；Nitrogen oxides includes silicon oxynitride
(SiON).According to the electrical parameter of the PIP capacitor of required formation, the constituent material and thickness of adjustment dielectric layer 207.
Gate dielectric 202a is formed using heat chemistry oxidation technology, is familiar with using those skilled in the art any existing
There is technology to form gate material layers 202b and dielectric layer 207, preferably chemical vapour deposition technique (CVD), as low temperature chemical vapor sinks
Product (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical gas
Mutually deposition (PECVD).
Next, the gate dielectric 202a, the gate material layers 202b that are stacked gradually by photoetching, etch process patterning
With dielectric layer 207, the first laminated construction being made up of gate dielectric 202a and dielectric layer 207 is formed on isolation structure 201,
Gate dielectric 202a, the grid material by being laminated from bottom to top are formed in Semiconductor substrate 200 between isolation structure 201
The second laminated construction that layer 202b and dielectric layer 207 are formed.
Next, form side wall construction 203 in above-mentioned laminated construction both sides.As an example, side wall construction 203 is included at least
Oxide skin(coating) and/or nitride layer.The technique for forming side wall construction 203 is familiar with by those skilled in the art, no longer superfluous herein
State.
Formed before side wall construction 203, implement LDD injections with the Semiconductor substrate 200 of the second laminated construction both sides
Lightly doped drain (LDD) structure is formed, and implements Halo injections with adjusting threshold voltage VtWith the break-through for preventing source/drain depletion layer.
Formed side wall construction 203 after, implement source drain implant with the Semiconductor substrate 200 of the second laminated construction both sides formed source/
Drain implant.To put it more simply, lightly doped drain structure and source drain implant not shown in diagram.
Then, as shown in Figure 2 B, material layer, blanket dielectric layer 207, side wall knot are connected in deposition on semiconductor substrate 200
Structure 203, isolation structure 201 and Semiconductor substrate 200.As an example, the interior thickness for connecting material layer is 200 angstroms -400 angstroms, interior company
The material of material layer can be polysilicon etc..
Next, by connecting material layer in photoetching, etch process patterning, the connecting layer 206 of formation covers the second lamination
The source electrode of structure and drain electrode, the side wall construction 203 between the first laminated construction and the second laminated construction and isolation structure
201 and neighbouring second laminated construction drain electrode isolation structure 201.Meanwhile remove the medium on the second laminated construction
Layer 207 and the certain media layer 207 on the first laminated construction.Now, the gate material layers in the first laminated construction
202b, dielectric layer 207 and connecting layer 206 form MOS capacitor laminated construction, the 1C as Pseudo SRAM memory cells.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that
The present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include afterwards
Other desired step, it is included in the range of this implementation preparation method.
Compared with the prior art, according to the proposed method, the 1C for forming Pseudo SRAM memory cells is formed
On isolation structure 201, the source electrode of the MOS transistor for the 1T for forming Pseudo SRAM memory cells is prolonged by connecting layer 206
Extend on the 1C on neighbouring isolation structure 201, meanwhile, by connecting layer 206 will form Pseudo SRAM memory cells 1T
The drain electrode of MOS transistor extend on neighbouring isolation structure 201, can effectively reduce Pseudo SRAM memory cells institute
The area in the chip active area occupied.
[exemplary embodiment two]
First, there is provided the semiconductor device that the processing step that one method is implemented according to an exemplary embodiment of the present obtains
Part, as shown in Figure 2 B, including：Semiconductor substrate 200, formed with isolation structure 201 and various traps in Semiconductor substrate 200
Structure, as an example, isolation structure 201 is fleet plough groove isolation structure.
The constituent material of Semiconductor substrate 200 can use undoped with monocrystalline silicon, doped with impurity monocrystalline silicon, insulation
Silicon (SOI) on body, silicon (SSOI) is laminated on insulator, is laminated SiGe (S-SiGeOI), germanium on insulator SiClx on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).
Formed with MOS capacitor laminated construction on isolation structure 201, the Semiconductor substrate between isolation structure 201
Formed with MOS transistor gate stack structure on 200.MOS transistor gate stack structure is situated between by the grid being laminated from bottom to top
Electric layer 202a and gate material layers 202b is formed.
In the both sides of MOS capacitor laminated construction and MOS transistor gate stack structure formed with side wall construction 203, its
In, side wall construction 203 is made up of oxide, nitride or combination.Before side wall construction 203 is formed, implement LDD
Injection is injected with adjusting threshold voltage V with forming lightly doped drain structure and HalotWith the break-through for preventing source/drain depletion layer, in shape
Into after side wall construction 203, implement source drain implant to form source drain implant, to put it more simply, being lightly doped not shown in diagram
Drain structure and source drain implant.
The part top of gate material layers 202b in MOS capacitor laminated construction is formed with dielectric layer 207, in medium
Layer 207 on formed with connecting layer 206, connecting layer 206 also cover MOS transistor source electrode and drain electrode, positioned at MOS capacitor lamination
Side wall construction 203 and isolation structure 201 between structure and MOS transistor gate stack structure and neighbouring MOS transistor
The isolation structure 201 of drain electrode.Gate material layers 202b, dielectric layer 207 and the connecting layer 206 being laminated from bottom to top form MOS electricity
Container laminate structure, the 1C as Pseudo SRAM memory cells.
The 1C for forming Pseudo SRAM memory cells is formed on isolation structure 201, will be made up of connecting layer 206
The source electrode of the 1T of Pseudo SRAM memory cells MOS transistor is extended on the 1C on neighbouring isolation structure 201, meanwhile,
The drain electrode of the MOS transistor for the 1T for forming Pseudo SRAM memory cells is extended to by neighbouring isolation junction by connecting layer 206
On structure 201, it can effectively reduce the area in the chip active area that Pseudo SRAM memory cells are occupied.
Then, the making of whole semiconductor devices is completed by subsequent technique, including：Formed on semiconductor substrate 200
Interlayer dielectric layer, multiple contact plugs are formed in interlayer dielectric layer, wherein, mos capacitance is electrically connected in the bottom of contact plug
The drain electrode of gate material layers 202b and MOS transistor in device laminated construction, bottom are electrically connected with MOS capacitor laminated construction
The gate material layers 202b top of contact plug be electrically connected with earth terminal, the drain electrode that bottom is electrically connected with MOS transistor connects
The top for touching plug is electrically connected with bit line, and the gate material layers 202b in MOS transistor gate stack structure is as wordline.
Another interlayer dielectric layer is formed on semiconductor substrate 200, and multiple interconnection gold are formed in another interlayer dielectric layer
Belong to layer, generally use dual damascene process is completed；Form metal pad, lead key when being encapsulated for subsequent implementation device
Close.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it includes according to an exemplary embodiment of the present two semiconductor devices.
The electronic installation can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD, DVD, navigation
Any electronic product such as instrument, camera, video camera, recording pen, MP3, MP4, PSP or equipment or any including described
The intermediate products of semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with the display portion being included in shell 401
402nd, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
The inner member of the electronic installation includes the semiconductor devices described in exemplary embodiment two.The electronics dress
Put, due to having used the semiconductor devices, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, formed with isolation structure in the Semiconductor substrate；Gate dielectric, gate material layers and dielectric layer are sequentially formed on the semiconductor substrate；The gate dielectric, gate material layers and the dielectric layer stacked gradually is patterned, is located at the isolation structure to be formed On capacitor stacking structure and the MOS transistor gate stack knot in Semiconductor substrate between the isolation structure Structure；Side wall construction is formed in the capacitor stacking structure and MOS transistor gate stack structure both sides；Connect material layer in deposition, cover the dielectric layer, side wall construction, isolation structure and Semiconductor substrate；The interior even material layer is patterned, to form the first connecting layer, by first connecting layer by the MOS transistor Source electrode is extended on the capacitor stacking structure on the neighbouring isolation structure.
- 2. according to the method for claim 1, it is characterised in that gate material layers, Jie in the capacitor stacking structure Matter layer forms capacitor arrangement with first connecting layer.
- 3. according to the method for claim 1, it is characterised in that the material of the interior even material layer includes polysilicon, described The material of gate material layers includes polysilicon.
- 4. according to the method for claim 1, it is characterised in that in the step of patterning the interior even material layer, simultaneously The second connecting layer is formed, the drain electrode of the MOS transistor is extended to by the neighbouring isolation junction by second connecting layer On structure.
- 5. according to the method for claim 1, it is characterised in that after the interior even material layer is patterned, positioned at described Dielectric layer in MOS transistor laminated construction is removed, and the dielectric layer in the capacitor stacking structure is partially removed.
- 6. according to the method for claim 1, it is characterised in that the semiconductor devices is pseudo- static random access memory Device.
- 7. according to the method for claim 1, it is characterised in that after the patterning interior even material layer, in addition to it is as follows Step：Interlayer dielectric layer is formed on the semiconductor substrate, and multiple contact plugs are formed in the interlayer dielectric layer, it is described to connect The drain electrode of gate material layers and the MOS transistor in the capacitor stacking structure is electrically connected in the bottom for touching plug.
- 8. according to the method for claim 7, it is characterised in that bottom is electrically connected with the grid in the capacitor stacking structure The top of the contact plug of pole material layer is electrically connected with earth terminal, and bottom is electrically connected with the contact plug of the drain electrode of the MOS transistor Top be electrically connected with bit line, the gate material layers of the MOS transistor are as wordline.
- A kind of 9. semiconductor devices that method using described in one of claim 1-8 manufactures, by the capacitor stacking structure In gate material layers, the capacitor arrangement that forms of dielectric layer and the first connecting layer is as pseudo sram storage A part for unit, the another part of the MOS transistor as the pseudo sram memory cell.
- 10. a kind of electronic installation, it is characterised in that the electronic installation includes the semiconductor devices described in claim 9.
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| CN102956437A (en) * | 2011-08-17 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Capacitor and method for manufacturing capacitor on semiconductor device with metal grid electrode |
| CN103633026A (en) * | 2012-08-23 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
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| CN102956437A (en) * | 2011-08-17 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Capacitor and method for manufacturing capacitor on semiconductor device with metal grid electrode |
| CN103633026A (en) * | 2012-08-23 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
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Application publication date: 20171212 |