CN106252244A - A kind of terminal passivating method and semiconductor power device - Google Patents
A kind of terminal passivating method and semiconductor power device Download PDFInfo
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- CN106252244A CN106252244A CN201610843019.1A CN201610843019A CN106252244A CN 106252244 A CN106252244 A CN 106252244A CN 201610843019 A CN201610843019 A CN 201610843019A CN 106252244 A CN106252244 A CN 106252244A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000010409 thin film Substances 0.000 claims abstract description 40
- 238000002161 passivation Methods 0.000 claims abstract description 39
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 27
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 27
- 238000006396 nitration reaction Methods 0.000 claims abstract description 24
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- -1 nitration case Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 238000005224 laser annealing Methods 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 238000000427 thin-film deposition Methods 0.000 claims description 3
- 229910001415 sodium ion Inorganic materials 0.000 abstract description 4
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 98
- 238000010586 diagram Methods 0.000 description 14
- 230000005684 electric field Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000002500 effect on skin Effects 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a kind of terminal passivating method and semiconductor power device, described method is included on semiconductor power device and sequentially deposits semi-insulating polysilicon thin film, nitration case, silicon dioxide layer and passivation layer, forms layer compound passivation layer；Semiconductor power device uses said method manufacture.Compared with prior art, a kind of terminal passivating method of present invention offer and semiconductor power device, semi-insulating polysilicon thin film deposits nitration case, steam and sodium ion can be stopped, thus improve the reliability of semiconductor power device.
Description
Technical field
The present invention relates to semiconductor power device preparing technical field, be specifically related to a kind of terminal passivating method and quasiconductor
Power device.
Background technology
Semiconductor power device is widely used in industrial processes, household electrical appliance, transportation, intelligent grid, national defense and military
The fields such as equipment and Aero-Space, it is therefore desirable to possess higher reliability.It is presently mainly the knot at semiconductor power device
In structure design and processes flow process, in the structure design and processes flow process of its terminal passivating, especially improve semiconductor power device
Reliability.
The terminal of semiconductor power device generally uses the plane terminal that planar technology manufactures, such as bipolar devices or field
Effect device.It can be passivated in the way of using cover film by plane terminal, and blocking harmful foreign ion is to substrate table
Face is spread, thus improves the reliability of semiconductor power device.Wherein, passivation film mainly includes boron-phosphorosilicate glass (Boro
Phospho Silicate Glass, BPSG), silicon nitride, semi-insulating polysilicon (Semi-Insulating
Polycrystalline Silicon, SIPOS), silicon oxynitride, polyimides (Polyimide, PI) and glass etc..Semi-insulating
Polysilicon is widely used owing to possessing following advantage:
1, half insulation.Its resistivity is 1E7～1E10 Ω .cm.
When the electric charge that substrate surface sensing produces flows into semi-insulating polysilicon thin film, it is possible to form space charge layer；This sky
Between charge layer can more effectively shield external electric field compared with insulating barrier, excessive leakage current will not be produced compared with metal level.
2, do not produce fixed charge, i.e. keep electric neutrality.
When the electric charge that substrate surface sensing produces flows into semi-insulating polysilicon thin film, it is possible to form space charge layer；This sky
Between charge layer can more effectively shield external electric field compared with insulating barrier, excessive leakage current will not be produced compared with metal level.
3, existing defects energy level, can effectively shield external electric field, greatly reduce skin effect.
Negative space-charge region can be set up to shield external electric field when semi-insulating polysilicon is by positive electric field effect.With
Sample, then can set up positive space-charge region when by negative electric field effect to shield external electric field, make semiconductor power device table
Face shows the characteristic of quite stable, greatly reduces skin effect, reduces tracking current.
But, semi-insulating polysilicon has certain moisture absorption, the most weak to the blocking capability of Na ion and steam, when partly leading
Body power device is likely to result in the reliability of semiconductor power device and is substantially reduced when working in adverse circumstances, affect its normal work
Make.
Summary of the invention
In order to overcome the defect of prior art, the invention provides a kind of terminal passivating method and semiconductor power device.
First aspect, in the present invention, the technical scheme of a kind of terminal passivating method is:
Described method includes:
Semiconductor power device sequentially deposits semi-insulating polysilicon thin film, nitration case, silicon dioxide layer and passivation layer,
Form layer compound passivation layer.
Further, the present invention provides the optimal technical scheme to be: described deposit on semiconductor power device semi-insulating many
Include before polycrystal silicon film:
Surface of silicon at described semiconductor power device grows oxide layer, and described oxide layer is carried out photoetching and etching
It is formed with source region window, is doped formation PN junction to silicon substrate；
In described oxide layer and deposit semi-insulating polysilicon thin film in the plane and thin to described semi-insulating polysilicon
Film carries out photoetching and etching forms fairlead.
Further, the present invention provides the optimal technical scheme to be: described deposit nitration case on semi-insulating polysilicon thin film
Including:
In the environment of full nitrogen, described semi-insulating polysilicon thin film is carried out laser annealing, form nitridation on its surface
Layer.
Further, the present invention provides the optimal technical scheme to be: described on silicon dioxide layer, deposit passivation layer before wrap
Include:
Deposited metal on described silicon dioxide layer, described metal level is inserted downwards described fairlead and serves as a contrast with described silicon
The active region contact at the end；Described metal level is carried out photoetching and etching forms metal electrode.
Further, the present invention provides the optimal technical scheme to be: deposits passivation layer on described silicon dioxide layer and includes:
At the metal electrode of described semiconductor power device and deposit passivation layer in the plane, and to described passivation layer
Carry out photoetching and etching forms welding window.
Further, the present invention provides the optimal technical scheme to be:
The thickness of described oxide layer is 8000～20000 angstroms；
Described passivation layer is polyimide film layer.
Second aspect, in the present invention, the technical scheme of a kind of semiconductor power device is:
Described semiconductor power device includes:
Silicon substrate；
Oxide layer, described oxide layer is deposited on described silicon substrate；
Semi-insulating polysilicon thin film, described semi-insulating polysilicon thin-film deposition is in described oxide layer, described semi-insulating many
Polycrystal silicon film includes fairlead；
Nitration case, described nitration case is grown in its surface by described semi-insulating polysilicon thin film is carried out laser annealing；
Silicon dioxide layer, described silicon dioxide layer is deposited on described nitration case；
Metal level, described metal level is deposited on described silicon dioxide layer, and inserts downwards described fairlead and with described
The active region contact of silicon substrate；
Passivation layer, described passivation layer is deposited on described metal level, and forms welding window on described metal level.
Compared with immediate prior art, the invention has the beneficial effects as follows:
1, a kind of terminal passivating method that the present invention provides, can improve quasiconductor merit by manufacturing layer compound passivation layer
The sealing of rate device, blocking harmful foreign ion spreads to substrate surface, deposits nitrogen on semi-insulating polysilicon thin film simultaneously
Change layer, steam and sodium ion can be stopped, thus improve the reliability of semiconductor power device；
2, a kind of semiconductor power device that the present invention provides, including insulated polysilicon thin film, nitration case, silicon dioxide layer
Multi-layer compound structure is constituted, it is possible to significantly improve the sealing of semiconductor power device so that it is be applied to severe ring with passivation layer
Higher reliability can also be kept time under border.
Accompanying drawing explanation
Fig. 1: oxide layer schematic diagram in the embodiment of the present invention；
Fig. 2: active area window schematic diagram in the embodiment of the present invention；
Fig. 3: PN junction schematic diagram in the embodiment of the present invention；
Fig. 4: semi-insulating polysilicon thin film schematic diagram in the embodiment of the present invention；
Fig. 5: silicon dioxide layer schematic diagram in the embodiment of the present invention；
Fig. 6: metal electrode schematic diagram in the embodiment of the present invention；
Fig. 7: passivation layer schematic diagram in the embodiment of the present invention；
Wherein, 1: silicon substrate N+ layer；2: silicon substrate N-layer；3: oxide layer；4:PN ties；5: semi-insulating polysilicon thin film；6:
Silicon dioxide layer；7: metal electrode；8: passivation layer.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely illustrated, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
Below in conjunction with the accompanying drawings, a kind of terminal passivating method provided the embodiment of the present invention illustrates.
By sequentially depositing semi-insulating polysilicon thin film, nitration case, dioxy on semiconductor power device in the present embodiment
SiClx layer and passivation layer, form layer compound passivation layer.Layer compound passivation layer can improve the sealing of semiconductor power device
Property, blocking harmful foreign ion spreads to substrate surface, deposits nitration case on semi-insulating polysilicon thin film simultaneously, can stop
Steam and sodium ion, thus improve the reliability of semiconductor power device.
Further, the present embodiment deposits on semiconductor power device semi-insulating polysilicon thin film and include following enforcement
Step.
1, the surface of silicon at semiconductor power device grows oxide layer.
Fig. 1 is oxide layer schematic diagram in the embodiment of the present invention, as it can be seen, silicon substrate includes silicon substrate N+ in the present embodiment
Layer 1 and silicon substrate N-layer 2, use the method for high-temperature oxydation to grow oxide layer 3 in surface of silicon after being carried out silicon substrate.
Wherein, the thickness of oxide layer 3 is 8000～20000 angstroms.
2, oxide layer is carried out photoetching and etching is formed with source region window.
Fig. 2 is active area window schematic diagram in the embodiment of the present invention, as it can be seen, be formed with source region window in the present embodiment
Can comprise the steps.
(1) in oxide layer 3, coat photoresist, and it is carried out baking reinforcing；
(2) photoresist is exposed；
(3) the part photoresist that should remove on silicon substrate after removing exposure with developer solution；
(4) oxide layer 3 being exposed at photoresist is performed etching so that silicon substrate herein comes out；
(5) remove the photoresist that surface of silicon is remaining, be finally exposed to the silicon substrate at oxide layer 3 and be active area
Window.
3, it is doped formation PN junction to silicon substrate.
Fig. 3 is PN junction schematic diagram in the embodiment of the present invention, as it can be seen, be doped formation to silicon substrate in the present embodiment
PN junction includes following enforcement step:
(1) at active area window surface of silicon growth layer of oxide layer as masking layer, its thickness be 300～
500 angstroms, it is possible to prevent when silicon substrate implanted dopant to damage；
(2) in the present embodiment, silicon substrate is N-type substrate, therefore to silicon substrate implantation dosage be 1e13-1e15 (atom/
Cm2) boron, injection condition is knot 1-5um under 1200 DEG C of condition of nitrogen gas.
4, in oxide layer 3 and deposit semi-insulating polysilicon thin film 5 in the plane, and to semi-insulating polysilicon thin film 5
Carry out photoetching and etching forms fairlead.
Fig. 4 is semi-insulating polysilicon thin film schematic diagram in the embodiment of the present invention, as it can be seen, semi-insulating many in the present embodiment
Polycrystal silicon film 5 be deposited on oxide layer 3 and be exposed to active area window partial silicon substrate on.
Further, the present embodiment deposits on semi-insulating polysilicon thin film nitration case and include following enforcement step.
In the environment of full nitrogen, semi-insulating polysilicon thin film is carried out laser annealing, form nitration case on its surface.
The present embodiment uses the mode deposited oxide layer of laser annealing, so that oxide layer possesses good stress
Joining property, and reduce the adhesiveness of oxide layer and silicon dioxide layer.Meanwhile, the temperature of nitrogen and silicon formation silicon nitride is greater than 900
DEG C, the temperature of deposit semi-insulating polysilicon thin film is generally 600～700 DEG C, and according to conventional silicon nitride deposition method, it forms sediment
Long-pending high temperature will change the physicochemical properties of semi-insulating polysilicon thin film, and laser annealing is only at semi-insulating polysilicon thin film
Shallow-layer machine is annealed, and does not affect the physicochemical properties of semi-insulating polysilicon thin film, and wherein the annealing degree of depth can be according to the wavelength not people having the same aspiration and interest
Whole.
Further, the present embodiment deposits on silicon dioxide layer passivation layer and include following enforcement step.
1, deposited metal on silicon dioxide layer 6, metal level inserts downwards fairlead and the active area with silicon substrate connects
Touch；Metal level is carried out photoetching and etching forms metal electrode 7.
Fig. 5 is silicon dioxide layer schematic diagram in the embodiment of the present invention, as it can be seen, silicon dioxide layer 6 is deposited on nitration case
On.
Fig. 6 is metal electrode schematic diagram in the embodiment of the present invention, as it can be seen, metal level is deposited on glass in the present embodiment
On passivation layer 6 and insert downwards in the fairlead that dielectric layer 5 is formed, with active region contact.
2, at the metal electrode 7 of semiconductor power device and deposit passivation layer 8 in the plane, and passivation layer 8 is entered
Row photoetching and etching form welding window.
In the present embodiment, passivation layer can use polyimide film layer.
Fig. 7 is passivation layer schematic diagram in the embodiment of the present invention, as it can be seen, passivation layer 8 is quasiconductor merit in the present embodiment
Last layer of passivation layer of rate device, constitutes MULTILAYER COMPOSITE with semi-insulating polysilicon thin film 5, nitration case, silicon dioxide layer 6 respectively
Structure, it is possible to significantly improve the sealing of semiconductor power device.
Present invention also offers a kind of semiconductor power device, and be given and be embodied as.
In the present embodiment semiconductor power device include silicon substrate, oxide layer, semi-insulating polysilicon thin film, nitration case, two
Silicon oxide layer, metal level and passivation layer.Wherein,
Silicon substrate can be P type substrate or N-type substrate.
Oxide layer deposits on a silicon substrate.
Semi-insulating polysilicon thin-film deposition is in oxide layer, and semi-insulating polysilicon thin film includes fairlead.
Nitration case is deposited on its surface by semi-insulating polysilicon thin film is carried out laser annealing.
Silicon dioxide layer is deposited on nitration case.
Metal level is deposited on silicon dioxide layer, and inserts downwards fairlead and the active region contact with silicon substrate.
Passivation layer deposits on the metal layer, and forms welding window on the metal layer.
In the present embodiment, semi-insulating polysilicon thin film, nitration case, silicon dioxide layer and passivation layer constitute multi-layer compound structure,
The sealing of semiconductor power device can be significantly improved so that it is when being applied under adverse circumstances, can also keep higher reliable
Property.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a terminal passivating method, it is characterised in that described method includes:
Semiconductor power device sequentially deposits semi-insulating polysilicon thin film, nitration case, silicon dioxide layer and passivation layer, is formed
Layer compound passivation layer.
2. a kind of terminal passivating method as claimed in claim 1, it is characterised in that described deposit on semiconductor power device
Include before semi-insulating polysilicon thin film:
Surface of silicon at described semiconductor power device grows oxide layer, described oxide layer carries out photoetching and etching is formed
Active area window, is doped formation PN junction to silicon substrate；
In described oxide layer and deposit semi-insulating polysilicon thin film in the plane, and described semi-insulating polysilicon thin film is entered
Row photoetching and etching form fairlead.
3. a kind of terminal passivating method as claimed in claim 1, it is characterised in that described shallow lake on semi-insulating polysilicon thin film
Long-pending nitration case includes:
In the environment of full nitrogen, described semi-insulating polysilicon thin film is carried out laser annealing, form nitration case on its surface.
4. a kind of terminal passivating method as claimed in claim 2, it is characterised in that described deposit passivation on silicon dioxide layer
Included before Ceng:
Deposited metal on described silicon dioxide layer, described metal level insert downwards described fairlead and with described silicon substrate
Active region contact；Described metal level is carried out photoetching and etching forms metal electrode.
5. a kind of terminal passivating method as claimed in claim 1, it is characterised in that deposit passivation on described silicon dioxide layer
Layer includes:
At the metal electrode of described semiconductor power device and deposit passivation layer in the plane, and described passivation layer is carried out
Photoetching and etching form welding window.
6. a kind of terminal passivating method as claimed in claim 2, it is characterised in that
The thickness of described oxide layer is 8000～20000 angstroms；
Described passivation layer is polyimide film layer.
7. a semiconductor power device, it is characterised in that described semiconductor power device includes:
Silicon substrate；
Oxide layer, described oxide layer is deposited on described silicon substrate；
Semi-insulating polysilicon thin film, described semi-insulating polysilicon thin-film deposition in described oxide layer, described semi-insulating polysilicon
Thin film includes fairlead；
Nitration case, described nitration case is grown in its surface by described semi-insulating polysilicon thin film is carried out laser annealing；
Silicon dioxide layer, described silicon dioxide layer is deposited on described nitration case；
Metal level, described metal level is deposited on described silicon dioxide layer, and inserts downwards described fairlead and serve as a contrast with described silicon
The active region contact at the end；
Passivation layer, described passivation layer is deposited on described metal level, and forms welding window on described metal level.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610843019.1A CN106252244A (en) | 2016-09-22 | 2016-09-22 | A kind of terminal passivating method and semiconductor power device |
| PCT/CN2017/093002 WO2018014792A1 (en) | 2016-07-20 | 2017-07-14 | Passivation layer manufacturing method, high-voltage semiconductor power device and front electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610843019.1A CN106252244A (en) | 2016-09-22 | 2016-09-22 | A kind of terminal passivating method and semiconductor power device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992207A (en) * | 2017-05-02 | 2017-07-28 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor terminal structure and power semiconductor |
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