CN210668387U

CN210668387U - Thyristor

Info

Publication number: CN210668387U
Application number: CN201922117414.3U
Authority: CN
Inventors: 张环; 朱迺茜; 周继峰
Original assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Current assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-06-02
Anticipated expiration: 2029-11-29

Abstract

A thyristor is disclosed, the thyristor comprising an N-type substrate having a first surface and a second surface opposite the first surface; the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate; the groove penetrates through the P-type doping layer from the surface, far away from the N-type substrate, of the P-type doping layer and extends into the substrate; the glass passivation protective layer is formed in the groove; and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.

Description

Thyristor

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a thyristor.

Background

Thyristors (thyristors) are short for thyristors and may also be called silicon controlled rectifiers; the thyristor has the characteristics of a silicon rectifier device, can work under the conditions of high voltage and large current, can control the working process, and is widely applied to electronic circuits such as controllable rectification, alternating current voltage regulation, contactless electronic switches, inversion, frequency conversion and the like.

However, existing series of dual-mesa thyristors, e.g. with junction temperatures of 125 ℃, typically use glass as passivation protection layer to ensure proper voltage blocking capability and long-term reliability, however, at 150 ℃, the glass formed passivation protection layer will greatly increase high temperature leakage, which easily leads to drift and reliability problems.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to solve at least one aspect of the above problems and disadvantages in the related art.

According to an embodiment of an aspect of the present disclosure, there is provided a thyristor including

An N-type substrate having a first surface and a second surface opposite the first surface;

the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate;

the groove penetrates through the P-type doping layer from the surface, far away from the N-type substrate, of the P-type doping layer and extends into the substrate; and

the glass passivation protective layer is formed in the groove;

and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.

In at least one embodiment, the semi-insulating polysilicon layer has a thickness of

To

In at least one embodiment, the thin oxygen layer has a thickness less than

In at least one embodiment, the thin oxide layer and the semi-insulating polysilicon layer are annealed.

In at least one embodiment, the annealing temperature is 800 to 850 °.

In at least one embodiment, the annealing treatment time is 20-60 minutes.

In at least one embodiment, the P-type doped layer is formed only on the first surface of the N-type substrate, and the second surface of the N-type substrate is formed with an N + -type emitter region.

In at least one embodiment, the P-type doped layer is formed on both the first surface and the second surface of the N-type substrate, and two N + -type emitter regions are formed in the P-type doped layer on the first surface.

In at least one embodiment, the P-type doped layers are formed on both the first surface and the second surface of the N-type substrate, and N + -type emitter regions are formed in the P-type doped layers on both the first surface and the second surface.

There is also provided, in accordance with an embodiment of another aspect of the present disclosure, a method of manufacturing a thyristor, the method including the steps of:

providing an N-type substrate;

forming a P-type doped layer on the N-type substrate;

forming a groove;

forming a thin oxide layer in the groove;

forming a semi-insulating polysilicon layer on the thin oxide layer;

and forming a glass passivation protective layer on the semi-insulating polycrystalline silicon layer.

To

In at least one embodiment, the thin oxygen layer has a thickness less than

In at least one embodiment, the method of manufacturing further comprises the step of annealing the thin oxide layer and the semi-insulating polysilicon layer prior to forming a glass passivation protection layer on the semi-insulating polysilicon layer.

In at least one embodiment, the manufacturing method has an annealing temperature of 800 to 850 °.

In at least one embodiment, the manufacturing method includes the annealing treatment time being 20-60 minutes.

In at least one embodiment, the method of manufacturing further comprises the step of cleaning the trench before forming a thin oxygen layer within the trench.

In at least one embodiment, the method further comprises the step of observing through a transmission electron microscope to determine the structures of the thin oxide layer and the semi-insulating polysilicon layer after forming the semi-insulating polysilicon layer on the thin oxide layer.

The thyristor and the manufacturing method thereof provided by the above embodiments of the present disclosure may help balance charge distribution near the junction depletion region by adding the thin TSIPOS layer below the glass passivation protective layer, so as to facilitate voltage stabilization, so as to further increase junction temperature while ensuring good reliability.

Drawings

Fig. 1 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure; and

fig. 4 is a flow chart of a method of manufacturing a thyristor according to an example embodiment of the present disclosure.

Detailed Description

While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it is to be understood before this description that one of ordinary skill in the art can, of course, modify the utility model described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.

According to the general inventive concept of the present disclosure, there is provided a thyristor including an N-type substrate having a first surface and a second surface opposite to the first surface; the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate; the surface of the P-type doped layer, which is far away from the N-type substrate, penetrates through the P-type doped layer and extends into the substrate, and the glass passivation protective layer is formed in the groove; and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.

Fig. 1 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.

In one exemplary embodiment, as shown in fig. 1, the thyristor includes an N-type substrate 1, such as N-type silicon; a first surface and a second surface opposite to the first surface of the N-type substrate 1 are both formed with a P-type doped layer 2. The thyristor further comprises an emitter region, in this embodiment N + -

type emitter regions

6, 7 are formed in the P-doped layer 2 on both the first and second surfaces of the N-type substrate 1. The thyristor further comprises a groove which penetrates through the P-type doped layer 2 from the surface of the P-type doped layer 2 far away from the N-type substrate 1 and extends to the N-type substrate 1, and a glass passivation protection layer 3 is formed in the groove. Wherein, a thin oxygen layer 4 is formed among the P-type doped layer 2, the N-type substrate 1 and the glass passivation protective layer 3, and a semi-insulating polysilicon layer 5 is formed between the thin oxygen layer 4 and the glass passivation protective layer 3. The thin oxygen layer 4 and the semi-insulating polysilicon layer 5 can be collectively referred to as a TSIPOS thin layer, and the thyristor can help balance charge distribution near a junction depletion region by adding the TSIPOS thin layer below the glass passivation protective layer 3, so that voltage stabilization is facilitated, leakage between the TSIPOS thin layer and the N-type substrate 1 and the P-type doped layer 2 is prevented, and junction temperature is further increased under the condition that good reliability is ensured.

Fig. 2 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.

In one exemplary embodiment, as shown in fig. 2, the thyristor includes an N-type substrate 1, such as N-type silicon; a P-type doped layer 2 is formed on both a first surface and a second surface opposite to the first surface of the N-type substrate 1. The thyristor further comprises an emitter region, in this embodiment two N + -type emitter regions 7' are formed in the P-doped layer only at the first surface of the N-type substrate 1. The thyristor further comprises a groove which penetrates through the P-type doped layer 2 from the surface of the P-type doped layer 2 far away from the N-type substrate 1 and extends to the N-type substrate 1, and a glass passivation protection layer 3 is formed in the groove. Wherein, a thin oxygen layer 4 is formed among the P-type doped layer 2, the N-type substrate 1 and the glass passivation protective layer 3, and a semi-insulating polysilicon layer 5 is formed between the thin oxygen layer 4 and the glass passivation protective layer 3. The thin oxygen layer 4 and the semi-insulating polysilicon layer 5 can be collectively referred to as a TSIPOS thin layer, and the thyristor can help balance charge distribution near a junction depletion region by adding the TSIPOS thin layer below the glass passivation protective layer 3, so that voltage stabilization is facilitated, leakage between the TSIPOS thin layer and the N-type substrate 1 and the P-type doped layer 2 is prevented, and junction temperature is further increased under the condition that good reliability is ensured.

Fig. 3 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.

In one exemplary embodiment, as shown in fig. 3, the thyristor includes an N-type substrate 1; only the first surface of the N-type substrate 1 is formed with the P-type doped layer 2, and the second surface of the N-type substrate 1 is formed with the N + -type emitter region 6'. The thyristor further comprises a groove which penetrates through the P-type doped layer 2 from the surface of the P-type doped layer 2 far away from the N-type substrate 1 and extends to the N-type substrate 1, and a glass passivation protection layer 3 is formed in the groove. Wherein, a thin oxygen layer 4 is formed among the P-type doped layer 2, the N-type substrate 1 and the glass passivation protective layer 3, and a semi-insulating polysilicon layer 5 is formed between the thin oxygen layer 4 and the glass passivation protective layer 3. The thin oxygen layer 4 and the semi-insulating polysilicon layer 5 can be collectively referred to as a TSIPOS thin layer, and the thyristor can help balance charge distribution near a junction depletion region by adding the TSIPOS thin layer below the glass passivation protective layer 3, so that voltage stabilization is facilitated, leakage between the TSIPOS thin layer and the N-type substrate 1 and the P-type doped layer 2 is prevented, and junction temperature is further increased under the condition that good reliability is ensured.

In one exemplary embodiment, as shown in fig. 1-3, the thin oxygen layer 4 has a thickness, for example, less than

It should be noted, however, that in other embodiments of the present disclosure, the thickness of the thin oxygen layer 4 may take other values, such as

In one exemplary embodiment, as shown in fig. 1-3, the semi-insulating polysilicon layer 5 has a thickness of

To

It should be noted, however, that in other embodiments of the present disclosure, the thickness of the semi-insulating polysilicon layer 5 may take other values, for example, as will be appreciated by those skilled in the art

In an exemplary embodiment, the thin layer of TSIPOS is annealed as shown in FIGS. 1-3. The annealing temperature may be, for example, 800 to 850 °. The annealing time may be, for example, 20 to 60 minutes, preferably 30 minutes. According to the thyristor, the TSIPOS thin layer is annealed, so that leakage between the TSIPOS thin layer and the N-type substrate 1 and between the TSIPOS thin layer and the P-type doped layer 2 can be further prevented, and junction temperature is further increased under the condition that good reliability is guaranteed.

According to another aspect of the present disclosure, as shown in fig. 4, there is also provided a method of manufacturing a thyristor, comprising the steps of: at block 21, an N-type substrate 1, such as N-type silicon, is provided. At block 22, forming a P-type doped layer 2 on an N-type substrate 1; among them, the dopant concentration in the P-type doped layer 2 and the layer thickness of the P-type doped layer 2 may be designed according to the electrical properties of the thyristor to be formed in the N-type substrate 1. In various embodiments, the layer thickness of the P-doped layer 2 may be, for example, in the range of 20 μm to 80 μm. At block 23, forming a trench; the trench may be formed by etching. The etching method comprises dry etching and wet etching. The dry etching includes light volatilization, gas phase etching, plasma etching and the like. In the embodiment, the used etching method is dry etching, so that automation is easier to realize, no pollution is introduced in the processing process, and the cleanliness is high. At block 25, growing a thin oxygen layer 4 within the trench; the thickness of the thin oxygen layer 4 is, for example, less than

At block 26, forming a semi-insulating polysilicon layer 5 on the thin oxide layer 4; forming a semi-insulating polysilicon layer 5 on the thin oxide layer 4, for example by low pressure chemical vapor deposition; and at block 29, a glass passivation protection layer 3 is formed on the semi-insulating polysilicon layer 5.

In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at block 27, a step of annealing the thin oxygen layer 4 and the semi-insulating polysilicon layer 5 (i.e., the thin layer of TSIPOS) before forming the passivation protection layer 3 on the semi-insulating polysilicon layer 4. The annealing temperature may be, for example, 800 to 850 °. The annealing time may be, for example, 20 to 60 minutes, preferably 30 minutes.

In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at block 28, the step of observing through a transmission electron microscope to determine the structure of the thin oxide layer 4 and the semi-insulating polysilicon layer 5 is also included after forming the semi-insulating polysilicon layer 5 on the thin oxide layer 4.

In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at block 24, the trench is cleaned prior to forming the thin oxide layer 4 within the trench.

The thyristor and the manufacturing method thereof provided by the above embodiments of the present disclosure may help balance charge distribution near the junction depletion region by adding the TSIPOS thin layer below the glass passivation protection layer, so as to be beneficial to voltage stabilization, and prevent leakage between the TSIPOS thin layer and the N-type substrate 1 and the P-type doping layer 2, so as to further increase junction temperature under the condition of ensuring good reliability. In addition, by annealing the TSIPOS thin layer, leakage between the TSIPOS thin layer and the substrate and between the TSIPOS thin layer and the P-type doped layer can be further prevented. Thus, the thyristor can further increase the junction temperature with good reliability, for example for a series of dual-mesa thyristors the junction temperature can be increased from 125 ℃ to 150 ℃.

It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.

Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.

Claims

1. A thyristor, characterized in that the thyristor comprises

the glass passivation protective layer is formed in the groove;

2. The thyristor according to claim 1, wherein the semi-insulating polysilicon layer has a thickness of

To

3. The thyristor of claim 2, wherein the thin oxygen layer has a thickness less than

4. The thyristor of claim 3, wherein the thin oxide layer and the semi-insulating polysilicon layer are annealed.

5. The thyristor of claim 4, wherein the annealing temperature is 800 to 850 °.

6. The thyristor according to claim 5, wherein the annealing time is 20-60 minutes.

7. The thyristor according to any one of claims 1-6, wherein the P-type doped layer is formed on only a first surface of the N-type substrate, and a second surface of the N-type substrate is formed with an N + -type emitter region.

8. The thyristor according to claim 7, wherein the P-doped layer is formed on both the first surface and the second surface of the N-type substrate, and wherein two N + -type emitter regions are formed in the P-doped layer on the first surface.

9. A thyristor according to any one of claims 1 to 6, wherein the P-doped layers are formed on both a first and a second surface of the N-type substrate, and N + -type emitter regions are formed within the P-doped layers on both the first and the second surface.