CN107275393A - Silicon carbide MOSFET device and preparation method thereof - Google Patents

Silicon carbide MOSFET device and preparation method thereof Download PDF

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Publication number
CN107275393A
CN107275393A CN201610216970.4A CN201610216970A CN107275393A CN 107275393 A CN107275393 A CN 107275393A CN 201610216970 A CN201610216970 A CN 201610216970A CN 107275393 A CN107275393 A CN 107275393A
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type doped
doped region
contact
carried out
doping concentration
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高云斌
李诚瞻
赵艳黎
陈喜明
蒋华平
刘国友
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Zhuzhou CRRC Times Electric Co Ltd
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Zhuzhou CRRC Times Electric Co Ltd
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Abstract

The present invention relates to a kind of silicon carbide metal-oxide-semiconductor FET device, it is characterised in that in the junction field effect transistor area of the metal-oxide semiconductor fieldeffect transistor device, along perpendicular to raceway groove and parallel to SiO2P-type doped region and n-type doped region alternately is distributed with the direction at/SiC interfaces.The invention further relates to its preparation method.

Description

Silicon carbide MOSFET device and preparation method thereof
Technical field
The present invention relates to a kind of electronic device, more particularly to a kind of transistor device.The invention further relates to the device Preparation method.
Background technology
Relative to the first generation semiconductor using silicon as representative and the second generation semiconductor by representative of GaAs, make There is bigger energy gap and critical breakdown electric field for the carbofrax material that third generation semiconductor is represented, so that suitable Close manufacture high-power semiconductor devices.It is used as power electronic in the world and the heat of field of novel research Point, SiC is paid much attention to by educational circles all the time, and in companies such as Cree, Rohm, Infineon Under tackling key problem is promoted, into commercialization stage.
For a kind of power device of high-performance high reliability, it is desirable to have sufficiently high voltage endurance capability, height is born Press main circuit break-make；Meanwhile, to have an as far as possible low conducting resistance, reduce device working loss, reach efficiently, Environmental protection and the requirement of energy-conservation.
It is worth noting that, compared to silicon substrate MOSFET element, the critical breakdown electric field of carbofrax material is strong Degree can reach 2-3MV/cm, according to the electric flux principle of continuity at oxide interface, be tied when device bears pressure-resistant Gate oxide electric-field intensity can easily exceed 4MV/cm, serious shadow above type field-effect transistor (JFET) area Ring reliability of the gate oxide.Therefore in traditional devices, generally using narrower JFET sector widths, higher p Trap doping concentration and larger p traps junction depth design, suppress gate oxide electric field above JFET areas and concentrate.However, The drift region of silicon carbide-based MOSFET element is relatively thin, and JFET areas and channel resistance account for device on-resistance ratio It is larger, therefore also need increase JFET areas doping concentration, reduce the region conducting resistance, such as profile 1a and bow Shown in view 1b.
In addition, also reverse-biased pn can be utilized using ion implantation technology in JFET areas formation highly-doped p-type region Knot depletion region carrys out suppressor electric field across oxide concentration, as shown in profile 2a and top view 2b.But this method meeting Reduce the effective width in JFET areas, increase device on-resistance.
Reduce JFET sector widths and increase p-well region doping concentration and junction depth, on the one hand increase break-over of device electricity Resistance, on the other hand need to use high energy high dose Al ion implantation, increase technology difficulty.And use ion implanting Technique forms highly-doped p-type region in JFET areas, and the carrier that can suppress JFET areas is concentrated, and increase device is led Be powered resistance.Therefore, the effect of both schemes of the prior art is unsatisfactory.
The content of the invention
In order to solve above-mentioned problems of the prior art, effectively strengthen gate oxide voltage endurance, improve grid Oxide layer reliability, the present invention proposes the modified carborundum gold of a kind of use JFET areas p-type and n-type injection Category-Oxide-Semiconductor Field effect transistor (MOSFET) device.Using device profile along channel direction as X Axle, device profile is Y-axis perpendicular to channel direction, then along Z-direction, p-type is alternatively formed in JFET areas Doping and n-type doped region, using charge balance concept, effectively reduce gate oxide electric-field intensity.Then fill Divide extension design margin, by using wider JFET plot structures, reduce device on-resistance.
The invention provides a kind of silicon carbide MOSFET device, it is characterised in that in the MOSFET devices The JFET areas of part, along perpendicular to raceway groove and parallel to SiO2P-type alternately is distributed with the direction at/SiC interfaces to mix Miscellaneous region and n-type doped region.
As shown in profile 3a and top view 3b, the silicon carbide MOSFET device in the present invention, using p The JFET areas that type and n-type doped region are arranged alternately.
Under device on-state, electric current extends to n-type epitaxial layer by n-type doped region.In device shut-off Under state, based on charge balance concept, p-type and n-type doped region all exhaust, so as to shield grid oxygen completely Change the electric field at layer, improve reliability of the gate oxide.
After this scheme, you can the relatively wide JFET areas of design, it is ensured that the low conducting resistance of device.
The present invention one preferred embodiment in, in the JFET areas, the p-type doped region Number to be one or more, the number of the n-type doped region is one or more.
The present invention one preferred embodiment in, perpendicular to raceway groove and parallel to SiO2/ SiC interfaces On direction (i.e. in the Z-axis direction), the product of the width and its dopant dose of each p-type doped region is homogeneous Deng, and the product of the width and its dopant dose equal to each n-type doped region.Thus, shape is turned off in device Under state, it is possible to achieve charge balance, p-type and n-type doped region all exhaust, so as to shield gate oxidation completely Electric field at layer, improves reliability of the gate oxide.
The present invention one preferred embodiment in, perpendicular to raceway groove and parallel to SiO2/ SiC interfaces On direction, the width of p-type doped region and/or n-type doped region is 1 μm to 5 μm.With reference to device cellular Design size, and consider the alignment precision of ion implantation technology, the width is particularly suitable.
It is preferred that, p-type and n-type doped region junction depth are 0.2 μm to 1 μm, and Y-direction length is 2 μm to 6 μm, Through whole JFET areas.
The present invention one preferred embodiment in, in the p-type doped region and the n-type doped region Dopant dose is respectively 1 × 10 in domain12cm-2To 5 × 1013cm-2In the range of.The unit cm of the dopant dose-2 It is unit sanctified by usage in ion implantation technology, represents the amount of ions injected on material every square centimeter.This The inventor of invention has found that the scope of the preferred dopant dose enables to uniform doping by many experiments, With especially good doping effect.On the premise of charge balance is ensured, it is contemplated that ion implantation technology is dense Spend the complexity of control aspect, too high or too low Uniform Doped all relatively difficult to achieve.In addition, dopant dose is too high Extra avalanche effect can also be introduced.
It is a further object of the invention to provide the method for preparing above-mentioned device, comprise the following steps：
1) epitaxial growth goes out N on sic substrates-Drift layer；
2) in step 1) made from N-Carried out on drift layer twice or more than twice, preferably three times or four secondary aluminiums from Son injection, forms p-well；
3) in step 2) Al ion implantation is carried out in the p-well that is formed, form P+Contact；
4) in step 3) obtained form P+N~+ implantation is carried out in the p-well of contact, N is formed+Contact；
5) N~+ implantation is carried out in JFET areas, forms N-Region；
6) Al ion implantation is carried out in JFET areas, forms P-Region；
7) annealed using carbon film protection；
8) at a temperature of 1100 DEG C to 1400 DEG C, preferably at a temperature of 1200 DEG C to 1350 DEG C, dry oxygen heat is raw Long 40 to 100nm, preferably 40 to 60nm SiO2Gate medium；
9) in SiO2Deposit 0.4 to 0.6um, doping concentration are 1 × 10 on gate medium20cm-3To 3 × 1020cm-3 Polysilicon；
10) dry etching formation polygate electrodes figure；
11) in source region N+Contact, P+Contact and SiC wafer rears deposit 30 to 100nm Ti and 100 to 300nm Al, as metal ohmic contact, and anneal, to form Ohmic contact.
The present invention one preferred embodiment in, step 9 in the above-mentioned methods) in, the deposit Carried out using low-pressure chemical vapor phase deposition method.
Manufacture is foregoing to have the SiC MOSFET for being arranged alternately p-type and n-type doped region, and key is JFET The ion implanting and annealing activation of area's p-type and p-type impurity, its technological process is referring to Fig. 4.
The present invention one preferred embodiment in, step 1) described in N-The thickness of drift layer is 10 To 13um, Nitrogen ion doping concentration is 1 × 1015cm-3To 9 × 1015cm-3；
Step 2) described in the depth of p-well be that 0.5 to 1.0um, doping concentration is 1 × 1018cm-3Extremely 5×1018cm-3；
Step 3) described in P+The junction depth of contact is 0.2 to 0.3um, and doping concentration is 1 × 1019cm-3Extremely 5×1019cm-3；
Step 4) described in N+The junction depth of contact is 0.2 to 0.3um, and doping concentration is 1 × 1019cm-3Extremely 5×1019cm-3；
Step 5) described in N-The junction depth in region is that 0.2 to 1.0um, doping concentration is 5 × 1016cm-3Extremely 5×1017cm-3；And
Step 6) described in P-The junction depth in region is that 0.2 to 1.0um, doping concentration is 5 × 1016cm-3Extremely 5×1017cm-3。
The present invention one preferred embodiment in, step 7) described in annealing at 1600 DEG C to 1800 DEG C At a temperature of carry out, annealing time is that the annealing is preferably carried out in the lehr, is more preferably existed 3 to 10min Carried out in carborundum special-purpose high temperature annealing furnace.
One of the present invention preferred embodiment in, step 8) the dry oxygen is thermally grown enters in oxidation furnace OK, carried out preferably in carborundum special-purpose high temperature oxidation furnace.
The present invention one preferred embodiment in, step 11) described in anneal at 800 DEG C to 1000 DEG C At a temperature of and carried out in inert gas atmosphere, preferably blanket of nitrogen, the annealing time of the annealing for 2 to 5min。
One of the present invention preferred embodiment in, the of the invention method for preparing above-mentioned device is including as follows Step：
1) epitaxial growth thickness is that 10 to 13um, Nitrogen ion doping concentration is 1 × 10 on sic substrates15cm-3 To 9 × 1015cm-3N-Drift layer (see Fig. 5)；
2) it is that 10 to 13um, Nitrogen ion doping concentration is 1 × 10 in thickness15cm-3To 9 × 1015cm-3The step of 1) N made from-Three times or four Al ion implantations are carried out on drift layer, depth is formed and is 0.5 to 1.0um, mixes Miscellaneous concentration is 1 × 1018cm-3To 5 × 1018cm-3P-well (see Fig. 6)；
3) in step 2) formed p-well on carry out Al ion implantation, is formed junction depth be 0.2 to 0.3um, mix Miscellaneous concentration is 1 × 1019cm-3To 5 × 1019cm-3P+Contact is (see Fig. 7)；
4) in step 3) obtained form P+N~+ implantation is carried out in the p-well of contact, forming junction depth is 0.2 to 0.3um, doping concentration is 1 × 1019cm-3To 5 × 1019cm-3N+Contact is (see Fig. 8)；
5) N~+ implantation is carried out in JFET areas, it is that 0.2 to 1.0um, doping concentration is to form junction depth 5×1016cm-3To 5 × 1017cm-3N-Region (see Fig. 9, including Fig. 9 a and Fig. 9 b)；
6) Al ion implantation is carried out in JFET areas, it is that 0.2 to 1.0um, doping concentration is to form junction depth 5×1016cm-3To 5 × 1017cm-3P-Region (see Figure 10, including Figure 10 a and Figure 10 b)；
7) in high-temperature annealing furnace, protected using carbon film, at a temperature of 1600 DEG C to 1800 DEG C, annealing 3 to 10min；
8) in high temperature oxidation furnace, at a temperature of 1200 DEG C to 1350 DEG C, dry oxygen thermally grown 40 to 60nm SiO2 Gate medium (see Figure 11)；
9) in SiO2Used on gate medium low-pressure chemical vapor phase deposition method deposit 0.4 to 0.6um, doping concentration for 1×1020cm-3To 3 × 1020cm-3Polysilicon (see Figure 12)；
10) dry etching formation polygate electrodes figure (see Figure 13)；
11) in source region N+Contact, P+Contact and SiC wafer rears deposit 30 to 100nm Ti and 100 to 300nm Al, as metal ohmic contact, and the annealing 2 to 5min in 800 DEG C to 1000 DEG C nitrogen atmospheres Form Ohmic contact (see Figure 14).
In the context of the present invention, " carborundum " refers to a kind of solid crystals, is one as semiconductor silicon Semi-conducting material is planted, available for manufacture semiconductor devices and integrated circuit.It is critical because its energy gap is larger Breakdown electric field is higher, is usually used in manufacturing power device.
In the context of the present invention, " extension " refers to a kind of mode of Material growth, and its material grown is Crystal.The silicon carbide layer that for example floor height of extension one hinders on sic.
In the context of the present invention, " knot terminal " (sometimes referred to as " terminal ") refers to power semiconductor device Concentrated in part to reduce electric field so as to improve structure that is pressure-resistant and specially doing.
In the context of the present invention, " silicon-based devices " refer to a kind of device manufactured based on semiconductor silicon, lead to It is often the device being fabricated to using semi-conductor silicon chip as main material.
In the context of the present invention, " N-type " (" p-type ") refers to an attribute of semi-conducting material, Turn into N-type (p-type) semiconductor if the main conduction by electronics (hole) of the semiconductor after doping.
The beneficial effects of the present invention are：Relative to existing MOSFET element, MOSFET of the invention Devices use charge balance concept, gate oxide electric-field intensity when can effectively reduce pressure-resistant, improving gate oxide can By property, so as to be designed using wider JFET areas, low conducting resistance is realized.
Brief description of the drawings
Fig. 1 a and 1b are respectively the sectional structure chart and overlooking structure figure of traditional Si C MOSFET elements.
Fig. 2 a and 2b are respectively the section knot that JFET areas p+ of the prior art injects SiC MOSFET elements Composition and overlooking structure figure.
Fig. 3 a and 3b are respectively the SiC MOSFET devices with n-type and the injection of p-type JFET areas of the present invention The sectional structure chart and overlooking structure figure of part.
Fig. 4 is the SiC MOSFET for being arranged alternately p-type and n-type doped region of present invention manufacture method Flow chart.
Fig. 5-14 is respectively outer layer growth, p-well injection, P+ injects, N+ injects, JFET areas N- injects, JFET areas P- injections, thermally grown gate oxide, polycrystalline silicon deposit, polysilicon graphics, ohmic metal contact Process schematic diagram.
Embodiment
With reference to non-limiting specific embodiment, the invention will be further described, but the protection model of the present invention Enclose and be not limited to following embodiments.
Embodiment 1
The silicon carbide MOSFET device of the present invention is prepared, is comprised the following steps：
1) epitaxial growth thickness is that 10 to 13um, Nitrogen ion doping concentration is 1 × 10 on sic substrates15cm-3 To 9 × 1015cm-3N-Drift layer (see Fig. 5)；
2) it is that 10 to 13um, Nitrogen ion doping concentration is 1 × 10 in thickness15cm-3To 9 × 1015cm-3The step of 1) N made from-Three times or four Al ion implantations are carried out on drift layer, depth is formed and is 0.5 to 1.0um, mixes Miscellaneous concentration is 1 × 1018cm-3To 5 × 1018cm-3P-well (see Fig. 6)；
3) in step 2) formed p-well on carry out Al ion implantation, is formed junction depth be 0.2 to 0.3um, mix Miscellaneous concentration is 1 × 1019cm-3To 5 × 1019cm-3P+Contact is (see Fig. 7)；
4) in step 3) obtained form P+N~+ implantation is carried out in the p-well of contact, forming junction depth is 0.2 to 0.3um, doping concentration is 1 × 1019cm-3To 5 × 1019cm-3N+Contact is (see Fig. 8)；
5) N~+ implantation is carried out in JFET areas, it is that 0.2 to 1.0um, doping concentration is to form junction depth 5×1016cm-3To 5 × 1017cm-3N-Region (see Fig. 9, including Fig. 9 a and Fig. 9 b)；
6) Al ion implantation is carried out in JFET areas, it is that 0.2 to 1.0um, doping concentration is to form junction depth 5×1016cm-3To 5 × 1017cm-3P-Region (see Figure 10, including Figure 10 a and Figure 10 b)；
7) in high-temperature annealing furnace, protected using carbon film, at a temperature of 1600 DEG C to 1800 DEG C, annealing 3 to 10min；
8) in high temperature oxidation furnace, at a temperature of 1200 DEG C to 1350 DEG C, dry oxygen thermally grown 40 to 60nm SiO2 Gate medium (see Figure 11)；
9) in SiO2Used on gate medium low-pressure chemical vapor phase deposition method deposit 0.4 to 0.6um, doping concentration for 1×1020cm-3To 3 × 1020cm-3Polysilicon (see Figure 12)；
10) dry etching formation polygate electrodes figure (see Figure 13)；
11) in source region N+Contact, P+Contact and SiC wafer rears deposit 30 to 100nm Ti and 100 to 300nm Al, as metal ohmic contact, and the annealing 2 to 5min in 800 DEG C to 1000 DEG C nitrogen atmospheres Form Ohmic contact (see Figure 14).
It should be noted that embodiment described above is only used for explaining the present invention, do not constitute to the present invention's Any limitation.By referring to exemplary embodiments, invention has been described, it should be appreciated that wherein used Word is descriptive and explanatory vocabulary, rather than limited vocabulary.Can be by regulation in the claims in the present invention In the range of the present invention is modified, and in without departing substantially from scope and spirit of the present invention to the present invention progress Revision.Although the present invention described in it is related to specific method, material and embodiment, it is not intended that The present invention is limited to wherein disclosed particular case, on the contrary, to can be extended to other all with identical function by the present invention Methods and applications.

Claims (10)

1. a kind of silicon carbide metal-oxide-semiconductor FET device, it is characterised in that described The junction field effect transistor area of metal-oxide semiconductor fieldeffect transistor device, along perpendicular to raceway groove simultaneously Parallel to SiO2P-type doped region and n-type doped region alternately is distributed with the direction at/SiC interfaces.
2. device according to claim 1, it is characterised in that in the junction field effect transistor area In, the number of the p-type doped region be it is one or more, the number of the n-type doped region for one or It is multiple.
3. device according to claim 1 or 2, it is characterised in that perpendicular to raceway groove and parallel to SiO2On the direction at/SiC interfaces, the width of each p-type doped region is equal with the product of its dopant dose, And the product of the width equal to each n-type doped region and its dopant dose.
4. the device according to any one of claim 1-3, it is characterised in that perpendicular to raceway groove and putting down Row is in SiO2On the direction at/SiC interfaces, the width of p-type doped region and/or n-type doped region for 1 μm extremely 5μm。
5. the device according to any one of claim 1-4, it is characterised in that in the p-type doped region Dopant dose is respectively 1 × 10 in domain and the n-type doped region12cm-2To 5 × 1013cm-2In the range of.
6. preparing the method for the device according to any one of claim 1-5, comprise the following steps：
1) epitaxial growth goes out N on sic substrates-Drift layer；
2) in step 1) made from N-Carried out on drift layer twice or more than twice, preferably three times or four secondary aluminiums from Son injection, forms p-well；
3) in step 2) Al ion implantation is carried out in the p-well that is formed, form P+Contact；
4) in step 3) obtained form P+N~+ implantation is carried out in the p-well of contact, N is formed+Contact；
5) N~+ implantation is carried out in junction field effect transistor area, forms N-Region；
6) Al ion implantation is carried out in junction field effect transistor area, forms P-Region；
7) annealed using carbon film protection；
8) at a temperature of 1100 DEG C to 1400 DEG C, preferably at a temperature of 1200 DEG C to 1350 DEG C, dry oxygen heat is raw Long 40 to 100nm, preferably 40 to 60nm SiO2Gate medium；
9) in SiO2Deposit 0.4 to 0.6um, doping concentration are 1 × 10 on gate medium20cm-3To 3 × 1020cm-3 Polysilicon；
10) dry etching formation polygate electrodes figure；
11) in source region N+Contact, P+Contact and SiC wafer rears deposit 30 to 100nm Ti and 100 to 300nm Al, as metal ohmic contact, and anneal, to form Ohmic contact.
7. method according to claim 6, it is characterised in that step 1) described in N-Drift layer Thickness is 10 to 13um, and Nitrogen ion doping concentration is 1 × 1015cm-3To 9 × 1015cm-3；
Step 2) described in the depth of p-well be that 0.5 to 1.0um, doping concentration is 1 × 1018cm-3Extremely 5×1018cm-3；
Step 3) described in P+The junction depth of contact is 0.2 to 0.3um, and doping concentration is 1 × 1019cm-3Extremely 5×1019cm-3；
Step 4) described in N+The junction depth of contact is 0.2 to 0.3um, and doping concentration is 1 × 1019cm-3Extremely 5×1019cm-3；
Step 5) described in N-The junction depth in region is that 0.2 to 1.0um, doping concentration is 5 × 1016cm-3Extremely 5×1017cm-3；And
Step 6) described in P-The junction depth in region is that 0.2 to 1.0um, doping concentration is 5 × 1016cm-3Extremely 5×1017cm-3。
8. the method according to claim 6 or 7, it is characterised in that step 7) described in annealing exist Carried out at a temperature of 1600 DEG C to 1800 DEG C, annealing time is for 3 to 10min, and the annealing is preferably in the lehr Carry out.
9. the method according to any one of claim 6-8, it is characterised in that step 8) the dry oxygen It is thermally grown to be carried out in oxidation furnace.
10. the method according to any one of claim 6-9, it is characterised in that step 11) described in Annealing is carried out at a temperature of 800 DEG C to 1000 DEG C and in inert gas atmosphere, preferably blanket of nitrogen, described to move back The annealing time of fire is 2 to 5min.
CN201610216970.4A 2016-04-08 2016-04-08 Silicon carbide MOSFET device and preparation method thereof Pending CN107275393A (en)

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