CN114582975A - SiC MOSFET device with low specific on-resistance and preparation method thereof - Google Patents

SiC MOSFET device with low specific on-resistance and preparation method thereof Download PDF

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CN114582975A
CN114582975A CN202210126895.8A CN202210126895A CN114582975A CN 114582975 A CN114582975 A CN 114582975A CN 202210126895 A CN202210126895 A CN 202210126895A CN 114582975 A CN114582975 A CN 114582975A
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region
type
heavily doped
drift region
doped semiconductor
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王俊
张倩
邓高强
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Hunan University
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Hunan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

The invention belongs to the technical field of power semiconductor devices, and relates to a SiC MOSFET device with low on-resistance, which comprises an N-type semiconductor drift region formed on an N-type heavily doped semiconductor substrate; the P-type well region and the JFET region formed on the surface of the N-type semiconductor drift region are formed on the P-type heavily doped semiconductor body contact region and the N-type heavily doped semiconductor source region on the surface of the P-type well region; and the planar gate structure is formed on the N-type heavily doped semiconductor source region, the P well region and the JFET region and comprises an oxide layer and polycrystalline silicon. Introducing a trench shielding gate structure which comprises insulating media and conducting materials, is inclined at a certain angle at the side wall and extends to the N-type semiconductor drift region, into the P-type heavily doped semiconductor body contact region and the side face of the P well region, and enabling the shielding gate to be in short circuit with the source electrode; and the P-type doped region is introduced into the bottom and the side surface of the trench shielding gate structure to assist in depleting the drift region, so that the concentration of the drift region is improved, the specific on-resistance of the device is reduced, and the performance of the device is improved.

Description

SiC MOSFET device with low specific on-resistance and preparation method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a SiC MOSFET device with low on-resistance and a preparation method thereof.
Background
With the increasing development of scientific technology, the performance of the traditional silicon-based power is close to the theoretical limit, and third-generation wide bandgap semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN) have better electrothermal characteristics, thereby causing extensive attention and intensive research. The SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) is rapidly developed and successfully applied to the Field of power systems due to its characteristics of high breakdown voltage, switching speed, thermal conductivity, low on-resistance and switching loss, and the like.
Due to the huge application prospect of the SiC MOSFET under the conditions of high frequency, high temperature and high power density, how to further improve the performance advantage of the SiC MOSFET becomes a problem of important attention in academic circles and industrial circles at home and abroad. The requirements for widely used power MOSFETs are higher reverse breakdown voltage, lower on-resistance and faster switching speed. The invention can reduce the specific on-resistance of the SiC MOSFET and further improve the device performance on the basis of the traditional SiC MOSFET.
Disclosure of Invention
In order to solve the problems, the invention provides a SiC MOSFET device with low specific on-resistance, which can reduce the specific on-resistance of the device and improve the performance of the device.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a SiC MOSFET device with low on-resistance structurally comprises an N-type heavily doped semiconductor substrate; the N-type semiconductor drift region is formed on the N-type heavily doped semiconductor substrate, the N-type semiconductor drift region is formed on the N-type semiconductor drift region, and the doping concentrations of the N-type semiconductor drift region and the N-type semiconductor drift region are different; the P well region and the JFET region are formed on the surface of the N-type semiconductor drift region; a P-type heavily doped semiconductor body contact region and an N-type heavily doped semiconductor source region formed on the surface of the P well region; the planar gate structure is formed on the N-type heavily doped semiconductor source region, the P well region and the JFET region and comprises an oxide layer and polycrystalline silicon, and a gate electrode is led out of the polycrystalline silicon; a source electrode is led out from the P-type heavily doped semiconductor body contact region and the N-type heavily doped semiconductor source region together, and a drain electrode is led out from the lower surface of the N-type heavily doped semiconductor substrate;
introducing a side wall comprising an insulating medium and a conductive material into the P-type heavily doped semiconductor body contact region and the side surface of the P-well region, wherein the side wall is inclined at a certain angle, the bottom of the side wall extends to a groove shielding gate structure in the N-type semiconductor drift region, and the shielding gate is in short circuit with the source electrode; and introducing P-type doped regions at the bottom and the side face of the trench shielding gate structure, wherein the P-type doped regions are positioned in the N-type semiconductor drift region and surround the bottom and most of the side wall of the trench shielding gate structure.
Preferably, the doping concentration of the N-type semiconductor drift region is greater than the doping concentration of the N-type semiconductor drift region.
Based on one general inventive concept, another object of the present invention is to provide a method for manufacturing the above SiC MOSFET device with low on-resistance, which is characterized by comprising the steps of:
selecting a SiC N + type substrate and sequentially extending to obtain an N type semiconductor drift region, an N type semiconductor drift region and a JFET region; forming a shielding gate trench; forming a P-type doped region; forming a shielding grid structure; forming a P well region; forming a polysilicon planar gate structure; forming an N-type heavily doped semiconductor source region; forming a P-type heavily doped semiconductor body contact region; forming a contact electrode.
Preferably, the shielding gate trench with the inclined side wall is formed by etching, and the P-type doped region surrounding the bottom and most of the side wall of the shielding gate structure of the trench is directly formed by one or more times of ion implantation due to the inclined side wall of the trench.
Compared with the prior art, the invention has the following advantages and positive effects:
1. the invention introduces a groove shielding grid structure with an inclined side wall, so that a P-type doped region can be directly obtained through simple ion implantation, and the groove shielding grid structure which is in short circuit with a source electrode can also play a two-dimensional charge coupling role, thereby reducing the contradiction between the reduction of the on-resistance and the improvement of the breakdown voltage.
2. According to the invention, the P-type doped region is introduced into the drift region at the bottom and the side surface of the trench shielding gate structure, the P-type doped region is used for assisting in depleting the N-type semiconductor drift region, based on the charge balance principle, the doping concentration of the drift region is increased under the condition of realizing the same withstand voltage, the specific on-resistance of the device is reduced, meanwhile, the P-type doped region can reduce the electric field near the shielding gate under the withstand voltage state, and the distribution of the electric field in the device is optimized.
Drawings
FIG. 1 is a schematic structural view of example 1 of the present invention;
FIG. 2 is a schematic structural diagram of example 2 of the present invention;
FIGS. 3 to 11 are diagrams illustrating respective steps of a preparation method of example 3 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, it is obvious that the described embodiments are some, but not all embodiments of the present invention, and the description in this section is only exemplary and explanatory, and should not be construed as limiting the scope of the present invention in any way. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
As shown in fig. 1, a SiC MOSFET device with low on-resistance: an N-type semiconductor drift region 2 is formed on an N-type heavily doped semiconductor substrate 1, and an N-type semiconductor drift region 3 is formed on the N-type semiconductor drift region 2; forming a P well region 8 and a JFET region 12 on the surface of the N-type semiconductor drift region 3; forming a P-type heavily doped semiconductor body contact region 9 and an N-type heavily doped semiconductor source region 1 on the surface of the P well region 8); forming a planar gate structure comprising an oxide layer 5 and polysilicon 7 on the N-type heavily doped semiconductor source region 10, the P well region 8 and the JFET region 12, and leading out a gate electrode from the polysilicon 7; and a source electrode is led out from the P-type heavily doped semiconductor body contact region 9 and the N-type heavily doped semiconductor source region 10 together, and a drain electrode is led out from the lower surface of the N-type heavily doped semiconductor substrate 1. The method is characterized in that a groove shielding gate structure which comprises an insulating medium 11 and a conducting material 6 and has a side wall inclined at a certain angle and a bottom extending into an N-type semiconductor drift region 3 is introduced into the side surfaces of the P-type heavily doped semiconductor body contact region 9 and the P-well region 8, and the shielding gate is in short circuit with a source electrode; and introducing a P-type doped region 4 at the bottom and the side face of the trench shielding gate structure, wherein the P-type doped region 4 is positioned in the N-type semiconductor drift region 2 and the N-type semiconductor drift region 3 and surrounds the bottom and most of the side wall of the trench shielding gate structure.
In the present embodiment, the doping concentration of the N-type semiconductor drift region 2 is greater than the doping concentration of the N-type semiconductor drift region 3.
Example 2
As shown in fig. 2, the difference between this embodiment and embodiment 1 is that the control gate in embodiment 1 is a planar gate structure, and the control gate in this embodiment is a trench gate structure.
Example 3
A preparation method of a SiC MOSFET device with low on-resistance comprises the following steps:
s1, selecting a SiC N + substrate layer 1, and sequentially growing an N-type semiconductor drift region 2 on the surface of the substrate layer 1, an N-type semiconductor drift region 3 on the surface of the N-type semiconductor drift region 2, and a JFET region 12 on the surface of the N-type semiconductor drift region 3 by using an epitaxial growth process, as shown in FIG. 3;
s2, forming a shielding grid groove: as shown in fig. 4, a trench area window is etched, trench etching and damage layer removal are performed, and a shielding gate trench with an inclined side wall is obtained;
s3, forming a P-type doped region 4: as shown in fig. 5, a P-type doped region window is photoetched, phosphorus ions are implanted, and a P-type doped region 4 is formed by advancing and annealing;
s4, forming a shielding grid structure: as shown in fig. 6, an insulating medium 11 and a conductive material 6 are deposited in sequence, and then etching of the conductive material 6 and etching of the insulating medium 11 are performed to form a shielding gate structure;
s5, forming a P well region 8: as shown in fig. 7, a P-well region doping window is photoetched, a sacrificial oxide layer is grown by sputtering, boron ions are injected, then the sacrificial oxide layer is etched, and then a P-well region 8 is formed by pushing and annealing;
s6, forming a polycrystalline silicon planar gate structure: as shown in fig. 8, a gate oxide layer is grown by oxidation, polysilicon is deposited and doped, polysilicon is etched and the oxide layer is etched, so that a polysilicon planar gate structure is formed;
s7, forming an N-type heavily doped semiconductor source region 10: as shown in fig. 9, a source region doping window is photoetched, a sacrificial oxide layer is grown by sputtering, phosphorus ions are injected, then the sacrificial oxide layer is etched, and then an N-type heavily doped semiconductor source region 10 is formed by advancing and annealing;
s8, forming a P-type heavily doped semiconductor body contact region 9: as shown in fig. 10, a P-type heavily doped region doping window is photoetched, a sacrificial oxide layer is grown by sputtering, boron ions are injected and then the sacrificial oxide layer is etched, and then the P-type heavily doped semiconductor body contact region 9 is formed by pushing and annealing;
s9, forming a contact electrode: sputtering a metal aluminum film on the front surface of the device, and reversely etching an aluminum metallization pattern to be used as source electrode contact metal and gate electrode contact metal; and sputtering multiple layers of metal films on the back surface of the device and alloying to be used as drain contact metal.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.
The above embodiments are merely preferred embodiments of the present invention, and any simple modification, modification and substitution changes made to the above embodiments according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.

Claims (4)

1. A SiC MOSFET device with low on-resistance, characterized in that it has a structure comprising an N-type heavily doped semiconductor substrate (1); an N-type semiconductor drift region (2) formed on the N-type heavily doped semiconductor substrate (1) and an N-type semiconductor drift region (3) formed on the N-type semiconductor drift region (2), wherein the doping concentrations of the N-type semiconductor drift region (2) and the N-type semiconductor drift region (3) are different; a P well region (8) and a JFET region (12) which are formed on the surface of the N-type semiconductor drift region (3); a P type heavily doped semiconductor body contact region (9) and an N type heavily doped semiconductor source region (10) which are formed on the surface of the P well region (8); the planar gate structure is formed on the N-type heavily doped semiconductor source region (10), the P well region (8) and the JFET region (12) and comprises an oxide layer (5) and polysilicon (7), and a gate electrode is led out of the polysilicon (7); a source electrode is led out from the P-type heavily doped semiconductor body contact region (9) and the N-type heavily doped semiconductor source region (10) together, and a drain electrode is led out from the lower surface of the N-type heavily doped semiconductor substrate (1);
a side wall comprising an insulating medium (11) and a conductive material (6) is introduced into the side faces of the P-type heavily doped semiconductor body contact region (9) and the P-well region (8), the side wall inclines at a certain angle, the bottom of the side wall extends to a groove shielding gate structure in the N-type semiconductor drift region (3), and the shielding gate is in short circuit with a source electrode; and introducing a P-type doped region (4) at the bottom and the side face of the trench shielding gate structure, wherein the P-type doped region (4) is positioned in the N-type semiconductor drift region (2) and the N-type semiconductor drift region (3) and surrounds the bottom and most of the side wall of the trench shielding gate structure.
2. A SiC MOSFET device with a low specific on-resistance according to claim 1, characterized in that the doping concentration of the N-type semiconductor drift region (2) is greater than the doping concentration of the N-type semiconductor drift region (3).
3. The method of manufacturing a SiC MOSFET device having a low specific on-resistance according to claim 1, comprising the steps of:
selecting a SiC N + type substrate (1) and sequentially extending to obtain an N type semiconductor drift region (2), an N type semiconductor drift region (3) and a JFET region (4); forming a shielding gate trench; forming a P-type doped region (4); forming a shielding grid structure; forming a P well region (8); forming a polysilicon planar gate structure; forming an N-type heavily doped semiconductor source region (10); forming a P-type heavily doped semiconductor body contact region (9); forming a contact electrode.
4. The method of claim 3, wherein the shield gate trench with a sloped sidewall is formed by etching, and the P-type doped region (4) surrounding the bottom and most of the sidewall of the shield gate trench structure is directly formed by one or more ion implantations due to the sloped sidewall of the trench.
CN202210126895.8A 2022-02-11 2022-02-11 SiC MOSFET device with low specific on-resistance and preparation method thereof Pending CN114582975A (en)

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CN202210126895.8A CN114582975A (en) 2022-02-11 2022-02-11 SiC MOSFET device with low specific on-resistance and preparation method thereof

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