CN103247529B - A kind of trench field-effect device and preparation method thereof - Google Patents
A kind of trench field-effect device and preparation method thereof Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- QVGXLLKOCUKJST-NJFSPNSNSA-N oxygen-18 atom Chemical compound [18O] QVGXLLKOCUKJST-NJFSPNSNSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention discloses a kind of trench field-effect device and preparation method thereof, the method includes: provide substrate, and described substrate includes body layer and is positioned at the groove on described body layer surface；Sacrificial oxide layer is formed at described channel bottom and sidewall；Above the sacrificial oxide layer of described channel bottom, form heavy doping type polysilicon region, and remove the sacrificial oxide layer being positioned at the trenched side-wall above described heavy doping type polysilicon region；Forming gate dielectric layer at the channel bottom and sidewall with heavy doping type polysilicon region, the thickness of the gate dielectric layer being positioned at described heavy doping type polysilicon region is more than the thickness of the gate dielectric layer of described trenched side-wall.Utilize the trench field-effect device that the method makes, the thickness of the oxide layer that described channel bottom is formed is oxidated layer thickness 2-4 times formed at trenched side-wall, thus not only reduce the electric capacity between described trench field-effect device drain and grid, reduce the figure of merit of described trench field-effect device, and technique is simple.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of trench field-effect device and preparation method thereof.
Background technology
In a lot of power management applications, in order to put forward high-octane conversion efficiency, the operating frequency requiring its trench field-effect device (trenchMOSFET) is greater than 1MHz, this just requires that trench field-effect device (trenchMOSFET) has relatively low gate charge and less conducting resistance, therefore, constantly reduce the figure of merit (i.e. the product of trench field-effect device grids electric charge and conducting resistance) of trench field-effect device to have become people and continue to optimize the target that trench field-effect device is pursued.In prior art, people generally utilize and form the technology of heavy oxygen layer to reduce gate charge and the figure of merit of trench field-effect device at channel bottom.
In the prior art, the method forming groove thickness oxygen is a lot, such as partial thermal oxidation (LOCOS), high density plasma deposition (HDP) etc., also there is the lightly doped polysilicon of document utilization to form the heavy oxygen layer of channel bottom, but, find in actual production process, the figure of merit using the trench field-effect device that above-mentioned fabrication techniques goes out is higher, and processing technology is complex.
Summary of the invention
For solving above-mentioned technical problem, embodiments providing a kind of trench field-effect device and preparation method thereof, the method is simple, effective, and reduce further the figure of merit of described trench field-effect device.
For solving the problems referred to above, embodiments provide following technical scheme:
The manufacture method of a kind of trench field-effect device, the method includes: provide substrate, and described substrate includes body layer and is positioned at the groove on described body layer surface；Sacrificial oxide layer is formed at described channel bottom and sidewall；Above the sacrificial oxide layer of described channel bottom, form heavy doping type polysilicon region, and remove the sacrificial oxide layer being positioned at the trenched side-wall above described heavy doping type polysilicon region；Forming gate dielectric layer at the channel bottom and sidewall with heavy doping type polysilicon region, the thickness of the gate dielectric layer being positioned at described heavy doping type polysilicon region is more than the thickness of the gate dielectric layer of described trenched side-wall.
Preferably, the speed of growth of described channel bottom heavy doping type polysilicon region gate dielectric layer is more than the speed of growth of described trenched side-wall monocrystalline silicon region gate dielectric layer.
Preferably, the thickness of described heavily doped polysilicon region is
Preferably, the doping type of described heavily doped polysilicon region is N-type.
Preferably, the doping content of described heavily doped polysilicon region is more than 1e19cm-3。
Preferably, described have the channel bottom of heavy doping type polysilicon region and sidewall forms gate dielectric layer particularly as follows: in the environment of high pressure and wet oxygen, use thermal oxidation technology, forms gate dielectric layer at the channel bottom and sidewall with heavy doping type polysilicon region.
Preferably, the thickness of described sacrificial oxide layer existsIn the range of.
Preferably, described body layer includes: Semiconductor substrate；It is positioned at the epitaxial layer on described Semiconductor substrate table, in described epitaxial layer, there is well region；It is positioned at the dielectric barrier in described epi-layer surface.
Preferably, the thickness of described dielectric barrier existsIn the range of.
Present invention also offers a kind of trench field-effect device using said method to make.
Compared with prior art, technique scheme has the advantage that
In traditional groove power fieldtron manufacture method, the gate dielectric layer of channel bottom and trenched side-wall is simultaneously formed, but due to factors such as stress so that the gate dielectric layer thickness of channel bottom is slightly below the gate dielectric layer of trenched side-wall.And the manufacture method of the trench field-effect device that the embodiment of the present invention is provided, utilize heavily doped polysilicon at high temperature, feature faster than lightly doped monocrystalline silicon speed under wet oxygen environment, one layer of heavily doped polysilicon is deposited at channel bottom, owing to the oxidation rate of channel bottom polysilicon is fast more than the oxidation rate of trenched side-wall monocrystal silicon, so that the thickness in the oxide layer of channel bottom formation is oxidated layer thickness 2-4 times formed at trenched side-wall, and then reduce the electric capacity between described trench field-effect device drain and grid, reduce the figure of merit of described trench field-effect device, and technique is simple.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The profile of the trench field-effect device manufacture method that Fig. 1-6 is provided by the embodiment of the present invention；
The trench field-effect device architecture doping comparative simulation schematic diagram that Fig. 7 is provided by conventional groove fieldtron and the embodiment of the present invention；
Fig. 8 is the structural representation of traditional trench field-effect device；
The structural representation of the trench field-effect device that Fig. 9 is provided by the embodiment of the present invention；
Figure 10 is in the trench field-effect device that breakdown voltage is 65V, the curve synoptic diagram that the gate charge of the trench field-effect device that the embodiment of the present invention is provided and traditional trench field-effect device changes with grid voltage；
Figure 11 is in the trench field-effect device that breakdown voltage is 65V, the curve synoptic diagram that the figure of merit of the trench field-effect device that the embodiment of the present invention is provided and traditional trench field-effect device changes with grid voltage.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also use other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization in the case of intension of the present invention, and therefore the present invention is not limited by following public specific embodiment.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
The most as described in the background section, using the trench field-effect device that in prior art, the manufacture method of trench field-effect device makes, the figure of merit is higher, and processing technology is complex.Inventor studies discovery, although this is owing to the oxidation rate of lightly doped polysilicon is quicker than low-doped monocrystal silicon, but difference is the most little, and, generally in the oxide layer utilizing polysilicon oxidation also can form suitable thickness while channel bottom forms heavy oxygen layer on trenched side-wall.If and want formed ideal thickness gate dielectric layer, first the oxide layer on trenched side-wall must be etched away, regrowth gate dielectric layer, but owing to lightly doped polysilicon is little with the speed difference that trenched side-wall forms oxide layer at channel bottom, therefore, channel bottom oxide layer is little with the thickness of trenched side-wall oxide layer also difference, thus cause channel bottom oxide layer while the oxide layer of etching groove sidewall also can be etched away, the method finally making to utilize lightly doped polysilicon to form heavy oxygen layer at channel bottom, it is not largely effective, and technics comparing is complicated.
In view of this, the invention provides the manufacture method of a kind of trench field-effect device, the flow chart of the method as shown in figs 1 to 6, comprises the following steps:
Step 1: provide substrate, described substrate includes body layer and is positioned at the groove on described body layer surface.
As it is shown in figure 1, described body layer includes: Semiconductor substrate 101, the epitaxial layer 102 being positioned on described Semiconductor substrate table and be positioned at the dielectric barrier 103 on described epitaxial layer 102 surface.Wherein, there is well region 104, as shown in Figure 2 in described epitaxial layer 102.
It should be noted that, Semiconductor substrate in the present embodiment can include semiconductor element, such as monocrystalline, polycrystalline or the silicon of non crystalline structure or SiGe (SiGe), the semiconductor structure of mixing, such as carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or a combination thereof can also be included；Can also be silicon-on-insulator (SOI).Additionally, semiconductor base can also include other material, such as epitaxial layer 102 or the multiple structure of oxygen buried layer.Although there is described herein several examples of the material that can form substrate, but the spirit and scope of the present invention can be each fallen within as any material of semiconductor base.
Epitaxial layer 102 in the present embodiment can be to use the technique such as thermal oxide or the CVD N-type that once property is formed in described Semiconductor substrate 101 or p-type epitaxial layer 102, the technique such as thermal oxide or CVD can be used afterwards, one layer of dielectric barrier 103 is formed, as the barrier layer of subsequent ion injection process on described epitaxial layer 102 surface.The thickness of dielectric barrier 103 described in the embodiment of the present invention existsIn the range of, concrete thickness can determine according to the concrete application requirement of device.Semiconductor substrate 101 described in the present embodiment can be N+ silicon substrate, and epitaxial layer 102 is N-type epitaxial layer, described dielectric barrier 103 generally silicon oxide.
With dielectric barrier 103 as mask, use the technique such as ion implanting or energetic ion injection, in described epitaxial layer 102, inject dopant ion, to form well region 104, i.e. form N-type well region or P type trap zone.If doping type is N-type, dopant ion can be phosphorus or other pentads, if doping type is p-type, dopant ion can be boron or other trivalent element.In the embodiment of the present invention as a example by doping type is as p-type, the present embodiment can use high energy ion implanter carry out the injection of boron element, after high annealing, form P-well district 104.
After forming P-well district 104, spin coating photoresist layer on dielectric barrier 103, in order to ensure exposure accuracy, also anti-reflecting layer (not shown) can be formed between photoresist layer and dielectric barrier 103, to reduce unnecessary reflection；Use the mask plate with groove figure that photoresist layer is exposed afterwards, described photoresist layer surface is formed channel patterns, the photoresist layer with groove figure is obtained after development, with there is groove figure photoresist layer as mask, use the techniques such as reactive ion etching, dielectric barrier 103 is formed trench pattern openings, uses the methods such as Chemical cleaning to remove photoresist layer and anti-reflecting layer afterwards.Then with there is trench pattern openings dielectric barrier 103 as mask, use the method such as wet etching or dry etching, remove the material that do not covered by dielectric barrier 103, in described epitaxial layer 102 layers, form groove 105.
Step 2: as shown in Figure 4, forms sacrificial oxide layer 106 bottom described groove 105 and on sidewall.
After forming groove 105, can use thermal oxidation technology bottom described groove 105 and grow one layer of sacrificial oxide layer, i.e. sacrificial oxide layer 106 on sidewall, the thickness of sacrificial oxide layer 106 described in the embodiment of the present invention existsIn the range of, and described sacrificial oxide layer 106 covers the upper surface of described dielectric barrier 103.
Step 3: as it is shown in figure 5, form heavy doping type polysilicon region 107 above sacrificial oxide layer 106 bottom described groove 105, and remove the sacrificial oxide layer 106 being positioned at groove 105 sidewall above described heavy doping type polysilicon region 107.
After forming sacrificial oxide layer 106, the techniques such as CVD or PECVD (plasma enhanced CVD) can be used at described sacrificial oxide layer 106 surface deposition certain thickness original position heavily doped polysilicon, and utilize back carving technology to remove the original position heavily doped polysilicon on described dielectric barrier 103 surface and described groove 105 sidewall and sacrificial oxide layer, thus bottom described groove 105, form heavy doping type polysilicon region 107.
The thickness of the polysilicon region of heavy doping type described in the embodiment of the present invention 107 isThe doping type of described heavily doped polysilicon region is N-type, and accordingly, the doping content of described heavily doped polysilicon region is more than 1e19cm-3。
Step 4: as shown in Figure 6, forms gate dielectric layer with sidewall bottom the groove 105 with heavy doping type polysilicon region 107, and the thickness of the gate dielectric layer 108 being positioned at described heavy doping type polysilicon region is more than the thickness of the gate dielectric layer 109 of described trenched side-wall.
In the environment of high pressure and wet oxygen, the heavy doping type polysilicon region 107 that has using thermal oxidation technology to be pointed to bottom described groove 105 aoxidizes, the monocrystal silicon being simultaneously positioned at described groove 105 sidewall is the most oxidized, concurrently forms one layer of gate dielectric layer with sidewall bottom described groove 105.But, owing to being positioned at the oxidation rate of the heavy doping type polysilicon bottom described groove 105 much larger than the lightly doped monocrystal silicon being positioned at described groove 105 sidewall, therefore, the thickness 108 of the gate dielectric layer bottom described groove 105 is much larger than the thickness 109 of the gate dielectric layer of described groove 105 sidewall.
The trench field-effect device architecture doping comparative simulation schematic diagram provided by conventional groove fieldtron and the embodiment of the present invention with reference to Fig. 7, Fig. 7.As can be seen from Figure 7, the trench field-effect device that the embodiment of the present invention is provided, compared to traditional trench field-effect device, in trench field-effect device provided in the embodiment of the present invention, the thickness of channel bottom gate dielectric layer is 2-4 times of trenched side-wall gate dielectric layer thickness, and under the conditions of process similarity, in conventional groove fieldtron, the thickness of channel bottom gate dielectric layer is essentially identical with the thickness of trenched side-wall gate dielectric layer, therefore, under the conditions of in trench field-effect device provided in the embodiment of the present invention, the thickness of channel bottom gate dielectric layer is process similarity in conventional groove fieldtron 2-4 times of the thickness of channel bottom gate dielectric layer, thus reduce the electric capacity between described trench field-effect device drain and grid, reduce the figure of merit of this trench field-effect device, and technique is simple.
The embodiment of the invention also discloses a kind of trench field-effect device using said method to make, as shown in Figure 8, this trench field-effect device includes:
Body layer, described body layer includes: Semiconductor substrate 101, the epitaxial layer 102 being positioned on described Semiconductor substrate 101 table；
It is positioned at well region 104 and the groove 105 of described epitaxial layer 102, wherein, bottom described groove 105, there is heavily doped polysilicon region.
In addition, the trench field-effect device that the embodiment of the present invention is provided also includes through conventional trench field-effect device technology formation:
It is positioned at the polysilicon gate 110 of described groove 105；
It is positioned at the P+ electrode 111 of described P-type well region 104 and is positioned at N+ source electrode 112 between described P+ electrode 111 and described groove 105；
It is positioned at the metal source 113 on described P+ electrode 111 surface, and N+ source electrode 112 described in described metal source 113 covering part and be positioned at the oxide layer 114 in the middle of described metal source 113.
In conjunction with Fig. 8 and Fig. 9, wherein, Fig. 8 is the structural representation of traditional trench field-effect device, the structural representation of the trench field-effect device that Fig. 9 is provided by the embodiment of the present invention.Can be seen that from Fig. 8 and Fig. 9, trench field-effect device provided in the embodiment of the present invention, for traditional trench field-effect device, bottom described groove 105, there is thicker gate dielectric layer, thus reduce the electric capacity between described trench field-effect device grids and drain electrode, and then reduce the gate charge of described trench field-effect device, reduce the figure of merit of described trench field-effect device.
It is in the trench field-effect device that breakdown voltage is 65V with reference to Figure 10, Figure 10, the curve synoptic diagram that the gate charge of the trench field-effect device that the embodiment of the present invention is provided and traditional trench field-effect device changes with grid voltage.Wherein, curve 1 is the curve that the gate charge of the trench field-effect device provided in the embodiment of the present invention changes with grid voltage；Curve 2 is the curve that the gate charge of traditional trench field-effect device changes with grid voltage.From fig. 10 it can be seen that under Vgs=4.5V, for traditional trench field-effect device, the gate charge of the trench field-effect device that the embodiment of the present invention is provided decreases 20%.
It is in the trench field-effect device that breakdown voltage is 65V with reference to Figure 11, Figure 11, the curve synoptic diagram that the figure of merit of the trench field-effect device that the embodiment of the present invention is provided and traditional trench field-effect device changes with grid voltage.Wherein, curve 3 is the curve that the figure of merit (RQg) of traditional trench field-effect device changes with grid voltage；The curve that the figure of merit (RQg) of the trench field-effect device that curve 4 is provided by the embodiment of the present invention changes with grid voltage.It can be seen from figure 11 that under Vgs=4.5V, for traditional trench field-effect device, the figure of merit (RQg) of the trench field-effect device that the embodiment of the present invention is provided reduces 13%.
In this specification, various piece uses the mode gone forward one by one to describe, and the explanation of each some importance is the difference with other parts, and between various piece, identical similar portion sees mutually.
It should be noted that, in this article, the relational terms of such as first and second or the like is used merely to separate an entity or operation with another entity or operating space, and not necessarily requires or imply the relation or sequentially that there is any this reality between these entities or operation.And, term " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include those key elements, but also include other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that there is also other identical element in including the process of described key element, method, article or equipment.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.Multiple amendment to these embodiments will be apparent from for those skilled in the art, and generic principles defined herein can realize without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention is not intended to be limited to embodiment illustrated herein, and is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (9)
1. the manufacture method of a trench field-effect device, it is characterised in that the method includes:
Thering is provided substrate, described substrate includes body layer and is positioned at the groove on described body layer surface；
Sacrificial oxide layer is formed at described channel bottom and sidewall；
Above the sacrificial oxide layer of described channel bottom, form heavy doping type polysilicon region, and remove the sacrificial oxide layer being positioned at the trenched side-wall above described heavy doping type polysilicon region；Described heavy doping type polysilicon region is completely covered the sacrificial oxide layer being positioned at described channel bottom；
Forming gate dielectric layer at the channel bottom and sidewall with heavy doping type polysilicon region, the thickness of the gate dielectric layer being positioned at described heavy doping type polysilicon region is more than the thickness of the gate dielectric layer of described trenched side-wall；
Described body layer includes:
Semiconductor substrate；
It is positioned at the epitaxial layer on the surface of described Semiconductor substrate, in described epitaxial layer, there is well region；
It is positioned at the dielectric barrier in described epi-layer surface；Described dielectric barrier is used for forming well region.
Method the most according to claim 1, it is characterised in that the speed of growth of described channel bottom heavy doping type polysilicon region gate dielectric layer is more than the speed of growth of described trenched side-wall monocrystalline silicon region gate dielectric layer.
Method the most according to claim 1, it is characterised in that the thickness of described heavy doping type polysilicon region is
Method the most according to claim 1, it is characterised in that the doping type of described heavy doping type polysilicon region is N-type.
Method the most according to claim 1, it is characterised in that the doping content of described heavy doping type polysilicon region is more than 1e19cm-3。
Method the most according to claim 1, it is characterised in that described there is the channel bottom of heavy doping type polysilicon region and sidewall form gate dielectric layer particularly as follows:
In the environment of high pressure and wet oxygen, use thermal oxidation technology, form gate dielectric layer at the channel bottom and sidewall with heavy doping type polysilicon region.
Method the most according to claim 1, it is characterised in that the thickness of described sacrificial oxide layer existsIn the range of.
Method the most according to claim 7, it is characterised in that the thickness of described dielectric barrier existsIn the range of.
9. one kind uses the trench field-effect device that method described in any one of claim 1-8 makes.
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| CN201210030159.9A CN103247529B (en) | 2012-02-10 | 2012-02-10 | A kind of trench field-effect device and preparation method thereof |
| US14/376,021 US9601336B2 (en) | 2012-02-10 | 2012-07-18 | Trench field-effect device and method of fabricating same |
| PCT/CN2012/078793 WO2013117077A1 (en) | 2012-02-10 | 2012-07-18 | Trench field-effect transistor and preparation method therefor |
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| CN103762180A (en) * | 2014-01-09 | 2014-04-30 | 上海华虹宏力半导体制造有限公司 | Method for improving thickness of bottom oxide of groove-type MOS |
| CN104810268A (en) * | 2014-01-29 | 2015-07-29 | 北大方正集团有限公司 | Groove-type power device gate oxide layer preparation method |
| US9893176B2 (en) * | 2014-12-26 | 2018-02-13 | Fairchild Semiconductor Corporation | Silicon-carbide trench gate MOSFETs |
| JP6623772B2 (en) * | 2016-01-13 | 2019-12-25 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP6583151B2 (en) * | 2016-06-09 | 2019-10-02 | 株式会社デンソー | Manufacturing method of semiconductor device |
| CN110114156B (en) * | 2016-12-26 | 2021-03-23 | 联合材料公司 | Special-shaped diamond die |
| CN106684129A (en) * | 2017-01-12 | 2017-05-17 | 河北昂扬微电子科技有限公司 | Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT |
| US10522549B2 (en) * | 2018-02-17 | 2019-12-31 | Varian Semiconductor Equipment Associates, Inc. | Uniform gate dielectric for DRAM device |
| CN109585284A (en) * | 2018-11-27 | 2019-04-05 | 上海颛芯企业管理咨询合伙企业（有限合伙） | Semiconductor devices and forming method thereof |
| CN112864249A (en) * | 2021-01-11 | 2021-05-28 | 江苏东海半导体科技有限公司 | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof |
| CN113782444A (en) * | 2021-09-13 | 2021-12-10 | 济南市半导体元件实验所 | Manufacturing method of MOSFET device with thick oxygen trench at bottom |
| CN114530504B (en) * | 2022-02-14 | 2023-10-10 | 南京晟芯半导体有限公司 | High threshold voltage SiC MOSFET device and manufacturing method thereof |
| CN115513061A (en) * | 2022-11-22 | 2022-12-23 | 广东芯粤能半导体有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN116564806A (en) * | 2023-07-06 | 2023-08-08 | 捷捷微电(南通)科技有限公司 | Method for increasing thickness of oxide layer at bottom of trench |
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| CN103247529A (en) | 2013-08-14 |
| US9601336B2 (en) | 2017-03-21 |
| US20150214061A1 (en) | 2015-07-30 |
| WO2013117077A1 (en) | 2013-08-15 |
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