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CN103247529B - A trench-FET device and manufacturing method thereof - Google Patents

A trench-FET device and manufacturing method thereof Download PDF

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CN103247529B
CN103247529B CN 201210030159 CN201210030159A CN103247529B CN 103247529 B CN103247529 B CN 103247529B CN 201210030159 CN201210030159 CN 201210030159 CN 201210030159 A CN201210030159 A CN 201210030159A CN 103247529 B CN103247529 B CN 103247529B
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CN 201210030159
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CN103247529A (en )
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周宏伟
高东岳
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无锡华润上华半导体有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28229Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors

Abstract

本发明实施例公开了一种沟槽场效应器件及其制作方法,该方法包括:提供基底,所述基底包括本体层和位于所述本体层表面内的沟槽;在所述沟槽底部和侧壁形成牺牲氧化层;在所述沟槽底部的牺牲氧化层上方形成重掺杂型多晶硅区域,并去除位于所述重掺杂型多晶硅区域上方的沟槽侧壁的牺牲氧化层;在具有重掺杂型多晶硅区域的沟槽底部和侧壁形成栅介质层,位于所述重掺杂型多晶硅区域的栅介质层的厚度大于所述沟槽侧壁的栅介质层的厚度。 Embodiment of the present invention discloses a trench field effect device and a manufacturing method, the method comprising: providing a substrate, the substrate trench in the surface of the body comprises a body layer and a layer; and at the bottom of the trench forming a sacrificial sidewall oxide layer; forming a heavily doped polysilicon region over a sacrificial oxide layer at the bottom of the trench, and removing the sacrificial oxide layer located above type heavily doped polysilicon region of the trench sidewalls; having trench bottom and sidewalls of heavily doped polysilicon type region forming a gate dielectric layer on the heavily doped region type polysilicon gate dielectric layer thickness greater than the thickness of the trench sidewall gate dielectric layer. 利用该方法制作的沟槽场效应器件,所述沟槽底部形成的氧化层的厚度为在沟槽侧壁形成的氧化层厚度2-4倍,从而不仅减小了所述沟槽场效应器件漏极和栅极间的电容,降低了所述沟槽场效应器件的优值,而且工艺简单。 With this method of producing a trench field effect device, the groove bottom thickness of the oxide layer is formed of an oxide layer thickness of the sidewalls of the trench formed in 2-4 times, thus not only reducing the trench field effect device capacitance between the drain and gate, reducing the merit of the trench field effect device, and a simple process.

Description

-种沟槽场效应器件及其制作方法 - kind of trench field effect device and manufacturing method thereof

技术领域 FIELD

[0001] 本发明设及半导体制造技术领域,尤其设及一种沟槽场效应器件及其制作方法。 [0001] and provided the present invention of semiconductor manufacturing technology, and in particular is provided a trench-FET device and a manufacturing method thereof.

背景技术 Background technique

[0002] 在很多电源管理应用中,为了提高能量的转换效率,要求其沟槽场效应器件(trench M0S阳T)的工作频率要大于IMHz,运就要求沟槽场效应器件(trench M0SFET)具有较低的栅极电荷W及较小的导通电阻,因此,不断降低沟槽场效应器件的优值(即沟槽场效应器件栅极电荷与导通电阻的乘积)已成为人们不断优化沟槽场效应器件所追求的目标。 [0002] In many applications, power management, in order to improve the energy conversion efficiency, which requires a trench field effect device (trench M0S male T) is greater than the operating frequency of 1 MHz, it would require transport trench field effect device (trench M0SFET) having W low gate charge and smaller on-resistance, therefore, continue to decrease merit trench field effect device (i.e., the product of the trench gate field effect device and the on-resistance of the charge) has become a continuous optimization groove the pursuit of the goal trough field effect device. 现有技术中,人们通常利用在沟槽底部形成厚氧层的技术来降低沟槽场效应器件的栅极电荷和优值。 In the prior art, people often use a technique for forming a thick oxide layer at the bottom of the trench to reduce gate charge and merit trench field effect device.

[0003] 在现有技术中,形成沟槽厚氧的方法很多,例如局部热氧化化0C0S),高密度等离子淀积化DP)等,也有文献利用轻渗杂的多晶娃来形成沟槽底部的厚氧层,但是,在实际生产过程中发现,采用上述技术制作出的沟槽场效应器件的优值较高,而且制作工艺较为复杂。 Method [0003] In the prior art, a trench is formed in a thickness of a lot of oxygen, such as local thermal oxidation of 0C0S), high density plasma deposition of DP), also literature using light dope polycrystalline baby trenches formed a thick oxide layer at the bottom, however, found in the actual production process, the higher the value of the above-described techniques preferably produce a trench field effect device, and more complicated production process.

发明内容 SUMMARY

[0004] 为解决上述技术问题,本发明实施例提供了一种沟槽场效应器件及其制作方法, 该方法简单、有效,而且进一步降低了所述沟槽场效应器件的优值。 [0004] To solve the above problems, embodiments provide a trench field effect device and a manufacturing method of the present invention, the method is simple, effective, and further reducing the merit of the trench field effect device.

[0005] 为解决上述问题,本发明实施例提供了如下技术方案: [0005] In order to solve the above problems, the present invention provides the following technical solutions:

[0006] -种沟槽场效应器件的制作方法,该方法包括:提供基底,所述基底包括本体层和位于所述本体层表面内的沟槽;在所述沟槽底部和侧壁形成牺牲氧化层;在所述沟槽底部的牺牲氧化层上方形成重渗杂型多晶娃区域,并去除位于所述重渗杂型多晶娃区域上方的沟槽侧壁的牺牲氧化层;在具有重渗杂型多晶娃区域的沟槽底部和侧壁形成栅介质层,位于所述重渗杂型多晶娃区域的栅介质层的厚度大于所述沟槽侧壁的栅介质层的厚度。 [0006] - seed trench field effect device fabrication method, the method comprising: providing a substrate, the substrate trench in the surface of the body comprises a body layer and a layer; forming a sacrificial bottom and sidewalls of the trench oxide layer; forming a heavily doped at polymorph baby area above the sacrificial oxide layer at the bottom of the trench, and removing the sacrificial oxide layer is doped at a weight Wa type polycrystalline region above the trench sidewalls; having heavy dope trench sidewalls and bottom baby polycrystalline region forming a gate dielectric layer on the gate dielectric layer heteroaryl heavy infiltration thickness of the gate dielectric layer-type polycrystalline baby region is greater than the thickness of the sidewalls of the trench .

[0007] 优选的,所述沟槽底部重渗杂型多晶娃区域栅介质层的生长速度大于所述沟槽侧壁单晶娃区域栅介质层的生长速度。 [0007] Preferably, the bottom of the trench-type doped at a weight growth rate of polycrystalline region baby gate dielectric layer is greater than the growth rate of the monocrystalline baby trench sidewall gate dielectric layer region.

[000引优选的,所述重渗杂的多晶娃区域的厚度为400A-5000 A。 [000 Preferably the thickness of the lead, the heavy dope baby polycrystalline region is 400A-5000 A.

[0009] 优选的,所述重渗杂的多晶娃区域的渗杂类型为N型。 [0009] Preferably, the weight of the dope type polycrystalline baby dope N-type region.

[0010] 优选的,所述重渗杂的多晶娃区域的渗杂浓度大于lel9cnf3。 [0010] Preferably, the concentration of impurity doped at a weight baby polycrystalline region is greater than lel9cnf3.

[0011] 优选的,所述在具有重渗杂型多晶娃区域的沟槽底部和侧壁形成栅介质层具体为:在高压和湿氧的环境下,采用热氧化工艺,在具有重渗杂型多晶娃区域的沟槽底部和侧壁形成栅介质层。 [0011] Preferably, the dope having a weight trench bottom and sidewalls of the polycrystalline region baby gate dielectric layer is formed specifically as follows: wet and oxygen under high pressure environment, using a thermal oxidation process, having a weight in the retentate heteroaryl trench bottom and sidewalls of polymorph baby gate dielectric layer formation region.

[001^ 优选的,所述牺牲氧化层的厚度在400A-2000 A的范围内。 [001 ^ Preferably, the thickness of the sacrificial oxide layer is in the range of 400A-2000 A.

[0013] 优选的,所述本体层包括:半导体衬底;位于所述半导体衬底表上的外延层,所述外延层内具有阱区;位于所述外延层表面上的介质阻挡层。 [0013] Preferably, the bulk layer comprising: a semiconductor substrate; in the epitaxial layer on the semiconductor substrate table, said epitaxial layer having a well region; a dielectric barrier layer on the surface of the epitaxial layer.

[0014] 优选的,所述介质阻挡层的厚度在400A-1000 A的范围内。 [0014] Preferably, the dielectric thickness of the barrier layer is in the range of 400A-1000 A.

[0015] 本发明还提供了一种采用上述方法制作的沟槽场效应器件。 [0015] The present invention further provides a trench field effect device which is prepared by the above method.

[0016] 与现有技术相比,上述技术方案具有W下优点: [0016] Compared with the prior art, the above solution has the following advantages W:

[0017] 传统的沟槽功率场效应器件制作方法中,沟槽底部和沟槽侧壁的栅介质层是同时形成的,但是由于应力等因素,使得沟槽底部的栅介质层厚度略低于沟槽侧壁的栅介质层。 [0017] The conventional trench power MOSFET device fabrication method, the trench bottom and trench sidewall gate dielectric layer are formed simultaneously, but due to stress and other factors, so that the thickness of the gate dielectric layer slightly below the bottom of the trench gate dielectric layer of the trench sidewalls. 而本发明实施例所提供的沟槽场效应器件的制作方法,利用重渗杂多晶娃在高溫、湿氧环境下比轻渗杂的单晶娃氧化速率快的特点,在沟槽底部淀积一层重渗杂的多晶娃,由于沟槽底部多晶娃的氧化速率远比沟槽侧壁单晶娃的氧化速率快,从而使得在沟槽底部形成的氧化层的厚度为在沟槽侧壁形成的氧化层厚度2-4倍,进而减小了所述沟槽场效应器件漏极和栅极间的电容,降低了所述沟槽场效应器件的优值,而且工艺简单。 Making a trench field effect device according to the present embodiment provided by the invention, a weight-dope the polycrystalline baby fast at high temperature, wet oxygen atmosphere than light dope oxide single crystal baby rate characteristics, at the bottom of the trench lake product layer of heavily dope the polycrystalline baby, due to rapid oxidation rate of polycrystalline oxidation rate of the trench bottom than the trench sidewalls crystal baby doll, so that the thickness of the oxide layer at the bottom of the trench is formed in the groove the thickness of the sidewall oxide layer formed in the groove 2-4 times, thereby reducing the capacitance between the drain and the gate trench field effect device, reducing the merit of the trench field effect device, and a simple process.

附图说明 BRIEF DESCRIPTION

[0018] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可W 根据运些附图获得其他的附图。 [0018] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments the drawings are only some embodiments of the present invention, those of ordinary skill in the art is concerned, without any creative effort, these may be transported in accordance with W drawings other drawings.

[0019] 图1-6为本发明实施例所提供的沟槽场效应器件制作方法的剖面图; [0019] Figures 1-6 a sectional view of a trench field effect device manufacturing method according to embodiments of the present invention is provided;

[0020] 图7为传统沟槽场效应器件与本发明实施例所提供的沟槽场效应器件结构渗杂对比模拟示意图; [0020] FIG. 7 is a configuration example of a trench field effect device is provided with a conventional trench field effect device according to the present invention contrast simulation schematic dope;

[0021 ]图8为传统的沟槽场效应器件的结构示意图; [0021] FIG. 8 is a schematic view of a conventional trench field effect device;

[0022] 图9为本发明实施例所提供的沟槽场效应器件的结构示意图; [0022] FIG. 9 is a schematic structure of a trench field effect device according to the embodiment of the present invention is provided;

[0023] 图10为在击穿电压为65V的沟槽场效应器件中,本发明实施例所提供的沟槽场效应器件与传统的沟槽场效应器件的栅极电荷随栅极电压变化的曲线示意图; [0023] FIG. 10 is a breakdown voltage of 65V trench field effect device, the embodiment of the present invention, a trench field effect device embodiment is provided with the conventional trench gate charge FET device with a gate voltage change curve a schematic view;

[0024] 图11为在击穿电压为65V的沟槽场效应器件中,本发明实施例所提供的沟槽场效应器件与传统的沟槽场效应器件的优值随栅极电压变化的曲线示意图。 [0024] FIG. 11 is a merit trench field effect device breakdown voltage of 65V, a trench field effect device embodiment is provided with conventional trench field effect device embodiment of the present invention with a gate voltage change curve FIG.

具体实施方式 detailed description

[0025] 下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明一部分实施例,而不是全部的实施例。 [0025] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0026] 在下面的描述中阐述了很多具体细节W便于充分理解本发明,但是本发明还可W 采用其他不同于在此描述的其它方式来实施,本领域技术人员可W在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施例的限制。 [0026] forth in the following description, numerous specific details are W facilitating full understanding of the present invention, but the present invention may also employ other W otherwise be different from the embodiments described herein, those skilled in the art may be made without departing the present invention W promotion do similar connotation case, therefore invention is not limited to the specific embodiments disclosed below.

[0027] 其次,本发明结合示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。 [0027] Next, the present invention is described in detail in conjunction with a schematic view, while embodiments of the invention described in detail, for ease of illustration, a sectional view showing a configuration of the device will be enlarged usual scale, and the diagram is merely an example, which is herein It should not limit the scope of the present invention. 此外,在实际制作中应包含长度、宽度及深度的Ξ维空间尺寸。 Further, the production should be included in the actual dimension Ξ spatial dimensions length, width and depth.

[0028] 正如背景技术部分所述,采用现有技术中沟槽场效应器件的制作方法制作的沟槽场效应器件,优值较高,而且制作工艺较为复杂。 [0028] As described in the background, using the prior art method for fabricating a trench field effect device fabricated trench field effect device, preferably a high value, and the production process is relatively complex. 发明人研究发现,运是由于轻渗杂的多晶娃的氧化速率虽然比低渗杂的单晶娃快一点,但差别并不大,而且,通常在利用多晶娃氧化在沟槽底部形成厚氧层的同时沟槽侧壁上也会形成相当厚度的氧化层。 The inventors have found that, due to the oxidation rate of the light transport dope polycrystalline Wa although faster than single crystal hypotonic heteroaryl baby, but the difference is not large, and, usually formed from polycrystalline oxide baby at the bottom of the trench thick oxide layer while also forming an oxide layer on the trench sidewalls considerable thickness. 而若想形成理想厚度的栅介质层,必须先将沟槽侧壁上的氧化层刻蚀掉,再生长栅介质层,但是由于轻渗杂的多晶娃在沟槽底部与沟槽侧壁形成氧化层的速率差别不大,因此,沟槽底部氧化层与沟槽侧壁氧化层的厚度也差别不大,从而导致在刻蚀沟槽侧壁的氧化层的同时沟槽底部氧化层也会被刻蚀掉,最终使得利用轻渗杂的多晶娃在沟槽底部形成厚氧层的方法,并不是十分有效,而且工艺比较复杂。 To form the desired thickness of the gate dielectric layer must be etched away first oxide layer on the trench sidewalls, the regrown gate dielectric layer, but since the light dope polymorph baby trench bottom and trench sidewalls in the rate of formation of oxide layer is not very different, and therefore, the thickness of the bottom of the trench oxide layer and the trench sidewall oxide is also not very different, while resulting in a bottom of the trench oxide sidewall oxide layer in the trench etching also It is etched away so that the final thickness of oxide layer using the method of the light dope polycrystalline baby is formed in the bottom of the trench, not very effective, and the process is more complicated.

[0029] 有鉴于此,本发明提供了一种沟槽场效应器件的制作方法,该方法的流程图如图1-图6所示,包括W下步骤: [0029] Accordingly, the present invention provides a method for manufacturing a trench field effect device, shown in the flowchart of the method in FIG. 1 to FIG. 6, W comprises the steps of:

[0030] 步骤1:提供基底,所述基底包括本体层和位于所述本体层表面内的沟槽。 [0030] Step 1: providing a substrate, said substrate comprising a trench in the surface of the body layer and a body layer.

[0031] 如图1所示,所述本体层包括:半导体衬底101、位于所述半导体衬底表上的外延层102W及位于所述外延层102表面上的介质阻挡层103。 [0031] 1, the bulk layer comprising: a semiconductor substrate 101, located on the surface of the epitaxial layer medium 102W on the semiconductor substrate table and the barrier layer 102 in the epitaxial layer 103. 其中,所述外延层102内具有阱区104,如图2所示。 Wherein, in said epitaxial layer region 102 having a well 104, as shown in FIG.

[0032] 需要说明的是,本实施例中的半导体衬底可W包括半导体元素,例如单晶、多晶或非晶结构的娃或娃错(SiGe),也可W包括混合的半导体结构,例如碳化娃、錬化铜、蹄化铅、 神化铜、憐化铜、神化嫁或錬化嫁、合金半导体或其组合;也可W是绝缘体上娃(SOI)。 [0032] Incidentally, in the present embodiment the semiconductor substrate W embodiment may include a semiconductor element, for example monocrystalline, polycrystalline or amorphous structure or a baby doll wrong (SiGe), W may also comprise a mixed semiconductor structure, For example baby carbide, copper and chain, hoof of lead, copper deified, copper pity, and chain of deification married or married, alloy semiconductor, or combinations thereof; W is also baby insulator (SOI). 此外, 半导体基底还可W包括其它的材料,例如外延层102或埋氧层的多层结构。 Further, the semiconductor substrate W may further comprise other materials, for example, a multilayer structure of the epitaxial layer 102 or buried oxide layer. 虽然在此描述了可W形成基底的材料的几个示例,但是可W作为半导体基底的任何材料均落入本发明的精神和范围。 Although several examples of materials forming the substrate W may be described herein, but any material may be used as a semiconductor substrate W fall within the spirit and scope of the invention.

[0033] 本实施例中的外延层102可为采用热氧化或CVD等工艺在所述半导体衬底101上一次性形成的N型或P型外延层102,之后可采用热氧化或CVD等工艺,在所述外延层102表面形成一层介质阻挡层103,作为后续离子注入过程的阻挡层。 [0033] N-type or P-type epitaxial layer, the epitaxial layer 102 in the embodiment may be employed other disposable thermal oxidation or CVD process is formed on the semiconductor substrate 101 in this embodiment 102, after the thermal oxidation or CVD may be employed other processes forming a dielectric layer on a surface of the epitaxial layer 103, barrier 102, the barrier layer as the subsequent ion implantation process. 本发明实施例中所述介质阻挡层103的厚度在400A-1000 A的范围内,具体厚度可按照器件的具体应用要求确定。 The thickness of the dielectric barrier layer embodiment 103 of the present embodiment of the invention is in the range of 400A-1000 A, specifically, the thickness may be determined according to the specific application requirements of the device. 本实施例中所述的半导体衬底101可为N+娃衬底,外延层102为N-型外延层,所述介质阻挡层103- 般为氧化娃。 The semiconductor substrate 101 described in the embodiment may be a baby N + substrate, the epitaxial layer is N- type epitaxial layer 102, the dielectric barrier layer 103- like baby oxide.

[0034] W介质阻挡层103为掩膜,采用离子注入或高能离子注入等工艺,在所述外延层102内注入渗杂离子,W形成阱区104,即形成N型阱区或P型阱区。 [0034] W dielectric barrier layer 103 as a mask, ion implantation or high-energy ion implantation process, ion implantation tainted within the epitaxial layer 102, W-well region 104 is formed, i.e. an N-type well or a P-type well region Area. 若渗杂类型为N型,渗杂离子可为憐或其他五价元素,若渗杂类型为P型,渗杂离子可为棚或其他Ξ价元素。 If the type is N type dope, dope may be a pity ions or pentavalent element other, if the type is P type dope, dope ions may be monovalent Ξ shed or other elements. 本发明实施例中W渗杂类型为P型为例,本实施例中可采用高能量离子注入机进行棚元素的注入,经高溫退火后形成P-阱区104。 W embodiment of the present invention type is P type doped at an example, this embodiment may employ a high-energy ion implantation machine shed injection elements present embodiment, the P- well region 104 is formed by high-temperature annealing.

[0035] 形成P-阱区104之后,在介质阻挡层103上旋涂光刻胶层,为了保证曝光精度,还可在光刻胶层和介质阻挡层103之间形成抗反射层(图中未示出),W减少不必要的反射;之后采用具有沟槽图形的掩膜版对光刻胶层进行曝光,在所述光刻胶层表面上形成沟槽图案, 显影之后得到具有沟槽图形的光刻胶层,W具有沟槽图形的光刻胶层为掩膜,采用反应离子刻蚀等工艺,在介质阻挡层103上形成沟槽图形开口,之后采用化学清洗等方法去除光刻胶层和抗反射层。 After [0035] P- well region 104 is formed on the dielectric barrier layer spin coating a photoresist layer 103, in order to ensure the accuracy of the exposure, the photoresist layer may be formed between the barrier layer and the dielectric antireflection layer 103 (FIG. not shown), W reduce unwanted reflections; obtained after using the mask after having a groove pattern on the photoresist layer exposed to form a groove pattern on the surface of the photoresist layer is developed with a trench the patterned photoresist layer, W layer having a trench pattern in the photoresist as a mask, reactive ion etching process, an opening is formed in the trench pattern on the dielectric barrier layer 103, after the chemical cleaning method for removing a photolithographic subbing layer and antireflection layer. 然后W具有沟槽图形开口的介质阻挡层103为掩膜,采用湿法腐蚀或干法刻蚀等方法,去除未被介质阻挡层103覆盖的材料,在所述外延层102层内形成沟槽105。 W barrier layer having a dielectric and a trench opening pattern 103 as a mask, wet etching or dry etching or the like, to remove material not covered by the dielectric barrier layer 103, a trench is formed within the epitaxial layer 102 layer 105.

[0036] 步骤2:如图4所示,在所述沟槽105底部和侧壁上形成牺牲氧化层106。 [0036] Step 2: 4, the sacrificial oxide layer 106 is formed on the trench bottom and sidewalls 105.

[0037] 形成沟槽105之后,可采用热氧化工艺在所述沟槽105底部和侧壁上生长一层牺牲氧化层,即牺牲氧化层106,本发明实施例中所述牺牲氧化层106的厚度在400A-2000 A 的范围内,且所述牺牲氧化层106覆盖所述介质阻挡层103的上表面。 After [0037] forming trenches 105, a thermal oxidation process can be grown on the trench bottom and sidewalls 105 one sacrificial oxide layer, i.e., sacrificial oxide layer 106, embodiments of the present invention the sacrificial oxide layer 106 a thickness in the range of 400A-2000 a, and the sacrificial oxide layer 106 covers the upper surface of the dielectric layer 103 of the barrier.

[0038] 步骤3:如图5所示,在所述沟槽105底部的牺牲氧化层106上方形成重渗杂型多晶娃区域107,并去除位于所述重渗杂型多晶娃区域107上方的沟槽105侧壁的牺牲氧化层106。 [0038] Step 3: As shown, the formation of heavy polymorph baby dope region 107 over the sacrificial oxide layer 105 at the bottom of the trench 1065, and removing portions of said doped at a weight Wa region 107 polymorph trench 105 sidewall 106 above the sacrificial oxide layer.

[0039] 形成牺牲氧化层106之后,可采用CVD或PECVD(等离子体增强化学气相淀积)等工艺在所述牺牲氧化层106表面淀积一定厚度的原位重渗杂多晶娃,并利用回刻工艺去除所述介质阻挡层103表面W及所述沟槽105侧壁上的原位重渗杂多晶娃和牺牲氧化层,从而在所述沟槽105底部形成重渗杂型多晶娃区域107。 After the [0039] sacrificial oxide layer 106 is formed, can be CVD or PECVD (plasma enhanced chemical vapor deposition) process and the like in place of the sacrificial oxide layer 106 is deposited a surface of a certain thickness dope polycrystalline weight baby, and using removing the etch-back process in situ on the surface of 103 W of the dielectric barrier layer 105 and the trench sidewalls dope the polycrystalline weight Wa and the sacrificial oxide layer to form the bottom of the trench 105 polymorph heavy dope Wa region 107.

[0040] 本发明实施例中所述重渗杂型多晶娃区域107的厚度为400A-5000 A,所述重渗杂的多晶娃区域的渗杂类型为N型,相应的,所述重渗杂的多晶娃区域的渗杂浓度大于lel9cm_3。 [0040] The embodiments of the present invention the weight Wa polymorph dope region 107 to a thickness of 400A-5000 A, a type of the re-dope dope baby polycrystalline N-type region, corresponding to the weight concentration of impurity dope baby polycrystalline region is greater than lel9cm_3.

[0041] 步骤4:如图6所示,在具有重渗杂型多晶娃区域107的沟槽105底部和侧壁形成栅介质层,位于所述重渗杂型多晶娃区域的栅介质层108的厚度大于所述沟槽侧壁的栅介质层109的厚度。 [0041] Step 4: 6, having a weight in the dope trench sidewalls 105 and bottom region 107 of the polycrystalline doll forming a gate dielectric layer on the doped at a weight polymorph baby gate dielectric region layer thickness 108 is greater than the trench sidewall gate dielectric layer 109.

[0042] 在高压和湿氧的环境下,采用热氧化工艺对位于所述沟槽105底部的具有重渗杂型多晶娃区域107进行氧化,同时位于所述沟槽105侧壁的单晶娃也被氧化,在所述沟槽105 底部和侧壁同时形成一层栅介质层。 [0042] Wet and oxygen under high pressure environment, using a thermal oxidation process is in the bottom of the trench 105 having a weight of polymorph baby dope region 107 is oxidized, while the single crystal is located in said trench sidewalls 105 baby also oxidized, forming a layer of gate dielectric layer 105 while the bottom and sidewalls of the trench. 但是,由于位于所述沟槽105底部的重渗杂型多晶娃的氧化速度远大于位于所述沟槽105侧壁的轻渗杂的单晶娃,因此,所述沟槽105底部的栅介质层的厚度108远大于所述沟槽105侧壁的栅介质层的厚度109。 However, since the weight positioned dope type polycrystalline oxidation rate of the baby is much larger than the bottom of trench 105 located sidewalls 105 of the trench baby crystal light dope, and therefore, the bottom portion 105 of the gate trench the thickness of the dielectric layer 108 is much greater than the thickness of the gate dielectric layer 109 of the trench 105 sidewalls.

[0043] 参考图7,图7为传统沟槽场效应器件与本发明实施例所提供的沟槽场效应器件结构渗杂对比模拟示意图。 [0043] Referring to FIG 7, FIG 7 is a configuration example of a trench field effect device is provided with a conventional trench field effect device according to the present invention dope Simulations of FIG. 从图7可W看出,本发明实施例所提供的沟槽场效应器件,相较于传统的沟槽场效应器件,本发明实施例中所提供的沟槽场效应器件中沟槽底部栅介质层的厚度为沟槽侧壁栅介质层厚度的2-4倍,而相似工艺条件下,传统沟槽场效应器件中沟槽底部栅介质层的厚度与沟槽侧壁栅介质层的厚度基本相同,因此,本发明实施例中所提供的沟槽场效应器件中沟槽底部栅介质层的厚度为相似工艺条件下传统沟槽场效应器件中沟槽底部栅介质层的厚度的2-4倍,从而减小了所述沟槽场效应器件漏极和栅极间的电容,降低了该沟槽场效应器件的优值,而且工艺简单。 W can be seen from Figure 7, a trench field effect device according to the embodiment of the present invention is provided, as compared to conventional trench field effect device, a trench field effect device in the bottom of the groove provided in the embodiment of the present invention, the gate thickness of the dielectric layer is 2-4 times the trench sidewalls of the gate dielectric layer thickness, and the thickness under similar conditions, the conventional trench field effect device and the thickness of the gate dielectric layer sidewall of the trench bottom of the trench gate dielectric layer substantially the same, therefore, the thickness of a conventional trench field effect device under similar process conditions in the bottom of the trench gate dielectric layer thickness of 2 trench field effect device in the bottom of the groove provided in the gate dielectric layer of the embodiment of the present invention 4 times, thus reducing the capacitance between the drain and the gate trench field effect device, reducing the merit of the trench field effect device, and a simple process.

[0044] 本发明实施例还公开了一种采用上述方法制作的沟槽场效应器件,如图8所示,该沟槽场效应器件包括: [0044] Example embodiments of the present invention also discloses a trench field effect device which is prepared by the above method, as shown in Figure 8, the trench field effect device comprising:

[0045] 本体层,所述本体层包括:半导体衬底101、位于所述半导体衬底101表上的外延层102; [0045] The bulk layer, said bulk layer comprises: a semiconductor substrate 101, an epitaxial layer 102 on the semiconductor substrate table 101;

[0046] 位于所述外延层102内的阱区104和沟槽105,其中,所述沟槽105底部具有重渗杂的多晶娃区域。 [0046] in the well region 104 and the epitaxial layer 102 within the trenches 105, wherein the trench bottom region 105 having a polycrystalline baby weight of dope.

[0047] 除此之外,本发明实施例所提供的沟槽场效应器件还包括经常规沟槽场效应器件工艺形成的: [0047] In addition, embodiments of the present invention, a trench field effect device comprises a further embodiment is provided by forming a conventional trench field effect device technology:

[004引位于所述沟槽105内的多晶娃栅极110; [004 primer located within the groove 105 baby polycrystalline gate electrode 110;

[0049] 位于所述P-型阱区104内的P+电极111W及位于所述P+电极111与所述沟槽105间N +源极112; [0049] positioned electrodes 111W and the P + P + electrode 111 positioned in the groove 105 and the N + source 112 in the P- well region 104;

[0050] 位于所述P+电极111表面的金属源极113,且所述金属源极113覆盖部分所述N+源极112W及位于所述金属源极113中间的氧化层114。 [0050] positioned in the P + surface of the metal electrode 111 of the source 113, the source electrode 113 and the metal covering said portion of the N + source and 112W metal oxide layer on the source electrode 113 of the intermediate 114.

[0051] 结合图8和图9,其中,图8为传统的沟槽场效应器件的结构示意图,图9为本发明实施例所提供的沟槽场效应器件的结构示意图。 [0051] Figures 8 and 9 in combination, wherein Figure 8 is a schematic view of a conventional trench field effect device, a schematic structure of a trench field effect device according to the invention is provided in FIG. 9 of the present embodiment. 从图8和图9中可W看出,本发明实施例中所提供的沟槽场效应器件,相较于传统的沟槽场效应器件而言,所述沟槽105底部具有较厚的栅介质层,从而减小了所述沟槽场效应器件栅极和漏极间的电容,进而减小了所述沟槽场效应器件的栅极电荷,降低了所述沟槽场效应器件的优值。 W can be seen from FIG. 8 and FIG. 9, a trench field effect device in the embodiment of the present invention is provided, compared to the traditional trench field effect device, the groove bottom portion 105 has a thicker gate dielectric layer, thereby reducing the capacitance between the gate and drain trench field effect device, thereby reducing the charge of the trench gate field effect device, preferably the reduction of the trench field effect device value.

[0052] 参考图10,图10为在击穿电压为65V的沟槽场效应器件中,本发明实施例所提供的沟槽场效应器件与传统的沟槽场效应器件的栅极电荷随栅极电压变化的曲线示意图。 [0052] Referring to FIG 10, FIG 10 is a breakdown voltage of the gate charge 65V trench field effect device, a trench field effect device embodiment is provided with conventional trench field effect device embodiment of the present invention with the gate voltage curve changes FIG. 其中,曲线1为本发明实施例中所提供的沟槽场效应器件的栅极电荷随栅极电压变化的曲线; 曲线2为传统的沟槽场效应器件的栅极电荷随栅极电压变化的曲线。 Wherein the gate charge curve 1 profile of trench field effect device provided in the embodiment with change in gate voltage of the embodiment of the present invention; curve 2 is a conventional trench gate charge FET device with a gate voltage change curve. 从图10可W看出,在Vgs = 4.5V下,相较于传统的沟槽场效应器件而言,本发明实施例所提供的沟槽场效应器件的栅极电荷减少了20%。 W can be seen from FIG. 10, at Vgs = 4.5V, compared to the traditional trench field effect device, the gate charge trench field effect device according to an embodiment of the present invention provided a 20% reduction.

[0053] 参考图11,图11为在击穿电压为65V的沟槽场效应器件中,本发明实施例所提供的沟槽场效应器件与传统的沟槽场效应器件的优值随栅极电压变化的曲线示意图。 [0053] Referring to FIG 11, FIG 11 is a figure of merit with a gate breakdown voltage of 65V in a trench field effect device, a trench field effect device embodiment is provided with conventional trench field effect device embodiment of the present invention. voltage change curve of FIG. 其中,曲线3为传统的沟槽场效应器件的优值(RQg)随栅极电压变化的曲线;曲线4为本发明实施例所提供的沟槽场效应器件的优值(RQg)随栅极电压变化的曲线。 Wherein, curve 3 is the merit conventional trench field effect device (RQG) with a gate voltage change curve; curve 4 merit embodiment trench field effect device is provided (RQG) embodiment of the present invention with a gate voltage change curve. 从图11可W看出,在Vgs = 4.5V下,相较于传统的沟槽场效应器件而言,本发明实施例所提供的沟槽场效应器件的优值(RQg)降低了13%。 W can be seen from FIG. 11, at Vgs = 4.5V, compared to the traditional trench field effect device, preferably the value 13% lower trench field effect device according to the provided (RQG) embodiment of the present invention, .

[0054] 本说明书中各个部分采用递进的方式描述,每个部分重点说明的都是与其他部分的不同之处,各个部分之间相同相似部分互相参见即可。 [0054] The various portions of the present specification describes a progressive manner, each section highlights are different from other portions of the same or similar portions between respective portions refer to the other.

[0055] 需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示运些实体或操作之间存在任何运种实际的关系或者顺序。 [0055] Incidentally, herein, relational terms such as first and second and the like are only used to distinguish one entity or operation from another entity or action without necessarily requiring or implying some transport the presence of any species transported actual relationship or order between entities or operations. 而且,术语"包括"、"包含"或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为运种过程、方法、物品或者设备所固有的要素。 Further, the term "comprising", "containing" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, article, or apparatus not include only those elements but not expressly listed further comprising the other elements, or further comprising op species process, method, article, or apparatus inherent elements. 在没有更多限制的情况下,由语句"包括一个......"限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。 Without more constraints, by the wording "include a ......" defined does not exclude the existence of additional identical elements in the element comprising a process, method, article, or apparatus.

[0056] 对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。 [0056] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. 对运些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可W在不脱离本发明的精神或范围的情况下,在其它实施例中实现。 These various modifications op professional skill in the art of the present embodiment will be apparent, and the generic principles defined herein may be W without departing from the spirit or scope of the present invention, be implemented in other embodiments . 因此,本发明将不会被限制于本文所示的实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。 Accordingly, the present invention will not be limited to the embodiments shown herein but is to be accorded herein consistent with the principles and novel features disclosed widest scope.

Claims (9)

  1. 1. 一种沟槽场效应器件的制作方法,其特征在于,该方法包括: 提供基底,所述基底包括本体层和位于所述本体层表面内的沟槽; 在所述沟槽底部和侧壁形成牺牲氧化层; 在所述沟槽底部的牺牲氧化层上方形成重掺杂型多晶硅区域,并去除位于所述重掺杂型多晶硅区域上方的沟槽侧壁的牺牲氧化层;所述重掺杂型多晶硅区域完全覆盖位于所述沟槽底部的牺牲氧化层; 在具有重掺杂型多晶硅区域的沟槽底部和侧壁形成栅介质层,位于所述重掺杂型多晶硅区域的栅介质层的厚度大于所述沟槽侧壁的栅介质层的厚度; 所述本体层包括: 半导体衬底; 位于所述半导体衬底的表面上的外延层,所述外延层内具有阱区; 位于所述外延层表面上的介质阻挡层;所述介质阻挡层用于形成阱区。 1. A method of making a trench field effect device, characterized in that, the method comprising: providing a substrate, said substrate comprising a trench in the surface of the body layer and a body layer located; the trench bottom and the sides wall forming sacrificial oxide layer; forming a heavily doped polysilicon region over a sacrificial oxide layer at the bottom of the trench, and removing the sacrificial oxide layer located above type heavily doped polysilicon region of the trench sidewalls; said weight doped polysilicon region completely covering the sacrificial oxide layer on the bottom of the trench; forming a gate dielectric layer in the trench having sidewalls and a bottom heavily doped region of polysilicon type, the gate dielectric located heavily doped polysilicon region of the type thickness of the layer is greater than the thickness of the sidewall of the trench gate dielectric layer; the bulk layer comprising: a semiconductor substrate; an epitaxial layer on a surface of said semiconductor substrate, said epitaxial layer having a well region; a the dielectric barrier layer on the surface of the epitaxial layer; the dielectric barrier layer for forming the well region.
  2. 2. 根据权利要求1所述的方法,其特征在于,所述沟槽底部重掺杂型多晶硅区域栅介质层的生长速度大于所述沟槽侧壁单晶硅区域栅介质层的生长速度。 2. The method according to claim 1, wherein the growth rate of the trench bottom heavily doped polysilicon region of the gate dielectric layer is greater than the growth rate of the monocrystalline silicon region trench sidewall gate dielectric layer.
  3. 3. 根据权利要求1所述的方法,其特征在于,所述重掺杂型多晶硅区域的厚度为40QA-5000 A〇 3. The method according to claim 1, wherein the thickness of the heavily doped polysilicon region is 40QA-5000 A〇
  4. 4. 根据权利要求1所述的方法,其特征在于,所述重掺杂型多晶硅区域的掺杂类型为N 型。 4. The method according to claim 1, characterized in that said heavily doped polysilicon region type doping type is N-type.
  5. 5. 根据权利要求1所述的方法,其特征在于,所述重掺杂型多晶硅区域的掺杂浓度大于lel9cm-3〇 The method according to claim 1, wherein the doping concentration of the heavily doped polysilicon type region is greater than lel9cm-3〇
  6. 6. 根据权利要求1所述的方法,其特征在于,所述在具有重掺杂型多晶硅区域的沟槽底部和侧壁形成栅介质层具体为: 在高压和湿氧的环境下,采用热氧化工艺,在具有重掺杂型多晶硅区域的沟槽底部和侧壁形成栅介质层。 6. The method according to claim 1, wherein, said trench having sidewalls and a bottom heavily doped region type polysilicon layer forming the gate dielectric is specifically: wet and oxygen under high pressure environment, thermal oxidation process, the gate dielectric layer is formed in the trench having sidewalls and a bottom heavily doped region of polysilicon type.
  7. 7. 根据权利要求1所述的方法,其特征在于,所述牺牲氧化层的厚度在400A-2000 A 的范围内。 7. The method according to claim 1, wherein the thickness of the sacrificial oxide layer is in the range of 400A-2000 A.
  8. 8. 根据权利要求7所述的方法,其特征在于,所述介质阻挡层的厚度在400A-1000人的范围内。 8. The method according to claim 7, wherein said dielectric barrier layer thickness in the range 400A-1000 human.
  9. 9. 一种采用权利要求1-8任一项所述方法制作的沟槽场效应器件。 A claim using a trench field effect device made by the method of any of 1-8.
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