CN115513061A - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
- Publication number
- CN115513061A CN115513061A CN202211462914.0A CN202211462914A CN115513061A CN 115513061 A CN115513061 A CN 115513061A CN 202211462914 A CN202211462914 A CN 202211462914A CN 115513061 A CN115513061 A CN 115513061A
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- epitaxial layer
- conductivity type
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims description 58
- 239000003989 dielectric material Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000009499 grossing Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 24
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000009825 accumulation Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 14
- -1 aluminum ions Chemical class 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000005922 Phosphane Substances 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- CECABOMBVQNBEC-UHFFFAOYSA-K aluminium iodide Chemical compound I[Al](I)I CECABOMBVQNBEC-UHFFFAOYSA-K 0.000 description 2
- 229910001439 antimony ion Inorganic materials 0.000 description 2
- 229910000410 antimony oxide Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910000413 arsenic oxide Inorganic materials 0.000 description 2
- 229960002594 arsenic trioxide Drugs 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052810 boron oxide Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- KTTMEOWBIWLMSE-UHFFFAOYSA-N diarsenic trioxide Chemical compound O1[As](O2)O[As]3O[As]1O[As]2O3 KTTMEOWBIWLMSE-UHFFFAOYSA-N 0.000 description 2
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910001449 indium ion Inorganic materials 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910000064 phosphane Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The application relates to a preparation method of a semiconductor structure and the semiconductor structure. A method of fabricating a semiconductor structure, comprising: forming an epitaxial layer; forming a fillet groove in the epitaxial layer; forming a first dielectric layer at the bottom of the fillet groove; and forming a second dielectric layer on the surface of the first dielectric layer and the side wall of the fillet groove, and forming a conducting layer in the fillet groove, wherein the conducting layer is positioned on the surface of the second dielectric layer. The fillet groove is formed in the epitaxial layer, the accumulation of an electric field at the bottom of the groove can be reduced, the first dielectric layer and the second dielectric layer are overlapped, the oxide layer with the thickened bottom can be obtained, the voltage resistance of the gate oxide layer is improved, and the semiconductor structure is better protected.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the continuous improvement of Semiconductor process technology, a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) can reduce the manufacturing cost due to its smaller size, and is currently widely used in various Semiconductor device products.
However, the trench gate type silicon carbide MOSFET causes a reliability problem of the device due to electric field accumulation at the gate oxide layer with sharp corners at the bottom of the trench.
Disclosure of Invention
In view of the above, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor structure, including:
forming an epitaxial layer;
forming a fillet groove in the epitaxial layer;
forming a first dielectric layer at the bottom of the fillet groove;
and forming a second dielectric layer on the surface of the first dielectric layer and the side wall of the fillet groove, and forming a conducting layer in the fillet groove, wherein the conducting layer is positioned on the surface of the second dielectric layer.
In one embodiment, a well region of a first conductivity type and a source region of a second conductivity type are formed in the epitaxial layer; after the forming of the epitaxial layer and before forming the fillet trench in the epitaxial layer, the method further comprises:
carrying out first ion implantation on the epitaxial layer to form an initial well region of a first conductivity type in the epitaxial layer;
performing a second ion implantation on the initial well region of the first conductivity type to form a well region of the first conductivity type and a source region of the second conductivity type, wherein the source region of the second conductivity type is located on the surface of the well region of the first conductivity type; the fillet groove penetrates through the source region of the second conduction type and the well region of the first conduction type along the thickness direction and extends into the epitaxial layer below the well region of the first conduction type.
In one embodiment, the forming of the rounded trench in the epitaxial layer includes:
forming a graphical mask layer on the surface of the epitaxial layer, wherein the graphical mask layer is internally provided with a first opening;
etching the epitaxial layer based on the first opening to form an initial groove in the epitaxial layer; the initial groove penetrates through the source region of the second conduction type and the well region of the first conduction type along the thickness direction and extends into the epitaxial layer below the well region of the first conduction type;
removing the graphical mask layer;
and carrying out smoothing treatment on the bottom corner and the top corner of the initial groove to obtain the fillet groove.
In one embodiment, the forming a patterned mask layer on the surface of the epitaxial layer, the patterned mask layer having a first opening therein, includes:
forming a mask layer on the surface of the epitaxial layer;
forming a light resistance layer on the surface of the mask layer far away from the epitaxial layer;
exposing and developing the light resistance layer to obtain a patterned light resistance layer, wherein a second opening is formed in the patterned light resistance layer;
and etching the mask layer based on the second opening to obtain the patterned mask layer with the first opening.
In one embodiment, the forming a first dielectric layer at the bottom of the rounded trench includes:
forming a first dielectric material layer in the fillet groove and on the surface of the epitaxial layer;
removing the first dielectric material layer protruding out of the fillet groove and the first dielectric material layer positioned on the surface of the epitaxial layer;
and etching back the residual first dielectric material layer, and removing part of the first dielectric material layer positioned in the fillet groove to obtain the first dielectric layer.
In one embodiment, a silicon dioxide material layer is formed as a first dielectric material layer in the rounded corner trench and on the surface of the epitaxial layer by using a high density plasma chemical vapor deposition method.
In one embodiment, forming a second dielectric layer on the surface of the first dielectric layer and the sidewall of the rounded trench, and forming a conductive layer in the rounded trench includes:
forming a second dielectric material layer on the surface of the first dielectric layer, the side wall of the fillet groove and the surface of the epitaxial layer;
forming a conductive material layer on the surface of the second dielectric material layer;
and removing the second dielectric material layer and the conductive material layer which protrude out of the fillet groove to obtain the second dielectric layer and the conductive layer.
The present application further provides a semiconductor structure comprising:
the epitaxial layer is internally provided with a fillet groove;
the first dielectric layer is positioned at the bottom of the fillet groove;
the second dielectric layer is positioned on the surface of the first dielectric layer and the side wall of the fillet groove;
and the conducting layer is positioned in the fillet groove and positioned on the surface of the second dielectric layer.
In one embodiment, the epitaxial layer further has a well region of a first conductivity type and a source region of a second conductivity type therein; the well region of the first conductive type is positioned at the periphery of the fillet groove; the source region of the second conduction type is located on the periphery of the fillet groove and located on the surface of the well region of the first conduction type.
In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.
According to the preparation method of the semiconductor structure, the fillet groove is formed in the epitaxial layer so as to reduce accumulation of an electric field at the bottom of the groove; through forming the first dielectric layer at the bottom of the fillet groove and forming the second dielectric layer on the surface of the first dielectric layer and the side wall of the fillet groove, the oxide layer with the thickened bottom can be obtained by superposing the first dielectric layer and the second dielectric layer so as to improve the pressure resistance of the gate oxide layer, and after the conductive layer is formed in the fillet groove, the gate structure with high pressure resistance effect can be obtained.
The semiconductor structure comprises an epitaxial layer, a first dielectric layer, a second dielectric layer and a conductive layer, wherein a fillet groove is formed in the epitaxial layer so as to reduce accumulation of an electric field at the bottom of the groove; the first dielectric layer is located at the bottom of the fillet groove, the second dielectric layer is located on the surface of the first dielectric layer and the side wall of the fillet groove, and the oxide layer with the thickened bottom can be obtained by superposing the first dielectric layer and the second dielectric layer so as to improve the pressure resistance of the gate oxide layer and further improve the pressure resistance of the semiconductor structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
fig. 2 is a schematic cross-sectional structure diagram of a structure obtained in step S11 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 3 is a schematic cross-sectional structure diagram of a structure obtained by performing a first ion implantation on the epitaxial layer to form an initial well region of the first conductivity type in the epitaxial layer in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 4 is a schematic cross-sectional structure diagram of a structure obtained by performing a second ion implantation on the initial well region of the first conductivity type to form a well region of the first conductivity type and a source region of the second conductivity type in the method for manufacturing a semiconductor structure according to an embodiment;
FIG. 5 is a flowchart illustrating a step S12 of a method for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 6 is a schematic cross-sectional structure diagram of a structure obtained in step S1211 in the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 7 is a schematic cross-sectional structure view of a structure obtained in step S1212 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 8 is a schematic cross-sectional structure diagram of a structure obtained in step S1213 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 9 is a schematic cross-sectional structure view of a structure obtained in step S1214 in the method for manufacturing a semiconductor structure provided in one embodiment;
FIG. 10 is a schematic cross-sectional view illustrating a structure obtained by removing the patterned photoresist layer in the method for fabricating a semiconductor structure according to an embodiment;
fig. 11 is a schematic cross-sectional structure view illustrating a structure obtained in step S122 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 12 is a schematic cross-sectional structure view of a structure obtained in step S123 of the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 13 is a schematic cross-sectional view illustrating the structure obtained in step S124 in the method for fabricating a semiconductor structure according to an embodiment;
FIG. 14 is a flowchart illustrating a step S13 of a method for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 15 is a schematic cross-sectional structure diagram of a structure obtained in step S131 in the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 16 is a schematic cross-sectional view illustrating a structure obtained in step S132 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 17 is a schematic cross-sectional structure view of the structure obtained in step S133 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 18 is a flowchart illustrating a step S14 of a method for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 19 is a schematic cross-sectional structure view of the structure obtained in step S141 of the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 20 is a schematic cross-sectional structure diagram of the structure obtained in step S142 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 21 is a schematic cross-sectional structure view of the structure obtained in step S143 in the method for manufacturing a semiconductor structure provided in one embodiment.
Description of the reference numerals:
1. an epitaxial layer; 111. an initial well region of a first conductivity type; 11. a well region of a first conductivity type; 12. a source region of a second conductivity type; 2. patterning the mask layer; 21. a mask layer; 22. a photoresist layer; 23. patterning the photoresist layer; 24. a second opening; 25. a first opening; 3. a fillet groove; 31. an initial groove; 4. a first dielectric layer; 41. a first dielectric material layer; 5. a second dielectric layer; 51. a second dielectric material layer; 6. a conductive layer; 61. a layer of conductive material.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
With the continuous improvement of Semiconductor process technology, trench-gate silicon carbide MOSFETs (Metal-Oxide-Semiconductor Field Effect transistors) have a smaller size, so that the manufacturing cost thereof can be reduced. However, the trench gate type silicon carbide MOSFET causes a reliability problem of the device due to electric field accumulation at the gate oxide layer with sharp corners at the bottom of the trench.
In view of the above, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure.
As shown in fig. 1, the present application provides a method for fabricating a semiconductor structure, comprising:
s11: forming an epitaxial layer;
s12: forming a fillet groove in the epitaxial layer;
s13: forming a first dielectric layer at the bottom of the fillet groove;
s14: and forming a second dielectric layer on the surface of the first dielectric layer and the side wall of the fillet groove, and forming a conductive layer in the fillet groove, wherein the conductive layer is positioned on the surface of the second dielectric layer.
In the method for manufacturing the semiconductor structure in the above embodiment, the rounded trench is formed in the epitaxial layer to reduce the accumulation of the electric field at the bottom of the trench; through forming the first dielectric layer at the bottom of fillet slot and forming the second dielectric layer on the surface of first dielectric layer and the lateral wall of fillet slot, the stack of first dielectric layer and second dielectric layer can obtain the oxide layer that the bottom thickens to improve gate oxide's pressure resistance, behind the formation conducting layer in fillet slot 3, can obtain the grid structure that has high withstand voltage effect.
In some embodiments, the epitaxial layer may comprise a silicon carbide layer; the first dielectric layer and the second dielectric layer may both comprise a silicon oxide layer; the conductive layer may include a polysilicon layer, a titanium nitride layer, or the like.
In step S11, please refer to step S11 in fig. 1 and fig. 2, an epitaxial layer 1 is formed.
In one embodiment, a well region 11 of a first conductivity type and a source region 12 of a second conductivity type are formed in the epitaxial layer 1; after the epitaxial layer 1 is formed, before the fillet trench 3 is formed in the epitaxial layer 1, the method further includes: performing a first ion implantation on the epitaxial layer 1 to form an initial well region 111 of the first conductivity type in the epitaxial layer 1, where the resulting structure is shown in fig. 3; performing a second ion implantation on the initial well region 111 of the first conductivity type to form a well region 11 of the first conductivity type and a source region 12 of the second conductivity type, where the resulting structure is shown in fig. 4, and the source region 12 of the second conductivity type is located on the surface of the well region 11 of the first conductivity type; the rounded trench 3 penetrates through the second conductivity type source region 12 and the first conductivity type well region 11 along the thickness direction, and extends into the epitaxial layer 1 below the first conductivity type well region 11.
Wherein the content of the first and second substances,performing a first ion implantation on the epitaxial layer 1, wherein the doping ions may include at least one of aluminum ions, boron ions, indium ions or gallium ions, and have a doping concentration of 10E16cm -3 ~10E17cm -3 (ii) a The doping material may include: aluminum nitride, aluminum oxide, aluminum chloride, aluminum iodide, boron nitride, boron oxide, gallium nitride, or indium oxide, and other doping materials can be used, without being limited to the exemplified doping materials. Performing a second ion implantation on the initial well region 111 of the first conductivity type, wherein the doping ions may include at least one of nitrogen ions, phosphorus ions, arsenic ions or antimony ions, and have a doping concentration of 10E19cm -3 ~10E21cm -3 (ii) a The doping material may include: nitrogen, phosphane, arsenic oxide or antimony oxide, but also other doping materials, without being limited to the exemplified doping materials.
In particular, the concentration of the doping ions in the well region 11 of the first conductivity type may be 10E16cm -3 Or 10E17cm -3 Or other positions at 10E16cm -3 ~10E17cm -3 Without being limited by the illustrated examples; the concentration of the dopant ions in the source region 12 of the second conductivity type may be 10E19cm -3 、10E20cm -3 Or 10E21cm -3 Or other positions at 10E19cm -3 ~10E21cm -3 Without being limited by the illustrated embodiment. And the work functions of the well region 11 of the first conductivity type and the source region 12 of the second conductivity type can be changed by changing the concentration of the doping ions, so that the work function of the gate structure can be reduced by regulating the concentration of the doping ions, and the risk of electric leakage of the structure is further reduced.
Further, after performing a second ion implantation on the initial well region 111 of the first conductivity type to form the well region 11 of the first conductivity type and the source region 12 of the second conductivity type, the method further includes: and annealing the obtained structure.
In the above embodiment, before forming the rounded trench 3, ion implantation is performed in the epitaxial layer 1 to obtain the well region 11 of the first conductivity type and the source region 12 of the second conductivity type, so that damage to the trench due to ion implantation performed after forming the trench can be avoided.
In one embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type; or the first conductivity type may be N-type and the second conductivity type may be P-type.
Specifically, the well region 11 of the first conductivity type may include a P-well region, and the source region 12 of the second conductivity type may include an N + source region.
In step S12, please refer to step S12 in fig. 1 and fig. 5 to fig. 13, a rounded corner trench 3 is formed in the epitaxial layer 1.
In one embodiment, as shown in fig. 5, forming a rounded trench 3 in the epitaxial layer 1 includes:
s121: forming a patterned mask layer 2 on the surface of the epitaxial layer 1, wherein the patterned mask layer 2 is provided with a first opening 25;
s122: etching the epitaxial layer 1 based on the first opening 25 to form an initial trench 31 in the epitaxial layer 1; the initial trench 31 penetrates through the second conductivity type source region 12 and the first conductivity type well region 11 along the thickness direction, and extends into the epitaxial layer 1 below the first conductivity type well region 11;
s123: removing the graphical mask layer 2;
s124: the bottom corners and top corners of the initial trenches 31 are rounded to obtain rounded trenches 3.
Specifically, the patterned mask layer 2 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
In step S121, please refer to step S121 in fig. 5 and fig. 6 to 9, a patterned mask layer 2 is formed on the surface of the epitaxial layer 1, and the patterned mask layer 2 has a first opening 25 therein.
In one embodiment, forming a patterned mask layer 2 on the surface of the epitaxial layer 1, where the patterned mask layer 2 has a first opening 25 therein, may include:
s1211: forming a mask layer 21 on the surface of the epitaxial layer 1, as shown in fig. 6;
s1212: forming a photoresist layer 22 on the surface of the mask layer 21 away from the epitaxial layer 1, as shown in fig. 7;
s1213: exposing and developing the photoresist layer 22 to obtain a patterned photoresist layer 23, wherein the patterned photoresist layer 23 has a second opening 24 therein, as shown in fig. 8;
s1214: the masking layer 21 is etched on the basis of the second openings 24 to obtain a patterned masking layer 2 having first openings 25, as shown in fig. 9.
Wherein, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method can be adopted to form a mask layer 21 on the surface of the epitaxial layer 1, and the mask layer 21 is grown in an oxygen-rich and self-biased growth mode to adjust the selection ratio (patterned mask layer/epitaxial layer) of the subsequently obtained patterned mask layer 2 in the dry etching of the epitaxial layer 1 to be more than 3; the mask layer 21 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
In some examples, the photoresist layer 22 may include a positive photoresist layer, and may also include a negative photoresist layer.
In step S1214, the mask layer 21 may be etched based on the second opening 24 by using a dry etching method.
Further, after etching mask layer 21 based on second opening 24 to obtain patterned mask layer 2 with first opening 25, the method further includes: the patterned photoresist layer 23 is removed, and the resulting structure is shown in fig. 10.
In step S122, referring to step S122 in fig. 5 and fig. 11, the epitaxial layer 1 is etched based on the first opening 25 to form an initial trench 31 in the epitaxial layer 1; the initial trench 31 penetrates the second conductivity type source region 12 and the first conductivity type well region 11 along the thickness direction, and extends into the epitaxial layer 1 under the first conductivity type well region 11.
Wherein, a dry etching process may be adopted to etch the epitaxial layer 1 based on the first opening 25 to obtain an initial trench 31; further, the dry etching process can select an inductively coupled plasma etching process of high-anisotropy and high-density plasma, the etching atmosphere can be a mixed atmosphere formed by mixing chlorine-based/fluorine-based gas and oxygen, and in the etching process, the inclination angle of the side wall of the initial groove 31 is kept as consistent as possible (kept in a 11-20 crystal plane), so that higher mobility can be obtained; the bottom corners of the initial trenches 31 are relatively sharp, and the use of this type of trench as a gate trench causes an electric field to build up at the bottom corners, causing abnormal discharge.
In the above embodiment, the initial trench 31 penetrates through the second conductivity type source region 12 and the first conductivity type well region 11 along the thickness direction and extends into the epitaxial layer 1 under the first conductivity type well region 11, and the second conductivity type source region 12 and the first conductivity type well region 11 are obtained before the initial trench 31 is formed, so that the initial trench 31 is not damaged by ions.
In step S123, please refer to step S123 in fig. 5 and fig. 12, the patterned mask layer 2 is removed.
Specifically, the patterned mask layer 2 may be removed by wet etching.
In step S124, please refer to step S124 in fig. 5 and fig. 13, the bottom corners and the top corners of the initial trench 31 are rounded to obtain the rounded trench 3.
Wherein, the bottom corner and the top corner of the initial trench 31 can be rounded by adopting an isotropic dry etching process or a high-temperature annealing process; the annealing gas in the high-temperature annealing process can adopt argon or argon/silane mixed gas.
In step S13, referring to step S13 in fig. 1 and fig. 14 to 17, a first dielectric layer 4 is formed at the bottom of the rounded trench 3.
In one embodiment, as shown in fig. 14, forming a first dielectric layer 4 at the bottom of the rounded trench 3 includes:
s131: forming a first dielectric material layer 41 in the rounded trench 3 and on the surface of the epitaxial layer 1, and obtaining a structure as shown in fig. 15; specifically, the first dielectric material layer 41 may be formed by a High Density Plasma Chemical Vapor Deposition (HDPCVD) method, and the first dielectric material layer 41 may include a silicon dioxide layer.
S132: removing the first dielectric material layer 41 protruding from the rounded corner trench 3 and the first dielectric material layer 41 on the surface of the epitaxial layer 1, and obtaining a structure as shown in fig. 16; specifically, the first dielectric material layer 41 protruding from the fillet trenches 3 and the first dielectric material layer 41 on the surface of the epitaxial layer 1 may be removed by etching or Chemical Mechanical Polishing (CMP).
S133: etching back the remaining first dielectric material layer 41, and removing part of the first dielectric material layer 41 located in the rounded corner trench 3 to obtain a first dielectric layer 4, where the obtained structure is shown in fig. 17; specifically, the method for etching back the remaining first dielectric material layer 41 includes a wet etching method, and the etching solution is selected from dilute Hydrofluoric Acid (Buffered etching solution (BOE) or Buffered Hydrofluoric Acid (BHF)) Buffered by ammonium fluoride, where the Buffered etching solution can slow down and stabilize the etching process, so that the etching process can be well controlled.
In one embodiment, a silicon dioxide material layer may be formed as the first dielectric material layer 41 in the rounded trench 3 and on the surface of the epitaxial layer 1 by using a high density plasma chemical vapor deposition method.
In step S14, please refer to step S14 in fig. 1 and fig. 18 to fig. 21, a second dielectric layer 5 is formed on the surface of the first dielectric layer 4 and the sidewall of the rounded trench 3, and a conductive layer 6 is formed in the rounded trench 3, wherein the conductive layer 6 is located on the surface of the second dielectric layer 5.
In one embodiment, as shown in fig. 18, forming a second dielectric layer 5 on the surface of the first dielectric layer 4 and the sidewall of the rounded trench 3, and forming a conductive layer 6 in the rounded trench 3, includes:
s141: forming a second dielectric material layer 51 on the surface of the first dielectric layer 4, the sidewall of the rounded trench 3 and the surface of the epitaxial layer 1, and obtaining a structure as shown in fig. 19; specifically, a second dielectric material layer 51 can be formed on the surface of the first dielectric layer 4, the side wall of the fillet groove 3 and the surface of the epitaxial layer 1 by adopting a dry oxygen oxidation mode, wherein the temperature of the dry oxygen oxidation is 1100-1400 ℃; the second dielectric material layer 51 may comprise a silicon dioxide layer.
S142: forming a conductive material layer 61 on the surface of the second dielectric material layer 51, the resulting structure is shown in fig. 20; specifically, the conductive material layer 61 may include a polysilicon layer, a titanium nitride layer, or the like.
S143: the second dielectric material layer 51 and the conductive material layer 61 protruding from the corner trench 3 are removed to obtain the second dielectric layer 5 and the conductive layer 6, and the resulting structure is shown in fig. 21.
Wherein, the second dielectric material layer 51 and the second dielectric layer 5 may both include a silicon oxide layer; the conductive material layer 61 and the conductive layer 6 may each include a polysilicon layer, a titanium nitride layer, or the like.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a part of the steps in the flowcharts of the embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
The present application further provides a semiconductor structure, as shown in fig. 21, the semiconductor structure comprising: the epitaxial layer 1, the first dielectric layer 4, the second dielectric layer 5 and the conducting layer 6; a fillet groove 3 is formed in the epitaxial layer 1; the first medium layer 4 is positioned at the bottom of the fillet groove 3; the second medium layer 5 is positioned on the surface of the first medium layer 4 and the side wall of the fillet groove 3; the conductive layer 6 is located in the rounded trench 3 and on the surface of the second dielectric layer 5.
In some embodiments, epitaxial layer 1 may comprise a silicon carbide layer; the first dielectric layer 4 and the second dielectric layer 5 may each include a silicon oxide layer; the conductive layer 6 may include a polysilicon layer, a titanium nitride layer, or the like.
The semiconductor structure in the above embodiment includes an epitaxial layer 1, a first dielectric layer 4, a second dielectric layer 5 and a conductive layer 6, wherein a rounded trench 3 is formed in the epitaxial layer 1 to reduce the accumulation of an electric field at the bottom of the trench; the first dielectric layer 4 is located at the bottom of the fillet groove 3, the second dielectric layer 5 is located on the surface of the first dielectric layer 4 and the side wall of the fillet groove 3, and the oxide layer with the thickened bottom can be obtained by overlapping the first dielectric layer 4 and the second dielectric layer 5, so that the pressure resistance of the gate oxide layer is improved, and further, the pressure resistance of the semiconductor structure is improved.
In one embodiment, the epitaxial layer 1 further has a well region 11 of the first conductivity type and a source region 12 of the second conductivity type therein; the well region 11 of the first conductivity type is located at the periphery of the rounded trench 3; the source region 12 of the second conductivity type is located at the periphery of the rounded trench 3 and at the surface of the well region 11 of the first conductivity type.
In some examples, the doping ions in the well region 11 of the first conductivity type may include at least one of aluminum ions, boron ions, indium ions, or gallium ions, with a doping concentration of 10E16cm -3 ~10E17cm -3 (ii) a In particular, the concentration of the doping ions in the well region 11 of the first conductivity type may be 10E16cm -3 Or 10E17cm -3 Or other positions at 10E16cm -3 ~10E17cm -3 Without being limited by the illustrated examples; the doping material may include: aluminum nitride, aluminum oxide, aluminum chloride, aluminum iodide, boron nitride, boron oxide, gallium nitride, or indium oxide, and may be other doping materials, and are not limited to the exemplified doping materials.
In some examples, the dopant ions in the second conductive-type source region 12 may include at least one of nitrogen ions, phosphorus ions, arsenic ions, or antimony ions with a doping concentration of 10E19cm -3 ~10E21cm -3 (ii) a Specifically, the concentration of the dopant ions in the second conductive-type source region 12 may be 10E19cm -3 、10E20cm -3 Or 10E21cm -3 Or other positions at 10E19cm -3 ~10E21cm -3 Without being limited by the illustrated examples; the doping material may include: nitrogen, phosphane, arsenic oxide or antimony oxide, but also other doping materials, without being limited to the exemplified doping materials.
In one embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type; or the first conductivity type may be N-type and the second conductivity type may be P-type.
Specifically, the well region 11 of the first conductivity type may include a P-well region, and the source region 12 of the second conductivity type may include an N + source region.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
forming an epitaxial layer;
forming a fillet groove in the epitaxial layer;
forming a first dielectric layer at the bottom of the fillet groove;
and forming a second dielectric layer on the surface of the first dielectric layer and the side wall of the fillet groove, and forming a conducting layer in the fillet groove, wherein the conducting layer is positioned on the surface of the second dielectric layer.
2. The method of claim 1, wherein a well region of a first conductivity type and a source region of a second conductivity type are formed in the epitaxial layer; after the forming of the epitaxial layer and before forming the fillet trench in the epitaxial layer, the method further comprises:
carrying out first ion implantation on the epitaxial layer so as to form an initial well region of a first conduction type in the epitaxial layer;
performing a second ion implantation on the initial well region of the first conductivity type to form a well region of the first conductivity type and a source region of the second conductivity type, wherein the source region of the second conductivity type is located on the surface of the well region of the first conductivity type; the fillet groove penetrates through the source region of the second conduction type and the well region of the first conduction type along the thickness direction and extends into the epitaxial layer below the well region of the first conduction type.
3. The method of claim 2, wherein forming the rounded trench in the epitaxial layer comprises:
forming a graphical mask layer on the surface of the epitaxial layer, wherein the graphical mask layer is internally provided with a first opening;
etching the epitaxial layer based on the first opening to form an initial groove in the epitaxial layer; the initial groove penetrates through the source region of the second conduction type and the well region of the first conduction type along the thickness direction and extends into the epitaxial layer below the well region of the first conduction type;
removing the graphical mask layer;
and carrying out smoothing treatment on the bottom corner and the top corner of the initial groove to obtain the fillet groove.
4. The method of claim 3, wherein forming a patterned mask layer on the surface of the epitaxial layer, the patterned mask layer having a first opening therein, comprises:
forming a mask layer on the surface of the epitaxial layer;
forming a light resistance layer on the surface of the mask layer far away from the epitaxial layer;
exposing and developing the light resistance layer to obtain a patterned light resistance layer, wherein a second opening is formed in the patterned light resistance layer;
and etching the mask layer based on the second opening to obtain the patterned mask layer with the first opening.
5. The method of claim 1, wherein forming a first dielectric layer at the bottom of the rounded trench comprises:
forming a first dielectric material layer in the fillet groove and on the surface of the epitaxial layer;
removing the first dielectric material layer protruding out of the fillet groove and the first dielectric material layer positioned on the surface of the epitaxial layer;
and etching the residual first dielectric material layer back, and removing part of the first dielectric material layer positioned in the fillet groove to obtain the first dielectric layer.
6. The method of claim 5, wherein a silicon dioxide layer is formed as the first dielectric material layer in the rounded trench and on the surface of the epitaxial layer by high density plasma chemical vapor deposition.
7. The method of claim 1, wherein forming a second dielectric layer on the surface of the first dielectric layer and the sidewalls of the corner trench, and forming a conductive layer in the corner trench comprises:
forming a second dielectric material layer on the surface of the first dielectric layer, the side wall of the fillet groove and the surface of the epitaxial layer;
forming a conductive material layer on the surface of the second dielectric material layer;
and removing the second dielectric material layer and the conductive material layer which protrude out of the fillet groove to obtain the second dielectric layer and the conductive layer.
8. A semiconductor structure, comprising:
the epitaxial layer is internally provided with a fillet groove;
the first dielectric layer is positioned at the bottom of the fillet groove;
the second dielectric layer is positioned on the surface of the first dielectric layer and the side wall of the fillet groove;
and the conducting layer is positioned in the fillet groove and positioned on the surface of the second dielectric layer.
9. The semiconductor structure of claim 8, wherein said epitaxial layer further has a well region of a first conductivity type and a source region of a second conductivity type therein; the well region of the first conductive type is positioned at the periphery of the fillet groove; the source region of the second conductive type is positioned at the periphery of the rounded corner groove and positioned on the surface of the well region of the first conductive type.
10. The semiconductor structure of claim 9, wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211462914.0A CN115513061A (en) | 2022-11-22 | 2022-11-22 | Preparation method of semiconductor structure and semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211462914.0A CN115513061A (en) | 2022-11-22 | 2022-11-22 | Preparation method of semiconductor structure and semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115513061A true CN115513061A (en) | 2022-12-23 |
Family
ID=84513693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211462914.0A Pending CN115513061A (en) | 2022-11-22 | 2022-11-22 | Preparation method of semiconductor structure and semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115513061A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001119023A (en) * | 1999-10-20 | 2001-04-27 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN103247529A (en) * | 2012-02-10 | 2013-08-14 | 无锡华润上华半导体有限公司 | Groove field effect device and manufacturing method thereof |
| CN105047542A (en) * | 2015-09-06 | 2015-11-11 | 国网智能电网研究院 | Method for manufacturing grooved silicon carbide MOSFET power device |
| US20150340487A1 (en) * | 2014-05-23 | 2015-11-26 | Infineon Technologies Ag | Semiconductor Device Having a Lower Diode Region Arranged Below a Trench |
| CN105702715A (en) * | 2014-12-11 | 2016-06-22 | 英飞凌科技股份有限公司 | Method of forming a silicon-carbide device with a shielded gate |
| CN109119473A (en) * | 2018-08-15 | 2019-01-01 | 深圳市南硕明泰科技有限公司 | A kind of transistor and preparation method thereof |
| CN112466747A (en) * | 2019-09-06 | 2021-03-09 | 芯恩（青岛）集成电路有限公司 | Manufacturing method of trench gate and trench gate power device |
| CN114334621A (en) * | 2022-01-04 | 2022-04-12 | 广东芯粤能半导体有限公司 | Semiconductor structure, semiconductor device and preparation method thereof |
| CN114551244A (en) * | 2022-03-11 | 2022-05-27 | 上海华虹宏力半导体制造有限公司 | Preparation method of vertical MOS transistor |
-
2022
- 2022-11-22 CN CN202211462914.0A patent/CN115513061A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| JP2001119023A (en) * | 1999-10-20 | 2001-04-27 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| CN103247529A (en) * | 2012-02-10 | 2013-08-14 | 无锡华润上华半导体有限公司 | Groove field effect device and manufacturing method thereof |
| US20150340487A1 (en) * | 2014-05-23 | 2015-11-26 | Infineon Technologies Ag | Semiconductor Device Having a Lower Diode Region Arranged Below a Trench |
| CN105702715A (en) * | 2014-12-11 | 2016-06-22 | 英飞凌科技股份有限公司 | Method of forming a silicon-carbide device with a shielded gate |
| CN105047542A (en) * | 2015-09-06 | 2015-11-11 | 国网智能电网研究院 | Method for manufacturing grooved silicon carbide MOSFET power device |
| CN109119473A (en) * | 2018-08-15 | 2019-01-01 | 深圳市南硕明泰科技有限公司 | A kind of transistor and preparation method thereof |
| CN112466747A (en) * | 2019-09-06 | 2021-03-09 | 芯恩（青岛）集成电路有限公司 | Manufacturing method of trench gate and trench gate power device |
| CN114334621A (en) * | 2022-01-04 | 2022-04-12 | 广东芯粤能半导体有限公司 | Semiconductor structure, semiconductor device and preparation method thereof |
| CN114551244A (en) * | 2022-03-11 | 2022-05-27 | 上海华虹宏力半导体制造有限公司 | Preparation method of vertical MOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3918565B2 (en) | Manufacturing method of semiconductor device | |
| US7285433B2 (en) | Integrated devices with optical and electrical isolation and method for making | |
| EP1359624A2 (en) | Vertical type MOSFET and manufacturing method thereof | |
| EP1965436B1 (en) | Silicon carbide self-aligned epitaxial mosfet and method of manufacturing thereof | |
| JP2004273742A (en) | Manufacturing method of semiconductor wafer | |
| CN102208336B (en) | Technical method for forming alternately arranged P type and N type semiconductor thin layers | |
| US11575010B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20070202650A1 (en) | Low voltage power MOSFET device and process for its manufacture | |
| CN111403487A (en) | Semiconductor device integrating MOSFET and diode and manufacturing method thereof | |
| US6887760B2 (en) | Fabrication process of a trench gate power MOS transistor with scaled channel | |
| US7466005B2 (en) | Recessed termination for trench schottky device without junction curvature | |
| CN115513061A (en) | Preparation method of semiconductor structure and semiconductor structure | |
| US20220384617A1 (en) | Semiconductor Device and Method | |
| CN114256077A (en) | Method for manufacturing low-voltage separation gate groove MOS device | |
| US20210359109A1 (en) | Semiconductor Device and Method | |
| US10978308B2 (en) | Method for manufacturing a semiconductor device | |
| CN112909075A (en) | Trench MOSFET with charge balance structure and manufacturing method thereof | |
| CN111540672B (en) | Super junction device manufacturing method and super junction device | |
| CN115938924A (en) | Preparation method of semiconductor structure and semiconductor structure | |
| EP4297096A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN115621120B (en) | Semiconductor structure and preparation method thereof | |
| CN212113730U (en) | Semiconductor device integrating MOSFET and diode | |
| CN117393586B (en) | Power semiconductor device and manufacturing method thereof | |
| CN117766401A (en) | Semiconductor device structure and preparation method thereof | |
| CN216980574U (en) | Structure of low-voltage separation gate groove MOS device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20221223 |