CN106684129A - Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT - Google Patents
Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT Download PDFInfo
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- CN106684129A CN106684129A CN201710020572.XA CN201710020572A CN106684129A CN 106684129 A CN106684129 A CN 106684129A CN 201710020572 A CN201710020572 A CN 201710020572A CN 106684129 A CN106684129 A CN 106684129A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 230000015556 catabolic process Effects 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 8
- 230000007774 longterm Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010511 deprotection reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention discloses a method for reducing gate-collector capacitance of a grooved-type IGBT and improving breakdown voltage of the grooved-type IGBT. The method comprises the steps as follows: a thick oxide layer is formed at the bottom of a groove after formation of the groove and before thermal growth of a gate oxide layer; the oxide layer at the bottom of the groove is protected by adopting highly doped polysilicon in the process; residual polysilicon is completely oxidized to become one part of the thick oxide layer at the bottom of the groove and no polysilicon conductive layer is left; and a thin gate oxide layer and a polysilicon gate are formed according to a normal process. According to the method, the yield and the long-term reliability of a device can be improved while the gate-collector capacitance Cgc of the grooved-type IGBT is reduced and the breakdown voltage is strengthened; and the production process and a standard CMOS process are highly compatible. The method is suitable for reducing the gate-collector capacitance of the grooved-type IGBT and improving the breakdown voltage and the reliability of the grooved-type IGBT.
Description
Technical field
The invention belongs to semiconductor power device technology is received, for improving the performance of groove-shaped IGBT, specifically
A kind of method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage.
Background technology
With the continuous development of semiconductor technology, advanced IGBT device adopted trench gate design with improve electric current density,
J-FET effects are eliminated, so as to reduce On-resistance.Fig. 1 is conventional groove type IGBT profile, in this design, chip bottom
Portion is that p-type is adulterated as colelctor electrode, and p-type base separates N-shaped drift region and n+ regions, and electric current is by the raceway groove along trenched side-wall
Flow in vertical direction, trenched side-wall and bottom are covered by thin gate oxide, conductive materials, such as polycrystalline are full of in groove
Silicon, as grid.N+ source regions and p-type base are shorted together, used as emitter stage.
The grid and emitter stage of groove-shaped IGBT is coupled by the thin oxide layer of channel bottom, and the trench gate so made is deposited
In following defect：
1）Reduce breakdown voltage,
2）Cause long-term reliability of the gate oxide problem,
3）Grid-collector capacitance Cgc is dramatically increased, this is because grid and n drift lap are thin grid oxygen
Change layer.This further results in switching speed reduction, and increases gate drive current.Can appreciable impact if gate oxide is thickened
Threshold voltage and device other performances, it is infeasible.
The United States Patent (USP) of Patent No. US 6,262,453 describes a solution, as shown in Fig. 2 being formed in etching
After groove, the oxide layer of long thick layer fills with photoresist groove, then removes part photoresist, only stays a part of photoresist
In channel bottom, so, thick oxide layer is protected, and will not be removed by oxide layer etching technics later, subsequently, channel bottom
Photoresist is eliminated, and proceeds normal thin grid oxide layer and polysilicon gate process.One defect of do so is photoetching
Glue is organic material, and with heavy metal and other impurities, the photoresist removing of channel bottom is highly difficult, it reduces yields,
And cause long-term reliability problems, additionally, compare with depositing technics with oxidation, it is difficult to the thickness of precise control photoresist residual layer
Degree, precision is the difference of tens nanometers and several nanometers of zero point, and this causes the great variety of channel length, affects device performance
Many aspects.
The United States Patent (USP) of Patent No. US 7494876 describes a kind of method：Stay next unadulterated in channel bottom
Polysilicon stopper.Later, thin grid oxide layer and polysilicon gate were formed by normal process, and its profile is as shown in figure 3, polycrystalline
Silicon is conductor, thus leaves conductor in channel bottom.Further to reduce Cgc, it is desirable to which channel bottom filler ratio is not
DOPOS doped polycrystalline silicon more insulate.
The content of the invention
The purpose of the present invention, is to provide for a kind of groove-shaped IGBT grid collection electric capacity of reduction and improves the side of its breakdown voltage
Method, the oxide layer of channel bottom is protected using highly doped polysilicon, then after the highly doped polysilicon of residual is all aoxidized
Become a part for channel bottom thick oxide layer, to can solve the problem that the problems referred to above existing for prior art.
For achieving the above object, the technical scheme for being adopted is as follows for the present invention：
One kind reduces groove-shaped IGBT grid collection electric capacity（Grid collection, i.e. grid-colelctor electrode）And the method for improving its breakdown voltage, in ditch
The technique that groove is followed the steps below before thermally grown gate oxide after being formed to form thick oxide layer in channel bottom,
The first step, in the deposited on top or thermal growth oxide layer of trenched side-wall, bottom and silicon,
Second step, with highly doped polysilicon of the doping content more than 1E20/cm3 groove is full of,
3rd step, anisotropic etching removes the highly doped polysilicon of flute surfaces and until trench bottom after the completion of second step
Portion, remains the highly doped polysilicon of the thickness of gash depth 1/20th,
4th step, using the highly doped polysilicon remained after the completion of the 3rd step as mask, selective clearing highly doped polysilicon
Trenched side-wall, the oxide layer at the top of silicon more than layer,
5th step, the highly doped polysilicon for aoxidizing all residuals makes silicon dioxide oxide layer,
6th step, the oxide layer formed in trenched side-wall after the completion of the step of isotropic etching the 5th；
So far thick oxide layer is defined in channel bottom.
As restriction：6th step complete after according to normal process step, the other parts of manufacture groove type IGBT, doing
By controlling diffusion time, ion implantation energy and concentration when base, it is ensured that the bottom of p-type base is higher than channel bottom shape
Into thick oxide layer.
As second restriction：It is 4 microns that the first step carries out front gash depth, oxidated layer thickness after the completion of the first step
0.3 micron.
As further restriction：After the completion of 3rd step, the thickness for remaining highly doped polysilicon is 0.2 micron.
The present invention as a result of above-mentioned method, its compared with prior art, acquired technological progress is：
（1）Highly doped polysilicon is used to protect the thick oxide layer of channel bottom in the present invention, many due to high-concentration dopant
Crystal silicon oxidation rate is higher than silicon 5 times or more, and the highly doped polysilicon of residual is all aoxidized, and becomes the thick oxidation of channel bottom
A part for layer, does not stay any polysilicon conducting layers.
（2）Production technology of the present invention and standard CMOS process highly compatible；
（3）Thin gate oxide of the present invention and polysilicon gate are formed by normal process；；
（4）The present invention can reduce grid-collector capacitance Cgc of groove-shaped IGBT, improve breakdown voltage, and improve non-defective unit
The long-term reliability of rate and device；
The present invention is applied to be reduced groove-shaped IGBT grid collection electric capacity and improves its breakdown voltage and reliability.
Description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and constitutes a part for description, the reality with the present invention
Applying example is used to explain the present invention together, is not construed as limiting the invention.
In the accompanying drawings：
Fig. 1 is conventional groove type IGBT profile；
Fig. 2 is that prior art does mask deprotection channel bottom thick oxide layer profile using photoresist；
Fig. 3 is reduced grid-capacitance of drain using polysilicon stopper and increases breakdown voltage profile for prior art；
Fig. 4-Fig. 9 is respectively that the embodiment of the present invention completes（1）Step-the（6）After step groove-shaped IGBT into state local
Profile；
Figure 10 is the groove-shaped IGBT profiles that the embodiment of the present invention is finally made.
Specific embodiment
The preferred embodiments of the present invention are illustrated below in conjunction with accompanying drawing.It should be appreciated that preferred reality described herein
Apply example and be merely to illustrate and explain the present invention, be not intended to limit the present invention.
A kind of method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage of embodiment
A kind of method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage, forms in groove（Wherein gash depth
It is 4 microns）Follow the steps below before thermally grown gate oxide afterwards（1）-（6）, to form thick oxide layer in channel bottom,
（1）In the deposited on top or thermal growth oxide layer of trenched side-wall, bottom and silicon, as shown in figure 4, oxidated layer thickness is
0.3 micron；
（2）Groove is full of with highly doped polysilicon of the doping content more than 1E20/cm3, doping content is purposely designed to be more than
1E20/cm3, so that highly doped polysilicon oxidation rate is much larger than silicon substrate, as shown in Figure 5；
（3）Anisotropic etching removes the（2）The highly doped polysilicon of flute surfaces is simultaneously until channel bottom, residual after the completion of step
The thickness highly doped polysilicon of gash depth 1/20th, i.e., 0.2 micron is stayed, as shown in Figure 6；
（4）Using（3）The highly doped polysilicon remained after the completion of step as mask, selective clearing highly doped polysilicon layer with
On trenched side-wall, the oxide layer at the top of silicon, as shown in Figure 7；
（5）As shown in figure 8, the highly doped polysilicon for aoxidizing all residuals makes silicon dioxide oxide layer, due to polysilicon
It is highly doped（More than 1E20/cm3）, its oxidation rate is bigger than the silicon of trenched side-wall 5 times or more, for undoped p or
Lightly doped polysilicon all aoxidizes nubbin and will consume the silicon of comparable thickness, and this can change many parameters, such as ditch
Well width, trench angles, channel doping etc. are so that have a strong impact on device performance, 0.2 micron height DOPOS doped polycrystalline silicon of oxidation only can
On trenched side-wall, the change to trench geometry is negligible the oxide layer of long 0.04 microns,
（6）Isotropic etching（5）The oxide layer formed in trenched side-wall after the completion of step, if trenched side-wall is only long by 0.04
Micron oxide layer（In 0.2 micron of polysilicon process is aoxidized）, etching target is exactly 0.04 micron rather than 0.2 micron, side wall
On oxide layer be also simultaneously sacrificial oxide layer（SAC）, this layer of oxide layer is removed while also removing groove plasma etching
Destruction to silicon crystal lattice；
So far thick oxide layer is defined in channel bottom, as shown in Figure 9.
The（6）Walk after completing according to normal process step, the other parts of manufacture groove type IGBT, should be noted
It is：By controlling diffusion time, ion implantation energy and concentration when base is done, it is ensured that the bottom of p-type base is higher than ditch
The thick oxide layer that trench bottom is formed, as shown in Figure 10.
Finally it should be noted that：The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to,
Although being described in detail to the present invention with reference to the foregoing embodiments, for a person skilled in the art, it still may be used
To modify to the technical scheme described in previous embodiment, or equivalent is carried out to which part technical characteristic.It is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements made etc., should be included in right of the present invention
Within the scope of claimed.
Claims (4)
1. a kind of method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage, it is characterised in that form it in groove
Follow the steps below afterwards to form thick oxide layer in channel bottom before thermally grown gate oxide：
The first step, in the deposited on top or thermal growth oxide layer of trenched side-wall, bottom and silicon,
Second step, with highly doped polysilicon of the doping content more than 1E20/cm3 groove is full of,
3rd step, anisotropic etching removes the highly doped polysilicon of flute surfaces and until trench bottom after the completion of second step
Portion, remains the highly doped polysilicon of the thickness of gash depth 1/20th,
4th step, using the highly doped polysilicon remained after the completion of the 3rd step as mask, selective clearing highly doped polysilicon
Trenched side-wall, the oxide layer at the top of silicon more than layer,
5th step, the highly doped polysilicon for aoxidizing all residuals makes silicon dioxide oxide layer,
6th step, the oxide layer formed in trenched side-wall after the completion of the step of isotropic etching the 5th is extremely formed in channel bottom
Thick oxide layer.
2. the method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage according to claim 1, its feature
It is：6th step complete after according to normal process step, the other parts of manufacture groove type IGBT, wherein, doing base
By controlling diffusion time, ion implantation energy and concentration when area, it is ensured that the bottom of p-type base is formed higher than channel bottom
Thick oxide layer.
3. the method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage according to claim 1 and 2, it is special
Levy and be：It is 4 microns that the first step carries out front gash depth, 0.3 micron of oxidated layer thickness after the completion of the first step.
4. the method for reducing groove-shaped IGBT grid collection electric capacity and improving its breakdown voltage according to claim 3, its feature
It is：After the completion of 3rd step, the thickness for remaining highly doped polysilicon is 0.2 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710020572.XA CN106684129A (en) | 2017-01-12 | 2017-01-12 | Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710020572.XA CN106684129A (en) | 2017-01-12 | 2017-01-12 | Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT |
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| Publication Number | Publication Date |
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| CN106684129A true CN106684129A (en) | 2017-05-17 |
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| CN201710020572.XA Pending CN106684129A (en) | 2017-01-12 | 2017-01-12 | Method for reducing gate-collector capacitance of grooved-type IGBT and improving breakdown voltage of grooved-type IGBT |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403476A (en) * | 2019-01-02 | 2020-07-10 | 株洲中车时代电气股份有限公司 | Trench gate MOS power device and gate manufacturing method thereof |
| CN116564806A (en) * | 2023-07-06 | 2023-08-08 | 捷捷微电(南通)科技有限公司 | Method for increasing thickness of oxide layer at bottom of trench |
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|---|---|---|---|---|
| CN102184855A (en) * | 2010-05-06 | 2011-09-14 | 天津环鑫科技发展有限公司 | Method for manufacturing non-punch-through (NPT) type groove IGBT (Insulated Gate Bipolar Transistor) with field stop structure |
| CN103247529A (en) * | 2012-02-10 | 2013-08-14 | 无锡华润上华半导体有限公司 | Groove field effect device and manufacturing method thereof |
| US20160380096A1 (en) * | 2007-09-03 | 2016-12-29 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
2017
- 2017-01-12 CN CN201710020572.XA patent/CN106684129A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160380096A1 (en) * | 2007-09-03 | 2016-12-29 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN102184855A (en) * | 2010-05-06 | 2011-09-14 | 天津环鑫科技发展有限公司 | Method for manufacturing non-punch-through (NPT) type groove IGBT (Insulated Gate Bipolar Transistor) with field stop structure |
| CN103247529A (en) * | 2012-02-10 | 2013-08-14 | 无锡华润上华半导体有限公司 | Groove field effect device and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403476A (en) * | 2019-01-02 | 2020-07-10 | 株洲中车时代电气股份有限公司 | Trench gate MOS power device and gate manufacturing method thereof |
| CN111403476B (en) * | 2019-01-02 | 2023-08-29 | 株洲中车时代半导体有限公司 | Trench gate MOS power device and gate manufacturing method thereof |
| CN116564806A (en) * | 2023-07-06 | 2023-08-08 | 捷捷微电(南通)科技有限公司 | Method for increasing thickness of oxide layer at bottom of trench |
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