CN111403476A - Trench gate MOS power device and gate manufacturing method thereof - Google Patents
Trench gate MOS power device and gate manufacturing method thereof Download PDFInfo
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- CN111403476A CN111403476A CN201910002574.5A CN201910002574A CN111403476A CN 111403476 A CN111403476 A CN 111403476A CN 201910002574 A CN201910002574 A CN 201910002574A CN 111403476 A CN111403476 A CN 111403476A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
According to the trench gate MOS power device and the gate manufacturing method thereof, two gate oxide layers with different thicknesses are formed at different positions through two thermal oxidation processes, the threshold voltage can meet the normal working requirement of the trench gate MOS power device due to the arrangement of the thin oxide layer, the normal switching action of the MOS power device is ensured, the Miller capacitance can be reduced due to the thick oxide layer, the problem that the switching action is difficult to regulate and control is solved, the switching loss is reduced, the carrier bombardment resistance of the thick oxide layer is strong, and the long-range reliability of the whole device is improved. The invention ensures the normal switching action of the MOS power device, reduces the Miller capacitance, solves the problem that the switching action is difficult to regulate and control, reduces the switching loss, improves the long-range reliability and is not limited by threshold voltage.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a trench gate MOS power device and a gate manufacturing method thereof.
Background
The gate Oxide layer of a conventional trench gate MOS (Metal Oxide Semiconductor) power device is formed by single thermal oxidation. The thickness of the thermal oxide layer cannot be too thick in general due to threshold voltage limitations, i.e. the gate oxide capacitance COXIs relatively large. The miller capacitance of the device can be expressed by the following equation:
grid oxide layer capacitor COXLarger, then Miller capacitance CMillerSo high that the switching behavior is difficult to regulate and the switching losses are difficult to reduce. Meanwhile, as the bottom of the trench is usually a high electric field region, carriers are continuously bombarded and injected into a gate oxide layer at the bottom of the trench in the transportation process, so that the long-range reliability of the gate and the whole device is influenced. The structure of the gate oxide layer of the conventional MOS power device is shown in fig. 1, the whole gate oxide layer is a thin oxide layer 111 formed by single thermal oxidation, the gate body is formed by polysilicon 12, and is arranged in the trench, and the equivalent series capacitance C is between the polysilicon 12 and the collector 13OXAnd CS。
Disclosure of Invention
The method aims to solve the problems that in the prior art, the Miller capacitance of a trench gate MOS power device is high, so that the switching behavior is difficult to regulate and control, and the switching loss is difficult to reduce; the invention provides a trench gate MOS power device and a gate manufacturing method thereof, and the technical problem that long-range reliability of a gate and the whole device is influenced by bombardment of a gate oxide layer by carriers is solved in the following specific scheme:
a method for manufacturing a grid of a groove grid MOS power device comprises the following steps:
step S1: forming a channel region and a groove;
step S2: performing primary oxidation to form a thick oxide layer in the groove;
step S3: removing the unnecessary thick oxide layer;
step S4: performing secondary oxidation to form a thin oxide layer above the thick oxide layer;
step S5: a gate body is formed.
Further, in the step S3, the final etching position of the thick oxide layer is controlled by using a photoresist as a mask.
Further, in the step S2, forming the thick oxide layer on top of the bulk material;
the step S3 includes the following steps:
step S301: filling the photoresist in the groove, and arranging the photoresist on the upper surface of the thick oxide layer;
step S302: exposing the photoresist and controlling the exposure depth of the photoresist;
step S303: removing the exposed photoresist;
step S304: etching the thick oxide layer by using the residual photoresist as a mask;
step S305: and removing the residual photoresist in the groove.
Further, in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the channel region.
Further, in step S1, a carrier injection region is formed, and in step S302, the bottom surface of the exposed photoresist is close to and higher than the bottom surface of the carrier injection region.
Further, in the step S304, the thick oxide layer is etched by using an over-etching method.
Further, in the step S304, the etching amount of the thick oxide layer is controlled by the etching time.
Further, in step S5, polysilicon is deposited in the trench and on the upper surface of the gate oxide layer, so that the trench is filled with the polysilicon, and then the polysilicon is etched so that the upper surface of the polysilicon is lower than the upper surface of the thin oxide layer.
The trench gate MOS power device manufactured by the gate manufacturing method is characterized by comprising a channel region, wherein a gate oxide layer corresponding to the channel region is a thin oxide layer, and a gate oxide layer below the thin oxide layer is a thick oxide layer.
Further, a current carrier injection region is arranged below the channel region and is closely adjacent to the channel region, and a gate oxide layer corresponding to the current carrier injection region is the thin oxide layer.
Compared with the prior art, the trench gate MOS power device and the gate manufacturing method thereof provided by the invention have the advantages that two gate oxide layers with different thicknesses are formed at different positions through two thermal oxidation processes, the threshold voltage can meet the normal working requirement of the trench gate MOS power device due to the arrangement of the thin oxide layer, the normal switching action of the MOS power device is ensured, the Miller capacitance can be reduced due to the thick oxide layer, the problem that the switching action is difficult to regulate and control is solved, the switching loss is reduced, the carrier bombardment resistance of the thick oxide layer is strong, and the long-range reliability of the whole device is improved. The invention ensures the normal switching action of the MOS power device, reduces the Miller capacitance, solves the problem that the switching action is difficult to regulate and control, reduces the switching loss, improves the long-range reliability and is not limited by threshold voltage.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
FIG. 1 is a schematic diagram of an IGBT structure in the prior art;
FIG. 2 is a schematic diagram of an IGBT structure according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of the embodiment of the present invention after step S1 is performed;
FIG. 4 is a schematic structural diagram illustrating the formation of a thick oxide layer after a single thermal oxidation step in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure formed after adding a photoresist in an embodiment of the invention;
FIG. 6 is a schematic structural diagram of a photoresist after exposure according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a structure after removing the exposed photoresist according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of the embodiment of the present invention after etching the thick oxide layer with the remaining photoresist as the mask;
FIG. 9 is a schematic diagram of a structure for removing the residual photoresist in an embodiment of the present invention;
FIG. 10 is a schematic diagram of the structure of the second oxidation to form a thin oxide layer over the thick oxide layer in the embodiment of the present invention in FIG. 7;
FIG. 11 is a schematic structural diagram after deposition of polysilicon in an embodiment of the present invention;
fig. 12 is a schematic structural diagram illustrating the formation of a gate body by etching polysilicon according to an embodiment of the present invention.
In the drawings, like parts are designated with like reference numerals, and the drawings are not necessarily to scale.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
The channel region in the invention refers to a well region which can form an inversion layer under the action of grid voltage;
the gate of the present invention includes a gate body and a gate oxide layer.
The thickness of the gate oxide layer in the invention is a relative concept, and the thickness of the thick oxide layer is thicker than that of the thin oxide layer.
The first embodiment is as follows:
as shown in fig. 2, this embodiment provides a trench gate MOS power device, taking a trench gate IGBT (insulated gate Bipolar transistor) as an example, which includes a channel region, specifically, the channel region of the trench gate IGBT in this embodiment is a P-well region 15. In general, to form a complete trench gate IGBT structure, an N + source region (not shown) contacting the emitter electrode is further disposed above the P-well region 15, which is common knowledge and will not be discussed in detail.
In this embodiment, a carrier injection region immediately adjacent to the P-well region 15 is further disposed below the P-well region 15, specifically, the carrier injection region in this embodiment is an N-well region 14, and the N-well region 14 can improve the injection level of carriers when the trench gate IGBT operates. The gate oxide layers corresponding to the P-well region 15 and the N-well region 14 are the thin oxide layers 111 as the gate oxide layers of the conventional trench gate MOS power device, and therefore, the threshold voltage of the conventional trench gate MOS power device can meet the working requirements of the P-well region 15 and the N-well region 14, so that under the action of the gate voltage, the P-well region 15 forms an inversion layer, and the N-well region 14 forms a depletion layer. The gate oxide layer below the thin oxide layer 111 is the thick oxide layer 112, the arrangement of the thick oxide layer 112 avoids the positions of the P-well region 15 and the N-well region 14, and the problem that the gate oxide layer cannot be too thick due to the limitation of threshold voltage is avoided, and meanwhile, the arrangement of the thick oxide layer 112 below the thin oxide layer 111, namely the bottom of the trench 16, can reduce the miller capacitance according to the calculation formula of the miller capacitance, so that the problem that the switching behavior is difficult to regulate and control is solved, and the switching loss is reduced; the thick oxide layer 112 has strong carrier bombardment resistance, and the long-range reliability of the whole device is improved.
Preferably, the bottom surface of the thin oxide layer 111 is lower than the bottom surface of the N-well region 14, and the top surface of the thin oxide layer 111 is higher than the top surface of the P-well region 15, so as to ensure that both the P-well region 15 and the N-well region 14 can completely correspond to the thin oxide layer 111. The present embodiment symmetrically arranges the P-well region 15 and the N-well region 14 on both sides of the trench 16.
As shown in fig. 3 to fig. 12, the present embodiment further provides a method for manufacturing a gate of a trench gate IGBT, where the method includes the following steps:
step S1: p-well regions 15 as channel regions and N-well regions 14 as carrier injection regions are formed and trenches 16 are etched. Preferably, P-well region 15 and N-well region 14 may be formed first, and then trench 16 may be etched according to the depth of the bottom surface of N-well region 14, where the bottom surface of trench 16 is lower than the bottom surface of N-well region 14. Depth d of bottom surface of N well region 142It is 1.5 μm to 5 μm, preferably 2.5 μm in this example. Etched trenchDepth d of bottom surface of groove 161The particle size is 2 μm to 6 μm, and the particle size is preferably 3.5 μm in this embodiment. The starting references for each depth are the same in this example.
Step S2: a thick oxide layer 112 is formed in the trench 16 by a thermal oxidation process, and a thick oxide layer 112 may also be formed on top of the bulk material, the thickness of the thick oxide layer 112 being between 100nm and 300nm, preferably 200 nm.
Step S3: the unwanted thick oxide layer 112 is removed.
The method comprises the following specific steps:
step S301: the trench 16 is filled with a photoresist 17, the photoresist 17 is disposed on the upper surface of the thick oxide layer 112, and the thickness of the photoresist above the upper surface of the thick oxide layer 112 is 0.5 μm to 2 μm, preferably 1 μm in this embodiment.
Step S302: it is common knowledge in the art to perform front exposure on the photoresist 17 and precisely control the exposure depth of the photoresist 17 by controlling the exposure parameters, and it is not developed herein. The exposure depth is the depth of the bottom surface of the exposed photoresist 171, and the bottom surface of the exposed photoresist 171 may be located near the bottom surface of the N well region 14, may be slightly higher than the bottom surface of the N well region 14, may be slightly lower than the bottom surface of the N well region 14, or may be flush with the bottom surface of the N well region, for example, the exposure depth is 2.5 μm. The bottom surface of the exposed photoresist 171 is slightly higher than the bottom surface of the nwell region 14, which is more favorable for controlling the final etching position of the thick oxide layer 112 by adopting an over-etching manner, i.e. the position of the upper surface of the thick oxide layer 112 relative to the bottom surface of the nwell region 14, and the position of the upper surface of the thick oxide layer 112 is the position of the bottom surface of the thin oxide layer 111.
Step S303: the exposed photoresist 171 is removed by development.
Step S304: the remaining photoresist 172 is not exposed, and the thick oxide layer 112 is wet etched over the entire surface using the remaining photoresist 172 as a mask to remove the unwanted thick oxide layer 112. Specifically, the thick oxide layer 112 on top of the bulk material and the thick oxide layer 112 on top within the trench are removed. The thick oxide layer 112 is etched by using an over-etching method, and the over-etching amount of the thick oxide layer 112 is controlled by using the etching time, in which the over-etching is performed to the thick oxide layer 112 until the upper surface of the over-etching is flush with the upper surface of the unexposed residual photoresist 172, and then the over-etching is continued to etch the thick oxide layer 112, so that the etched upper surface of the thick oxide layer 112 is slightly lower than the bottom surface of the N well region 14, for example, the depth of the upper surface of the thick oxide layer 112 is 2.8 μm.
Step S305: the remaining photoresist 172 within the trench 16 is removed.
After completion of step S3, step S4 is implemented: performing secondary oxidation to form a thin oxide layer 111 above the thick oxide layer 112, wherein the thickness of the thin oxide layer is 50nm-150nm, and preferably 100 nm;
step S5: and depositing polysilicon 12 on the upper surface of the thin oxide layer 111 and in the trench 16, so that the trench is filled with the polysilicon 12, and etching the polysilicon 12 on the whole surface to make the upper surface of the polysilicon 12 slightly lower than the upper surface of the thin oxide layer, thereby forming a gate body consisting of the polysilicon 12.
The bulk material forming the trench gate IGBT in this embodiment may be one of Si, SiC, GaN, or the like, and each well region is formed by doping on the basis of the bulk material. The material of the gate body is not limited to polysilicon and other materials known in the art for making gate bodies may be used in the present invention.
Example two:
the N-well region 14 only serves to increase the level of carrier injection, and removal of the N-well region 14 does not affect the basic function of the trench gate IGBT. The trench gate IGBT provided in this embodiment does not have a carrier injection region, i.e., the N-well region 14 is removed. When the gate of the trench gate IGBT device is manufactured, the N-well region 14 is not formed any more in step S1, and the bottom surface of the trench 16 is lower than the bottom surface of the P-well region 15; in step S302, the bottom surface of exposed photoresist 171 is located near the bottom surface of P-well region 15, and may be slightly higher or lower or even with the bottom surface of P-well region 15. In step S304, the top surface of the finally etched thick oxide layer 112 is slightly lower than the bottom surface of the P-well region 15. The rest is the same as the first embodiment.
The trench gate IGBT in the two embodiments is an N-channel, and the present invention is applicable to any trench gate MOS power device such as a P-channel trench gate IGBT and a VDMOS (vertical double diffused metal oxide semiconductor).
In other embodiments, the gate oxide layer corresponding to the region above the channel region may be a thin oxide layer or a thick oxide layer, which is not limited in the present invention. A thick oxide layer is formed for the gate oxide layer corresponding to the region above the channel region, and a step of etching the oxide layer and oxidizing multiple times may be added between step S4 and step S5.
In other embodiments, the channel region may be disposed on only one side of the trench, the channel region may not be disposed on the other side of the trench, and the gate oxide layer on the side where the channel region is not disposed may be a thick oxide layer entirely.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the various features mentioned in the various embodiments may be combined in any combination as long as there is no logical or structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a grid of a groove grid MOS power device is characterized by comprising the following steps:
step S1: forming a channel region and a groove;
step S2: performing primary oxidation to form a thick oxide layer in the groove;
step S3: removing the unnecessary thick oxide layer;
step S4: performing secondary oxidation to form a thin oxide layer above the thick oxide layer;
step S5: a gate body is formed.
2. The method of claim 1, wherein in step S3, the final etching position of the thick oxide layer is controlled by using a photoresist as a mask.
3. The method of claim 2, wherein in step S2, the thick oxide layer is formed on top of a bulk material;
the step S3 includes the following steps:
step S301: filling the photoresist in the groove, and arranging the photoresist on the upper surface of the thick oxide layer;
step S302: exposing the photoresist and controlling the exposure depth of the photoresist;
step S303: removing the exposed photoresist;
step S304: etching the thick oxide layer by using the residual photoresist as a mask;
step S305: and removing the residual photoresist in the groove.
4. A gate manufacturing method according to claim 3, wherein in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the channel region.
5. A gate manufacturing method according to claim 3, wherein a carrier injection region is further formed in the step S1, and a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the carrier injection region in the step S302.
6. The method for manufacturing a gate according to any one of claims 3 to 5, wherein in the step S304, the thick oxide layer is etched by over-etching.
7. The gate manufacturing method according to any of claim 6, wherein in the step S304, the over-etching amount of the thick oxide layer is controlled by etching time.
8. The method for fabricating a gate electrode according to any of claims 1-5, wherein in step S5, polysilicon is deposited in the trench and on the upper surface of the gate oxide layer, the trench is filled with polysilicon, and then the polysilicon is etched such that the upper surface of the polysilicon is lower than the upper surface of the thin oxide layer.
9. The trench gate MOS power device manufactured by the gate manufacturing method of any one of claims 1 to 8, wherein the trench gate MOS power device comprises a channel region, a gate oxide layer corresponding to the channel region is a thin oxide layer, and a gate oxide layer below the thin oxide layer is a thick oxide layer.
10. The trench-gate MOS power device of claim 9, wherein a carrier injection region is disposed below the channel region and is immediately adjacent to the channel region, and a gate oxide layer corresponding to the carrier injection region is the thin oxide layer.
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