JP2008270606A - Mosfet semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MOSFET semiconductor device including a trench gate structure, capable of reducing ON resistance and improving destruction resistance characteristics, and a manufacturing method thereof. <P>SOLUTION: An MOSFET type semiconductor device includes a semiconductor substrate of a first conductive type, an epitaxial layer of the first conductive type, a first semiconductor region of a second conductive type and a second semiconductor region of the first conductive type formed in the epitaxial layer, and a trench formed from a surface of the epitaxial layer through the second semiconductor region and the first semiconductor region. In the inside of the trench, a trench lower portion insulating film is formed thicker than a surface gate oxide film in the first semiconductor region. In a trench lower portion, the trench lower portion insulating film, a polysilicon film, a thermal oxide film and a gate electrode are sequentially laminated on the epitaxial layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a MOSFET type semiconductor device having a trench gate structure and a method for manufacturing the same, and more particularly to a semiconductor device with low power consumption and high withstand voltage and a method for manufacturing the same.

  2. Description of the Related Art A power MOSFET type semiconductor device having a trench gate structure has been developed as a semiconductor device that switches a high voltage and large current of a current number A to 100A at a voltage of 20V to 600V.

FIG. 7 shows a main example of a power MOSFET type semiconductor device having a conventional trench gate structure. 7 includes an n-type semiconductor substrate 1 including a drain region, an n ⁻ -type semiconductor layer 2 formed by epitaxial growth on the n-type semiconductor substrate 1, a channel provided in the n ⁻ -type semiconductor layer 2. A p-type semiconductor region 3 including a region, an n-type semiconductor region 4 provided in the p-type semiconductor region 3 and serving as a source region, and an n ⁻ -type semiconductor layer penetrating the n-type semiconductor region 4 and the p-type semiconductor region 3 2, a gate electrode 12 provided in a trench 5 formed through a gate oxide film 11 made of a thermal oxide film, and a source electrode 14 provided on the gate electrode 12 through an insulating film 13. Have. In addition, it has a drain electrode (not shown) connected to the n-type semiconductor substrate 1.

  Recently, with respect to power MOSFET type semiconductor devices having such a trench gate structure, there has been an increasing demand for low on-resistance, high-speed switching, and high reliability accompanying the demand for low power consumption. High breakdown resistance is demanded, and each company is proceeding with miniaturization and structural optimization of power MOSFET type semiconductor devices having a trench gate structure.

  In Patent Documents 1-3, as a power MOSFET type semiconductor device having a trench gate structure capable of reducing on-resistance while ensuring a withstand voltage, an insulating film on a trench side wall below a trench in the trench groove is insulated. Disclosed is a power MOSFET type semiconductor device having a structure formed thicker than a gate insulating film on a trench sidewall on an upper part of a trench disposed continuously with the film. FIG. 8 shows an example of the structure and manufacturing method of such a semiconductor device.

The power MOSFET type semiconductor device of FIG. 8D is formed by epitaxial growth on the n type semiconductor substrate 1 including the drain region and the n type semiconductor substrate 1 in the same manner as the main example of the conventional power MOSFET type semiconductor device of FIG. -type semiconductor layer 2, n ^{- -} formed n a p-type semiconductor region 3 including the channel region provided in type semiconductor layer 2, an n-type semiconductor region 4 to be provided on the p-type semiconductor region 3 a source region The trench 5 is formed so as to penetrate the n-type semiconductor region 4 and the p-type semiconductor region 3 and reach the n ⁻ -type semiconductor layer 2.

In the semiconductor device manufacturing method of FIG. 8, after forming the first thermal oxide film 6 in the trench 5, a TEOS (tetraethylorthosilicate) film 7 having a thickness of about 0.2 to 0.3 μm is formed by CVD. Is provided. A resist is applied to the surface of the TEOS film 7, and the resist 10 is formed by exposure and development so that the upper surface of the resist 10 is located below the lower surface of the p-type semiconductor region 3 serving as a channel region (FIG. 8A). ). Using the resist 10 as a mask, the TEOS film 7 and the first thermal oxide film 6 are removed by etching (FIG. 8B). A gate oxide film 11 is formed by thermal oxidation (FIG. 8C). A power MOSFET type semiconductor device having the trench gate structure of FIG. 8 is formed by forming the gate electrode 12 and the source electrode 14 on the gate electrode 12 via the insulating film 13 (FIG. 8D).
Japanese Patent Laid-Open No. 4-22962 US Pat. No. 6,528,355 German Published Patent No. 102004057791A1

In the conventional power MOSFET type semiconductor device having a trench gate structure as shown in FIG. 7, 20 to 80% of the entire on-resistance is occupied by the n ⁻ type semiconductor layer 2 formed by epitaxial growth. When the impurity concentration of the n ⁻ type semiconductor layer 2 is increased in order to reduce the overall on-resistance, the electric field strength at the lower part of the trench including the bottom of the trench is increased, and the gate breakdown resistance is lowered. There is a trade-off relationship between the on-resistance and the breakdown tolerance, and this solution has been a problem for improving the characteristics of the power MOSFET type semiconductor device having a trench gate structure.

  On the other hand, in the conventional power MOSFET type semiconductor device shown in FIG. 8D having a trench gate structure in which the insulating film below the trench is formed thicker than the gate oxide film above the trench for the purpose of improving the breakdown tolerance, In forming the insulating film, there is a problem that the etching process cannot be performed accurately and stably because the adhesion between the resist 10 and the TEOS film 7 in contact with the resist is insufficient. Further, if the cell pitch is reduced in order to increase the integration density of the trench cells and reduce the on-resistance, it becomes difficult to secure a sufficient thickness of the TEOS film 7, and the insulation film thickness below the trenches becomes difficult. Therefore, there is a problem in that it is not possible to improve the breakdown tolerance.

  Further, in a power MOSFET type semiconductor device having a trench gate structure, polysilicon serving as a gate electrode is provided in the trench through an insulating film. In order to connect this polysilicon to the surface extraction electrode, this polysilicon is used. Must be pulled up to the surface of the semiconductor device through the upper corner of the trench. However, although the upper corner portion has an acute shape, the insulating film in the upper corner portion is formed of only a thin oxide film formed at the same time as the gate oxide film 11 of 25 to 70 nm. The solution was a problem.

  The present invention eliminates the above problems by forming an insulating film under the trench with high accuracy and stability and forming a field plate structure, thereby reducing the on-resistance and improving the breakdown withstand characteristics in a balanced manner. An object of the present invention is to provide a MOSFET type semiconductor device having a possible trench gate structure and a method of manufacturing the same.

  Further, the present invention eliminates the above problems by extending the insulating film under the trench at the corner of the polysilicon pull-up portion that becomes the gate electrode for connection with the surface lead electrode, thereby raising the corner of the pull-up portion. An object of the present invention is to provide a MOSFET type semiconductor device having a trench gate structure with improved breakdown resistance of the portion and a method for manufacturing the same.

  A MOSFET type semiconductor device having a trench gate structure according to the present invention is formed on a first conductive type semiconductor substrate, a first conductive type epitaxial layer formed on a main surface of the semiconductor substrate, and the epitaxial layer. A first conductivity type second semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; and at least the second semiconductor region and the first semiconductor region from a surface of the epitaxial layer A trench formed in the trench, a gate oxide film on the surface in the trench, and a polysilicon layer serving as a gate electrode, and the trench in the first semiconductor region including the channel region inside the trench A gate oxide film formed on the inner surface of the trench lower insulating film formed continuously with the gate oxide film below the trench. In the MOSFET type semiconductor device, the trench lower insulating film, the polysilicon film, and the thermal oxide film formed by thermally oxidizing the polysilicon film are provided between the epitaxial layer and the gate electrode at the lower part of the trench. It is characterized by that.

A MOSFET type semiconductor device having a trench gate structure according to the present invention,
The trench lower insulating film, the polysilicon film, and the polysilicon film are thermally oxidized on the gate oxide film at the corner of the raised portion on the surface of the semiconductor region of the polysilicon layer that becomes the gate electrode in the trench. It may be characterized by having a thermal oxide film formed.

  According to the method of manufacturing a MOSFET type semiconductor device having a trench gate structure of the present invention, the second conductive type first semiconductor region is formed on the surface of the first conductive type epitaxial layer formed on the surface of the first conductive type semiconductor substrate. Forming a second semiconductor region of the first conductivity type on the surface of the first semiconductor region, and forming an epitaxial layer that penetrates the second semiconductor region and the first semiconductor region and exists below the first semiconductor region. A step of forming a trench reaching, a step of forming a first thermal oxide film on a surface of the semiconductor region including the inside of the trench, a step of forming an insulating film on the first thermal oxide film, Forming a polysilicon film; and at least registering the polysilicon film in the trench so as to cover at least the lower surface of the first semiconductor region serving as a channel. Etching the polysilicon film using the resist as a mask, exposing the insulating film, etching the insulating film and the first thermal oxide film using the polysilicon film as a mask, A step of exposing the first semiconductor region and the second semiconductor region, and after removing the resist, a gate oxide film and a polysilicon film are formed on the surface in the trench of the first semiconductor region to be a channel by thermal oxidation Forming a second thermal oxide film on the surface of the trench simultaneously and forming a polysilicon layer serving as a gate electrode in the trench, and forming the epitaxial layer and the gate electrode below the trench. The first thermal oxide film, the insulating film, the polysilicon film, and the second thermal oxide film are formed between the polysilicon layers. And butterflies.

  In the method of manufacturing a MOSFET type semiconductor device having a trench gate structure according to the present invention, the polysilicon film is covered at the corner portion of the polysilicon layer that becomes the gate electrode in the trench on the surface of the semiconductor region. After forming the resist, leaving the polysilicon film, the insulating film, and the first thermal oxide film, forming a second thermal oxide film on the surface of the polysilicon film, and then forming the second thermal oxide film on the second thermal oxide film. A portion for pulling up the polysilicon layer serving as the gate electrode to the semiconductor surface may be formed.

  According to the present invention, the etching of the thick insulating film in the trench (for example, the thermal oxide film and the TEOS film) is performed using the polysilicon film having good adhesion to the TEOS film as a mask, so that the etching accuracy is improved and the controllability is improved. There is an advantage that it is possible to provide a semiconductor device with good reliability and a manufacturing method thereof.

  According to the present invention, the polysilicon film is sandwiched between the gate electrode and the semiconductor region at the bottom of the trench, and a so-called multiple field plate structure is formed by capacitive coupling between the gate electrode, the mask polysilicon film, and the semiconductor region. Therefore, there is an advantage that a large electric field relaxation effect can be obtained at the lower part of the trench.

  In addition, according to the present invention, by adopting a so-called multiple field plate structure, it is possible to achieve a reduction in on-resistance and an improvement in breakdown resistance characteristics, so that on-resistance is low and low power consumption is high. There is an advantage that a semiconductor device having a high withstand voltage and high reliability and a manufacturing method thereof can be provided.

  Further, by adopting a so-called multiple field plate structure, the insulating film under the trench can be made thin, so that the degree of integration can be improved, and the semiconductor device can be downsized by reducing the on-resistance. is there.

  In addition, the gate electrode polysilicon can be formed without adding a special process in the process of manufacturing a so-called multiple field plate structure from the cell part of the polysilicon for the gate electrode to the upper corner of the pulling part on the semiconductor surface. Since the thick insulating film under the trench can be formed under the trench, the electric field at the corner of the pulling portion can be relaxed, and the breakdown resistance of the semiconductor device can be improved. is there.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.

  FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2, 3 and 4 are explanatory diagrams for explaining a method of manufacturing the semiconductor device of FIG. 1 according to an embodiment of the present invention. It is. FIG. 5 is a schematic plan view showing the semiconductor device according to the embodiment of the present invention as viewed from above, and shows a cross section of the semiconductor device according to the embodiment of FIG.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. The semiconductor device according to the embodiment of the present invention includes an n-type semiconductor substrate 1 including a drain region, an n ⁻ -type semiconductor layer 2 formed by epitaxial growth on the n-type semiconductor substrate 1, and ions in the n ⁻ -type semiconductor layer 2. A p-type semiconductor region 3 (corresponding to a first semiconductor region) formed by implantation and including a channel region, and an n-type semiconductor region 4 (second semiconductor) formed by ion implantation in the p-type semiconductor region 3 and serving as a source region Corresponding to the area). The semiconductor device according to the present invention has a trench 5 that penetrates the n-type semiconductor region 4 and the p-type semiconductor region 3 and reaches the n ⁻ -type semiconductor layer 2 below the p-type semiconductor region 3.

  A gate oxide film 11 formed by thermal oxidation is provided on the side wall of the p-type semiconductor region 3 constituting the channel above the trench 5. Under the trench 5, there is a trench lower insulating film 15 disposed continuously with the gate oxide film 11. When the gate oxide film 11 and the trench lower insulating film 15 are relatively compared, the trench lower insulating film 15 is formed thicker than the gate oxide film 11.

The trench lower insulating film 15 includes a first thermal oxide film 6 formed on the n ⁻ type semiconductor layer 2 and a TEOS film 7 formed on the first thermal oxide film 6 by the CVD method. The Here, as described in the following method for manufacturing a semiconductor device of the present invention, another type of insulating film suitable for the present invention may be used in place of the TEOS film 7.

  The semiconductor device according to the present invention has a gate electrode 12 formed of polysilicon doped with impurities on the gate oxide film 11 and the second thermal oxide film 16 inside the trench 5, and on the gate electrode 12. A source electrode 14 is provided through an insulator 13.

Under the trench of the semiconductor device according to the present invention, on the n ⁻ type semiconductor layer 2, the trench lower insulating film 15, the polysilicon film 8, the second thermal oxide film 16 formed on the surface of the polysilicon film 8, the gate The electrodes 12 are sequentially stacked. As a result, the polysilicon film 8 is sandwiched between the gate electrode 12 and the n ⁻ type semiconductor layer 2 below the trench, and the capacitive coupling between the gate electrode 12, the polysilicon film 8 and the n ⁻ type semiconductor layer 2 is performed. Since a so-called multiple field plate structure is formed, a large electric field relaxation effect can be obtained under the trench.

Next, an embodiment of the method for manufacturing the semiconductor device of FIG. 1 according to the present invention will be described with reference to FIGS. First, a p-type semiconductor region 3 to be a channel region is formed by ion implantation in an n ⁻ -type semiconductor layer 2 formed by epitaxial growth on the n-type semiconductor substrate 1, and a source region is formed in the p-type semiconductor region 3. An n-type semiconductor region 4 is formed (FIG. 2A). Here, a region in which the p-type semiconductor region 3 and the n-type semiconductor region 4 are not formed in the n-type semiconductor substrate 1 and the n ⁻ -type semiconductor layer 2 constitutes a drain region.

Next, a trench 5 having a depth of 2 to 4 μm is formed by etching to penetrate the n-type semiconductor region 4 serving as the source region and the p-type semiconductor region 3 serving as the channel region to reach the n ⁻ -type semiconductor layer 2 serving as the drain region. (FIG. 2 (b)).

  Next, a first thermal oxide film 6 of 25 to 70 nm is formed on the entire surface of the semiconductor region in a water vapor atmosphere at about 950 ° C. (FIG. 2C).

  Next, a TEOS film 7 having a thickness of about 0.2 to 0.3 μm is formed on the entire surface of the first thermal oxide film 6 by the CVD method. The first thermal oxide film 6 and the TEOS film 7 constitute a thick oxide film under the trench. In the present invention, the TEOS film 7 is preferably formed to have a film thickness 3 to 10 times that of the first thermal oxide film 6. In the embodiment of the present invention, a mode using a TEOS film will be described as an example. However, the present invention is not limited to a TEOS film, and an NSG (Non Doped Silicate Glass) film formed using silane gas may be used, which is suitable for the present invention. If so, other types of insulating films may be used (FIG. 2D).

  Next, a polysilicon film 8 having a thickness of 50 to 200 nm is formed on the entire surface of the TEOS film 7 by CVD (FIG. 3A).

  Next, a resist is applied to the surface of the polysilicon film 8, and a resist 10 is formed in the trench 5 by exposure and development. At this time, by adjusting the exposure amount, the resist 10 is formed so that the upper surface of the resist 10 is located below the lower surface of the p-type semiconductor region 3 (FIG. 3B).

  Next, the polysilicon film 8 is etched by an isotropic dry etching method using the resist 10 as a mask. (Fig. 3 (c))

  Next, using the etched polysilicon film 8 as a mask, the first thermal oxide film 6 and the TEOS film 7 are wet-etched with a hydrofluoric acid-based etchant. Since the adhesion between the polysilicon film 8 and the TEOS film 7 is superior to the adhesion between the resist 10 and the TEOS film 7, the etching process can be performed more stably than when the resist 10 is used as a mask. It can be etched well (FIG. 3D).

  Next, the resist 10 in the trench 5 is removed. Then, thermal oxidation is performed in a steam atmosphere at about 950 ° C. to form a gate oxide film 11 having a thickness of 25 to 70 nm on the sidewall of the trench 5. At this time, the surface of the polysilicon film 8 is also thermally oxidized, and a second thermal oxide film 16 is formed on the surface of the polysilicon film 8 continuously with the gate oxide film 11. The second thermal oxide film 16 on the surface of the polysilicon film 8 is preferably formed to a thickness of 50 to 200 nm (FIG. 4A).

  Next, polysilicon to be a gate electrode is grown on the entire surface. At this time, this polysilicon is formed as phosphorus-doped polysilicon or by doping phosphorus as an impurity into non-doped polysilicon (FIG. 4B).

  Next, the etching time is controlled to etch back the polysilicon so that the polysilicon end face is located below the silicon surface, thereby forming the gate electrode 12 (FIG. 4C).

  Next, an insulating film 13 is formed on the gate electrode 12 (FIG. 4D).

  Next, the source electrode 14 is formed through the insulating film 13 to form the semiconductor device according to the present invention shown in FIG.

A first thermal oxide film 6, a TEOS film 7, a polysilicon film 8, a second thermal oxide film 16 are formed on the n ⁻ type semiconductor layer 2 below the trench of the semiconductor device manufactured by the manufacturing method according to the present invention. The gate electrode 12 is formed by sequentially stacking. As a result, the polysilicon film is sandwiched between the gate electrode 12 and the n ⁻ type semiconductor layer 2 at the bottom of the trench, and so-called due to capacitive coupling between the gate electrode 12, the polysilicon film 8 and the n ⁻ type semiconductor layer 2. Since a multi-field plate structure is formed, a large electric field relaxation effect can be obtained at the lower portion of the trench.

  As described above, according to the present invention, a reduction in on-resistance and an improvement in breakdown resistance characteristics can be achieved in a coordinated manner, and a semiconductor device having low on-resistance, low power consumption and excellent reliability, and a method for manufacturing the same. Can be provided.

  In order to connect the gate electrode 12 of the semiconductor device according to the embodiment of the present invention to the semiconductor surface extraction electrode, the structure of the raised portion corner portion may be described below, and the structure and manufacturing method of the raised portion corner portion will be described. .

  FIG. 5 is a schematic plan view showing the semiconductor device according to the embodiment of the present invention as viewed from above, and FIG. 6 is a semiconductor device according to the embodiment of the present invention shown by a cross section BB in FIG. It is explanatory drawing explaining the manufacturing method of the raising part corner part on the semiconductor surface of the gate electrode 12 of FIG.

  FIG. 6D is a cross-sectional view showing a portion where the gate electrode 12 according to the present invention is pulled up onto the semiconductor surface. A trench lower insulating film 15 (first thermal oxide film 6 and TEOS film 7), a polysilicon film 8, and a polysilicon film 8 are formed under the raised portion of the gate electrode 12 on the semiconductor surface as in the trench lower part of the trench cell. A second thermal oxide film 16 formed simultaneously with the gate oxide film 11 is formed by thermal oxidation. Since the trench lower insulating film 15 is formed under the gate electrode 12, the dielectric strength of the raised corner portion of the polysilicon for the gate electrode on the semiconductor surface can be improved.

  Next, with reference to FIG. 6, the manufacturing method of the raising part corner part on the semiconductor surface of the polysilicon for gate electrodes is demonstrated. A pull-up portion corner provided on the outermost periphery of the transistor cell is formed wider than the cell portion on the inside. The first thermal oxide film 6, the TEOS film 7, and the polysilicon film 8 are sequentially stacked, and a resist 10 is formed by a photomask so that the resist remains at the corner (FIG. 6A). This step is performed simultaneously with the step of FIG.

  After removing the resist 10, in the same process (corresponding to FIG. 4A) as forming the second thermal oxide film 16 simultaneously with the gate oxide film 11 by thermally oxidizing the polysilicon film 8 in the trench cell, Also in the corner portion, the polysilicon film 8 is thermally oxidized to form a laminated structure of the thick film insulating film 15, the polysilicon film 8, and the second thermal oxide film 16 (FIG. 6B).

  Through the photomask process, simultaneously with the formation of polysilicon for the gate electrode, a raised corner portion on the semiconductor surface of the gate electrode is formed (FIG. 6C).

  Along with the cell source and gate contact formation, a contact hole 17 is formed in the insulating film 13 covering the polysilicon for the gate electrode, and the gate electrode 12 and the aluminum electrode (not shown) are connected via the contact hole 17. Then, the raised corner portion of the gate electrode 12 on the semiconductor surface is connected to the outside (FIG. 6D).

  In the manufacturing process for forming the multi-field plate structure of the present invention, a laminated structure of the trench lower insulating film 15, the polysilicon film 8, and the second thermal oxide film 16 is formed under the gate electrode 12. Thus, since the trench lower insulating film 15 is formed under the gate electrode 12 without adding a special process to the manufacturing process of the semiconductor device, the corner of the raised portion on the semiconductor surface of the gate electrode can be formed by a simple method. Insulation resistance can be improved.

  Although the embodiment in which the present invention is configured by an n-type semiconductor substrate has been described above, the present invention can be implemented even if the n-type element and the p-type element described above are interchanged using a p-type semiconductor substrate. Is possible.

It is sectional drawing which shows the semiconductor device which concerns on embodiment of this invention. It is explanatory drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention of FIG. It is explanatory drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention of FIG. It is explanatory drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention of FIG. It is a schematic plan view which shows the state which looked at the semiconductor device which concerns on embodiment of this invention from the top. It is explanatory drawing explaining the manufacturing method of the raising part corner part on the semiconductor surface of the polysilicon for gate electrodes of the semiconductor device which concerns on embodiment of this invention shown by the cross section BB of FIG. It is sectional drawing which shows the main example of the power MOSFET type semiconductor device which has the conventional trench gate structure. It is explanatory drawing explaining the power MOSFET type semiconductor device which has the conventional trench gate structure which improved the withstand voltage, and its manufacturing method.

Explanation of symbols

1: n-type semiconductor substrate, 2: n ⁻ type semiconductor layer, 3: p-type semiconductor region, 4: n-type semiconductor region, 5: trench, 6: first thermal oxide film, 7: TEOS film, 8: polysilicon Film: 9: p ⁺ diffusion region, 10: resist, 11: gate oxide film, 12: gate electrode, 13: insulating film, 14: source electrode, 15: trench lower insulating film, 16: second thermal oxide film, 17 : Contact hole

Claims (4)

A MOSFET type semiconductor device having a trench gate structure,
A first conductivity type semiconductor substrate;
An epitaxial layer of a first conductivity type formed on the main surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type formed on the epitaxial layer;
A second semiconductor region of a first conductivity type formed on the first semiconductor region;
A trench formed through at least the second semiconductor region and the first semiconductor region from the surface of the epitaxial layer, a gate oxide film on the surface in the trench, and a polysilicon layer serving as a gate electrode,
A trench in which a gate oxide film formed on a surface of the first semiconductor region including a channel region inside the trench is continuously disposed with the gate oxide film below the trench. In the MOSFET type semiconductor device thinner than the lower insulating film,
A trench gate structure having a trench lower insulating film, a polysilicon film, and a thermal oxide film formed by thermally oxidizing the polysilicon film between the epitaxial layer and the gate electrode at the lower part of the trench MOSFET type semiconductor device having   The trench lower insulating film, the polysilicon film, and the polysilicon film are thermally oxidized on the gate oxide film at the corner of the raised portion on the surface of the semiconductor region of the polysilicon layer that becomes the gate electrode in the trench. 2. The MOSFET type semiconductor device having a trench gate structure according to claim 1, comprising a thermal oxide film formed. A method for manufacturing a MOSFET type semiconductor device having a trench gate structure,
A second conductivity type first semiconductor region is formed on the surface of the first conductivity type epitaxial layer formed on the surface of the first conductivity type semiconductor substrate, and the first conductivity type second semiconductor is formed on the surface of the first semiconductor region. Forming a region;
Forming a trench that penetrates the second semiconductor region and the first semiconductor region and reaches an epitaxial layer that exists under the first semiconductor region;
Forming a first thermal oxide film on the surface of the semiconductor region including the inside of the trench;
Forming an insulating film on the first thermal oxide film;
Forming a polysilicon film on the insulating film;
Forming a resist in the trench so as to cover at least the polysilicon film located below the lower surface of the first semiconductor region serving as a channel;
Etching the polysilicon film using the resist as a mask to expose the insulating film;
Etching the insulating film and the first thermal oxide film using the polysilicon film as a mask to expose the first semiconductor region and the second semiconductor region;
Forming a gate oxide film on the surface of the trench in the first semiconductor region to be a channel and a second thermal oxide film on the surface of the polysilicon film by thermal oxidation after removing the resist;
Forming a polysilicon layer to be a gate electrode in the trench,
The first thermal oxide film, the insulating film, the polysilicon film, and the second thermal oxide film are formed below the trench between the epitaxial layer and the polysilicon layer that becomes the gate electrode. A method of manufacturing a MOSFET type semiconductor device having a trench gate structure.   The resist is formed so as to cover the polysilicon film at the corner of the raised portion on the surface of the semiconductor region of the polysilicon layer serving as the gate electrode in the trench, and the polysilicon film, the insulating film, and the first 1 After leaving a thermal oxide film, a second thermal oxide film is formed on the surface of the polysilicon film, and then a portion for raising the polysilicon layer to be a gate electrode to the semiconductor surface is formed on the second thermal oxide film. The method for manufacturing a MOSFET type semiconductor device having a trench gate structure according to claim 3.

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