JP2003509836A - Trench semiconductor device with gate oxide layer having multiple thicknesses and method of manufacturing the same - Google Patents

Abstract

In trench semiconductor devices such as power MOSFETs, large electric fields at the corners of trench (250) are reduced by increasing the thickness of gate oxide layer (244) at the bottom of trench (250). You. Several processes for manufacturing such devices are disclosed. In one group of processes, a directional deposition of silicon oxide (272) is performed after the trench (268) is etched, forming a thick oxide layer (270) at the bottom of the trench (268). The oxide deposited on the walls of the trench (268) is removed before a thin gate oxide layer (276) is grown on the walls. Subsequently, the trench (268) is filled with polysilicon (278) in one or two stages. In a process variation, a small amount of photoresist is deposited on the oxide (270) at the bottom of the trench (268) before etching the walls of the trench (268). Alternatively, after the polysilicon (320) is deposited in the trench (268), it may be etched back until only a portion (322) remains at the bottom of the trench (268). Subsequently, the polysilicon (320) is oxidized and the trench (268) is filled with polysilicon. These processes can be combined, with directional deposition of oxide followed by polysilicon filling and oxidation. The method of forming the "keyhole" type gate electrode (634) includes a step of depositing polysilicon at the bottom of the trench (606), a step of oxidizing the upper surface of the polysilicon, and a step of etching the oxidized polysilicon. Filling the trench 606 with polysilicon.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to semiconductor devices having gate electrodes buried in trenches, and more particularly to gate oxide layers when such devices are exposed to large voltage differentials during the off state. The present invention relates to a structure and a method for protecting an element against damage of the element. The invention particularly relates to trench MOSFETs.

BACKGROUND ART There is a type of semiconductor device in which a gate electrode is formed in a trench extending from the surface of a semiconductor chip. One example is a trench gate MOSFET, and other examples are an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET) and an integrated mode field effect transistor (ACC).
UFET). All of these devices may for some reason be exposed to a strong electric field at the bottom of the trench, or may be formed at the bottom of the trench with a parasitic capacitor containing the gate electrode and the semiconductor material surrounding the trench. That is, the trench structure has common characteristics.

1 to 10 show cross-sectional views and characteristics of known trench gate devices. FIG. 1 illustrates a trench gate MOSFET 100 having an upper metal layer 102, a gate 104 formed in a trench 106 and separated from an epitaxial silicon layer 108 by a gate oxide layer 110. MOSFET 100 also has an N + source region 112 and a P- body 114. The drain of MOSFET 100 has epi layer 108 and N + substrate 116. A deep P + region 118 is formed below the P-body 114, which is shown by Bulucea et al. In US Pat. No. 5,072,266. The PN junction between the deep P + region 118 and the Nepi layer 108 forms a voltage clamp diode 117 such that a normal avalanche occurs. The P + body contact region 119 provides a contact between the metal layer 102 and the P− body 114. A gate 104, typically formed of polysilicon, is overlying the gate 104 and is protected from the metal layer 102 by an oxide layer 120, which is typically patterned by a contact mask with features that do not correspond to the trench itself.

As shown, the gate oxide layer 110 comprises a uniform thin layer of oxide along the three sides of the polysilicon gate 104. That is, the portion of the gate oxide layer 110 on the sidewalls of the trench and the curved or straight portion of the gate oxide layer 110 at the bottom of the trench (are subject to stress-related changes and etching found at the bottom of the trench). 15 (excluding associated oxide thickness variations)
It has a uniform thickness in the range of 0Å to 1200Å.

There are many variations in such a general type MOSFET. For example, in FIG. 2 it is generally similar to MOSFET 100 but with a deep P + region 11
MOSFET 130 not including 8 is shown. The gate of MOSFET 130 projects slightly into P-body 132 because the depth of P-body 132 and the depth of trench 134 are determined by two unrelated processes. In such a vertical device, the amount of net overlap of the polysilicon gate with the drain region is not guaranteed. It is known that such variations affect the operation of the device and can also affect its reliability. Also, in FIG. 2, there is no additional diode formed by the deep P + region 118 to clamp the voltage, so breakdown will always occur if the voltage rises to a level where the device goes to an avalanche. obtain.

The MOSFET 140 shown in FIG. 3 is a variation of the MOSFETs 100 and 130, where the MOSFET cell 142 does not include a deep P + region,
The diode cells 144, including the deep P + regions, are distributed in the array at regular intervals,
It acts as a voltage clamp and limits the strength of the electric field in the MOSFET cell. MO
The gate oxide layer is of uniform thickness in SFET 140.

4A-4G depict various aspects of the breakdown phenomenon. FIG. 4A represents the field strength profile at breakdown in a trench gate device having a relatively thick gate oxide layer. Device 150 is effectively a gate diode, which is a structural element in most trench gate vertical power MOSFETs. As shown, the strongest electric field where impact ionization occurs during the avalanche breakdown is located at the junction just below the P + body region.
In contrast, the device 160 shown in Figure 4B has a relatively thin gate oxide layer. The strongest electric field level is now located near the corner of the trench, since some ionization is caused below the P + region. The breakdown mechanism due to the field plate increases the electric field strength.

4C and 4D represent the ionization profile of each element 150 and 160 as it goes to the avalanche breakdown. In the presence of a thick oxide layer as in FIG. 4C or a thin oxide layer as in FIG. 4D, the device must conduct large currents as an avalanche phenomenon, ie in a “deep” avalanche,
Breakdown begins to occur at the corners of the trench. Even in the case of thick oxide layers (FIG. 4C), where the peak electric field is not at the corners of the trench (FIG. 4C), ionization eventually occurs at the corners of the trench as the drain voltage increases. However, there are more contours in FIG. 4D, which means a higher ionization rate when the gate oxide layer is thin.

FIG. 4E shows that on the right hand side, when a diode clamp including a deep P + region is provided, the diode breaks down at a lower voltage and avalanche breakdown cannot occur at the corner of the trench. It is shown that.
If the resistance of the current path through the diode is low enough, the diode will clamp the maximum voltage of the device. As a result, the voltage does not rise to a level where avalanche breakdown occurs near the corners of the trench.

FIG. 4F is a graph showing breakdown voltage (B _V ) as a function of gate oxide thickness (X _OX ) for 20 V and 30 V devices. 30 volt device epitaxial
The layer is lightly doped. A 30V device would ideally have an avalanche yield point of approximately 38 volts. At 20 volts, the epi would be more heavily doped, ideally with an avalanche yield point of approximately 26 volts. If the thickness of the gate oxide layer is reduced from 1,000Å to several 100Å,
Basically, the breakdown voltage is relatively constant, and the breakdown voltage rises rather because the shape of the field plate of the gate acts to relax the electric field. At thicknesses less than a few Å, breakdown voltage breakdown begins to occur.

FIG. 4G is a schematic diagram of the device shown in FIGS. 4A-4D, with a gate diode in parallel with the MOSFET and a diode voltage clamp connected in parallel with both the MOSFET and the gate diode. Indicates. This configuration is designed so that the diode clamp breaks down first. The gate diode does not avalanche prior to the diode clamp. This becomes more difficult as the gate oxide becomes thinner.

FIGS. 5A, B show ionization profiles for element 170 with sharp trench corners and element 172 with rounded trench corners.
FIG. 5B shows that rounded trenches reduce the degree of ionization, but still drive the device deep enough for breakdown, causing breakdown at the trench corners and putting the device at risk. . 6A to 6C show electric field strength contours, equipotential lines, and electric force lines in the MOSFET 180, respectively. The gate of MOSFET 180 is connected to the source and body and is grounded, and the drain is biased to V _D.
From FIG. 6B, it is clear that the drain voltage V _D is divided and distributed over the entire region. On the other side of FIG. 6B, the equipotential lines are biased to one side, especially around the corners of the trench. This is shown in Figure 6C.
As shown in, electric force lines perpendicular to the equipotential lines are generated. This would make it clear that a strong electric field is generated at the trench corners and rounding does not solve this problem. Electrodes with small surface area, ie basically a volume problem at the point where they terminate at the gate, the lines of electric force are clustered at the corners.

FIG. 6D shows that the MO is turned on by applying a positive voltage V _G to the gate.
The SFET 180 is shown. Current flows down the sidewalls of the trench and at the same time spreads along the bottom of the trench and at an angle from the sides of the trench to the region below the mesa. However, in this process, the current flow is shown in FIG.
Flows through a region with a strong electric field, as indicated by the electric field contour of When a large current flows in a part with a strong electric field (that is, when the device is saturated)
The current carrier collides with the atom in the epi layer and repels another carrier by the transfer of momentum. This creates new electron-hole pairs, which are accelerated and cause further collisions, thereby ionizing another atom.

FIG. 6E shows the ionization profile when MOSFET 180 is in the on state.
The ionization profile shown in FIG. 6E is different than that shown in FIG. 4C, where element 150 represents the off state. The difference is that the ionization contour is raised along the sides of the trench to its upper end and also to the P-body. This has various destructive effects on the device. One effect is to generate electron-hole pairs in the vicinity of the gate oxide layer, which are easily accelerated by the strong electric field in this part. This pair can actually get trapped in the gate oxide layer and damage the gate oxide layer.

Moreover, this phenomenon defines the upper limit of the voltage that can be applied to the device. Because too many pairs occur, the region around the trench sidewalls begins to modulate the effective doping concentration of the epi layer by making it appear more heavily doped than it really is. This is because the newly generated pairs of electrons are sent into the substrate by the positive drain voltage V _D , and the holes are sent to the P body. The net effect is that the electrons and holes can only move at a certain velocity, so the local charge distribution will adjust itself so that the charge is neutral.
In particular, the region surrounding the reverse-biased junction is called the coupling region or space charge region, where there are no free charge carriers (unless impact ionization is present). The non-movable charge in this depletion region, ie the positive ions on the N-type side of the junction and the negative ions on the P-type side of the junction, are incorporated across the junction (
built-in) An electric field is formed. Unless impact ionization is present, holes that drift in the N-type region add to the positive fixed charge, enhancing the electric field and further promoting the impact ionization process. These excess holes make the epi region, which in this case consists of N-type material, more strongly doped than it actually is due to the built-in electric field. The net effect is an increase in the electric field that further degrades the breakdown. This effect is shown in the current-voltage characteristic of FIG. 6F, and the drain current _ID increases rapidly at a certain drain voltage. The drain voltage at which this occurs is the same for each of the gate voltages shown. This problem is exacerbated when the gate oxide layer becomes thinner.

[0016]   Another issue associated with trench devices is that associated with capacitance.
is there. FIG. 7A shows a gate and resistive load 194 driven by a current source 192.
FIG. 3 is a schematic diagram of a MOSFET 190 that operates. For source and drain
The connected voltage source 196 has a drain voltage V_DSo that
Voltage V_DDTo supply. As shown in FIGS. 7B-7D, time t₁At
The current source 192 starts to supply a constant current to the gate, and in FIG._GCode
The voltage on the gate to the source marked with begins to rise. However soon
Does not reach the threshold, so MOSFET 190 is still on.
Drain voltage V_DNever begins to fall. V_GReaches the threshold,
Tick t_TwoAt, MOSFET 192 saturates and turns on, conducting current. V _D Begins to fall, but at that time between the drain and gate of MOSFET 192
Causes capacitive coupling and gate voltage V_GStops ascending upwards.
V_GRemains flat until MOSFET 192 reaches its linear region
. Second, MOSFET 192 looks like an on-resistance in a voltage divider.
And At this time, the voltage across the MOSFET 192 is low and the voltage V_DDmany
Is added to resistor 194.

At this point, the effect of capacitive coupling between the gate and drain is satisfied,
V _G rises towards higher voltage. The plateau is due to the gate-drain overlap capacitance, which is similar to the Miller effect, but this is not the effect for small signals. This is the effect on large signals. At this point, the drain current I _D continues to rise, but the rate of its rise decreases as shown in FIG. 7D.

FIG. 7E shows a plot of V _G as a function of charge at gate 9D. Where Q _G is equal to the product of I _G × t, where I _G is a constant. The gate voltage rises to a certain level, becomes constant at that level, and then rises again. If there is no feedback capacitance between the drain and gate, the voltage will rise linearly, but in reality this line will eventually reach the plateau.

In FIG. 7E, V _G1 and Q _G1 correspond to a certain capacitance because C is equal to ΔQ / ΔV. This point corresponds to a larger capacitance, because more charge is needed to reach the point Q _G2 , V _G1 . So, as shown in FIG. 7F, the capacitance of the device starts from a relatively constant small value C _ISS , jumps to a higher effective value C _G (eff), and then becomes relatively constant. This effect results in the device having a larger than desirable effective capacitance during its switching changes. Therefore, unnecessarily large amount of energy is consumed to turn on the device.

As shown in FIG. 7G, the input capacitance has various components including a gate-source capacitance C _GS and a gate-body capacitance C _GB . These two capacitive components are
Neither has a function of amplifying the gate-drain capacitance. The gate-drain capacitance C _GD is shown in FIG. 7G, which is formed at the bottom and sidewalls of the trench. The equivalent circuit is shown in Figure 7H. Even though C _GD is of the same order as C _GS and C _GB , it is electrically 5 to 10 times larger. Because it is amplified during the switching process.

As mentioned above, rounding the bottom of the trench serves to prevent damage to the gate oxide layer. However, this is not a complete solution to the problem. 8A-8C illustrate a method for forming a trench having rounded corners. In FIG. 8A, small reactive ions 202 are
The silicon is etched through the openings provided in the mask 200 on the surface. The ions 202 are accelerated downward by the electric field, causing them to etch trenches with generally straight sidewalls. When the trench reaches a certain depth, the electric field is relaxed as shown in FIG. 8B. Alternatively, the chemical composition can be changed. At the end of the process, the electric field is modified to move the etching ions in various directions, as shown in FIG. 8C. This not only begins to widen the trench, but also rounds the bottom. Anisotropy is also affected by the formation of polymers as a byproduct of the trench sidewall etching process. If the chemical component is one that removes the polymer as it is formed, the etching will be more isotropic. If the polymer is left on the sidewalls, the trench will only be etched at the bottom.

9A-9D form a mask 210 as shown in FIG. 9A, etch a trench 212 as shown in FIG. 9B, and an oxide layer on the walls of the trench as shown in FIG. 9C. 214, the oxide layer can be removed and then grown again to remove the defects (by a technique called sacrificial oxidation), and the polysilicon layer 216 allows trenches to be formed as shown in FIG. 7D. fill in.

10A and 10F show a general method for forming a trench MOSFET. This process produces N on N + substrate 222 as shown in FIG. 10A.
It begins by growing the epitaxial layer 220. A polysilicon-filled trench 224 is formed in the Nepi layer 220 as shown in FIG. 10B, such as by using the method shown in FIGS. 9A-9C. The surface may or may not be flat, depending on how the surface oxide layer is formed during this process. Next, P-body 226 is introduced, but P-body 226 can also be introduced prior to forming trench 224 as shown in FIG. 10C. Although any of these processes can be applied to the actual manufacturing process, it is preferable to first form the trench because the etching process affects the doping concentration in the P-body. Next, a mask is provided on the surface and N + source regions 228 are implanted (FIG. 12). Shallow P + as an option
The region 230 is implanted into an ohmic contact or the like between the P body and the metal layer,
Then it is put on. The P + region 230 is deposited by depositing an oxide layer 232 over the entire region, as shown in FIG. 10E, and then implanting it through an opening provided by etching to form a contact mask. It is formed. The contact mask may or may not be used to define P + region 232. Finally, a metal layer 234 is deposited on the surface to contact the N + source region 228 and P + region 230 (FIG. 10F).

DISCLOSURE OF THE INVENTION According to the present invention, it is possible to have a dielectric layer separating the gate electrode from the semiconductor material surrounding the trench, such that the thickness of this dielectric layer is thicker in the region of the trench bottom. A trench gate type semiconductor device is formed. This structure is near the bottom of the trench,
In particular, it contributes to the reduction of the electric field strength at the corner or the rounded portion which is the boundary between the trench bottom and the trench side wall, and also contributes to the reduction of the electrostatic capacitance.

Several processes are used to form this structure. One process includes the following steps. First, a trench is formed in the semiconductor material by etching. Subsequently, a directional deposition of the dielectric material is performed so that the dielectric material is selectively deposited only on horizontal surfaces such as trench bottoms. This is the deposition chamber (eg,
This is done by creating an electric field in a chemical vapor deposition or sputtering chamber) so that the charged ions of the dielectric are accelerated towards the semiconductor material. The trench is filled with a conductive material forming the gate electrode. After directional deposition, any dielectric deposited on the sidewalls of the trench can be removed and a conventional dielectric layer can be grown on the sidewalls of the trench. In many processes, the dielectric material is silicon dioxide and the conductive material is polysilicon.

In one process, the conductive material is etched back to a level that is generally coplanar with the surface of the semiconductor material and a dielectric layer is deposited on the surface of the dielectric material. In one variation, the conductive material (eg, polysilicon) is oxidized to form an oxide layer, preferably after being etched back into the trench. Oxidation of the conductive material can be made to a thickness such that the oxide itself is sufficient to insulate the gate electrode, but another conductive material (eg glass) is oxidized to the conductive material. It can also be applied over.

In another variant embodiment, the deposition of the conductive material forming the gate electrode is done in two steps.

In another method, a masking material such as photoresist is applied after selective deposition of the dielectric material. This masking material is removed everywhere except the bottom of the trench, and the trench is then etched or dipped to remove the dielectric material from the sidewalls. A dielectric layer is then formed on the sidewalls of the trench.

In yet another embodiment, the directional deposition of the dielectric is followed by deposition of a material, such as polysilicon, that can be oxidized to form the dielectric, and a portion of that material. Only etch back until only the dielectric remains on the bottom of the trench. This material is then oxidized to form a thicker dielectric layer at the bottom of the trench.

In some other embodiments, there is no directional deposition of dielectric material. Instead, a material, such as polysilicon, that can be oxidized to form a dielectric is deposited and then etched back until only a portion of that material remains on the dielectric at the bottom of the trench. .

The process according to the present invention may include a process of self-aligning the trenches with contacts to the top surface of the “mesas” between the trenches. A "hard" layer of material such as silicon nitride is used as the trench mask. This hard mask remains in place until a dielectric layer is formed on the top surface of the gate electrode, preferably by oxidation of the polysilicon gate. The hard mask is then removed, exposing the entire top surface of the mesa and allowing the metal layer to make contact thereto.

The process of the present invention may use sidewall spacers near the upper corners of the trench to prevent a short circuit between the gate electrode and the semiconductor mesa. After the trench mask has been deposited and the trench-positioning openings have been formed in the trench mask, a layer of "hard" material, such as silicon nitride, and, if desired, a topcoat oxide is deposited in the trench mask openings. Isotropically deposited. "hard"
Material is deposited on the exposed edges of the trench mask. Subsequently, etching is carried out, after which the surface of the semiconductor material is exposed at the center of the opening, but the deposited dielectric remains at the side edges of the trench mask, forming sidewall spacers. The trench is subsequently etched. The dielectric sidewall spacer serves to further enhance the insulation between the subsequently formed gate electrode and the semiconductor material in the mesa.

Some other processes provide “keyhole” shaped trenches. In this trench, a thick dielectric layer extends some upwards over the sidewalls of the trench. After etching the trench, a relatively thick oxide lining is grown or deposited on the bottom and sidewalls of the trench. Fill the trench with polysilicon,
Etch back until only a portion overlies the oxide lining and remains at the bottom of the trench. The exposed oxide lining is removed from the trench sidewalls. The polysilicon is then partially oxidized by heating so that an oxide layer is formed on its exposed surface, with an oxide layer being formed on the sidewalls of the trench in the same heating process. The trench is then oxide etched to remove the oxide layer formed of polysilicon and some of the oxide layer from the sidewalls of the trench. The trench is then refilled with polysilicon to obtain the keyhole shaped gate electrode.

In a variation of the above process for forming the keyhole-shaped gate electrode, after the oxide lining is formed on the bottom and sidewalls of the trench, a predetermined amount of masking material such as photoresist is applied to the oxide lining on the trench bottom. Covered on. And then
An oxide etch is performed to remove the oxide lining from the sidewalls of the trench and the masking material is removed from the bottom of the trench. In addition, a relatively thin gate oxide layer is grown on the sidewalls of the trench and the trench is filled with a conductive material such as polysilicon forming the gate electrode.

BEST MODE FOR CARRYING OUT THE INVENTION The problems associated with the interaction between the gate and drain of a MOSFET can be partially solved by reducing the coupling capacitance between them. . In the present invention, it is done by thickening the gate oxide layer at the bottom of the trench. 11-27 show the structure and sequence of steps for forming a thick gate oxide at the bottom of the trench.

FIG. 11A shows an epitaxial (“epi”) layer 242 grown on a substrate 240. The trench 250 is formed in the epi layer 242. Gate oxide layer 244
Runs along the walls of trench 250 and is a thick portion 246 of gate oxide layer 244.
Is located under the trench 250. The trench 250 is polysilicon 248
Filled with. Note that there is no oxide layer on polysilicon 248. The arrangement of FIG. 11A may be an intermediate structure and could form a layer of oxide on polysilicon 248 at a later stage in the process. The polysilicon 248 is
It is typically doped with a high doping concentration. It may be formed with a generally flat top surface, i.e. flattened with the silicon epi surface by various means. One way to planarize the surface is to deposit a polysilicon layer to a larger thickness and then etch it back. Another way to planarize the surface is to deposit more polysilicon than is needed to fill the trench and chemically polish the surface. The flat surface is desirable to reduce the height of steps that may be formed in later manufacturing processes.

FIG. 11B shows a structure with a layer of oxide 252 on polysilicon layer 248.
Since the side edges of the oxide layer 252 do not correspond to the walls of the trench 250, the oxide layer 2
Most of 52 may be formed by masking and etching. Oxide layer 252
May be deposited (eg by chemical vapor deposition), thermally grown, or some combination thereof. FIG. 11C shows application number 09 / 296,959.
Shown is an oxide layer 254 grown according to (herein incorporated by reference). The sides of oxide layer 254 are generally aligned with the walls of trench 250, and oxide layer 254 extends down trench 250. Polysilicon layer 248 is thus buried in trench 250. The example of FIGS. 11B and 11C is
Both have a thick gate oxide region 246 at the bottom of the trench.

FIG. 12 is a schematic diagram of a number of process flows that can be used to fabricate a gate trench according to the present invention. Details of the flow of these processes are shown in Figures 13-20. FIG. 12 shows a trench is formed using a photoresist mask or a hard mask, followed by a directional oxide deposition, which is planarized by either selective etching, dipback or selective oxidation. This is shown in block diagram form. Selective oxidation can be used without directional deposition. Finally, the trench is filled with polysilicon using a one-step or two-step process.

More specifically, there are two options for trench formation starting on the left side of FIG. In one option, shown in FIGS. 13-18, the trenches are formed using a mask that is later removed, so that this mask cannot be used as a reference for other processing steps. Another option is the above-mentioned application number 09/296959.
The use of a "hard" mask to form the trenches, as described in, is also used as a reference later in the process. This option is generally described in Figures 19 and 20. After the trench is formed, a sacrificial oxide layer is typically grown on the walls of the trench and then removed. An oxide lining may then be formed on the walls of the trench. This step results in a trench with a uniform oxide layer on its walls, with or without a hard mask on top of the silicon.

The so-called directional dielectric deposition may then proceed. Directional dielectric deposition deposits more oxide at the bottom of the trench than at the sidewalls of the trench. Then there are three options. Selective etchback can be performed as shown in FIG. 16, leaving a thick oxide at the bottom of the trench and removing the oxide from the sidewalls of the trench. As shown in Figures 13-15, one method may perform a "dipback" to remove the oxide layer from the trench sidewalls. Finally, as shown in FIGS. 17A and 18, one method is to select the polysilicon layer to be formed at the bottom of the trench and then oxidized to form additional oxide at the bottom of the trench. Oxidation can be carried out. Selective oxidation of the polysilicon layer can be performed in addition to or instead of directional dielectric deposition.

At this stage of the process, a trench with a thick oxide layer underneath is formed. The top surface of the semiconductor may or may not have a "hard" mask. Next, a thin oxide layer is grown on the walls of the trench, filling the trench with polysilicon. The polysilicon may be deposited in a single layer structure or it may be deposited in two layers with etchback between depositions. Deposition of polysilicon in a two-step process introduces dopants into the "mesas" between the trenches, resulting in a lighter doped polysilicon layer on the surface of the wafer, diode, resistance. And may be beneficial in forming other polysilicon devices.

[0042]   Finally, a glass layer is applied and contact openings are formed in the glass layer.

13A-13N represent a process using the oxide “dipback” method. The process begins with epi layer 262 formed on substrate 260. Mask layer 26
4 is formed on the upper surface of the epi layer 262 and has an opening in which a trench is formed. The mask layer 264 may be photoresist or some other material, which may be formed on top of the oxide layer 262. Trenches 268 are formed using conventional processes as shown in Figure 13A.

In FIG. 13B, a sacrificial oxide layer 270 is formed on the surface of the trench. The sacrificial oxide layer 270 is then removed as shown in Figure 13C. Sacrificial oxide layer 27
0 may be 100 angstroms to 1000 angstroms thick, and may typically be on the order of 300 angstroms thick. Generally, the structure may be formed by heating at 800 ° C to 1100 ° C for 10 minutes to 5 hours in an oxidizing environment. The ambient environment can be either oxygen or oxygen and hydrogen. If the environment is a combination of oxygen and hydrogen, the reaction produces water vapor, which is considered to be "wet" oxidation because it can affect the properties and growth rate of the oxide.

Thereafter, an optional oxide lining 272 is formed over trench 268. The lining 272 may have a thickness in the range of 100 Å to 600 Å. The lining 272 prevents the deposited oxide from making direct contact with silicon, which may be in a charged state. This problem can occur especially at the interface between the silicon and the deposited oxide. The addition of a clean oxide layer on the walls of the trench reduces the charge state.

As shown in FIG. 13E, an electric field is applied over the surface of epi layer 262 to form dielectric ions, which are directed downward into trench 268 by the electric field. Desirably, plasma CVD (plasma-enhanced chemical vapor deposition)
) The chamber is used for this process. As the electric field accelerates the dielectric ions downward, they preferentially deposit in the horizontal plane, including the bottom of trench 268. Chemical vapor deposition of oxides involves the chemical reaction of oxygen with silane, dichlorosilane, or silicon tetrachloride in the gaseous state. The source of oxygen is usually nitreous oxide, and silane is the source of silicon. Plasma CVD equipment is Novellus Syste
Companies such as ms and Applied Materials are available.

Another method to achieve directional deposition is to sputter an oxide film onto the wafer from an oxide coated target. Deposition occurs linearly because sputtering is a momentum transport process.

As a result of the process shown in FIG. 13F, an oxide layer 270 is formed inside and outside the trench 268. Note that oxide layer 270 is thicker at the bottom than at the sidewalls of trench 268. It is also thicker on the flat surface of epi layer 262. Processes other than chemical vapor deposition, such as sputtering, are also suitable for oxide layer 27.
It can be used to generate 0.

Layer 270 can also be formed from materials other than oxides, such as phosphorous deposited glass or boron phosphorous silicon glass. It can also consist of other materials such as polymers or polyimides with a low dielectric constant K. Bubbles may be introduced into layer 270 to reduce the dielectric constant.

In FIG. 13G, oxide layer 270 has been etched back and diped back to remove the sidewalls of trench 268. The bottom portion 274 of the oxide layer 270 remains at the bottom of the trench 268. As shown in FIG. 13H, trench 2
The structure is then heated to form a thin oxide layer 276 on the sidewalls of 68.
Polysilicon layer 278 is then deposited to fill trench 268 and overflow the top surface of the structure. This is shown in Figure 13I.

As shown in FIG. 13J, polysilicon layer 278 is then etched back until it is substantially coplanar with the top surface of epi layer 262. Next, a portion of the oxide layer 270 on the surface of the epi layer 262 is removed, taking care not to over etch the oxide layer 276 on the sidewalls of the trench. The result of this step is shown in FIG. 13K. By having a slightly protruding polysilicon layer 278 over the oxide layer 276,
The avoidance of the removal of the oxide layer 276 is optimally carried out. In FIG. 13L, the entire top surface of the structure, including the top surface of polysilicon layer 278, is oxidized to form oxide layer 280.

A glass layer 282 covers the surface of the oxide layer 280, as shown in FIG. 13M,
The glass layer 282 and oxide layer 280 are then patterned and etched to form contact openings in the epi layer 262, resulting in the structure shown in Figure 13N.

14A-14F show an alternative process flow starting with the structure shown in FIG. 13I. FIG. 14A corresponds to FIG. 13I. The polysilicon layer 278 is etched as shown in FIG. 14B, and then the polysilicon layer 278 is etched.
The top surface of the remaining portion of the is oxidized to form an oxide layer 290 as shown in Figure 14C. A glass layer 292 is then deposited over the entire surface of the structure as shown in Figure 14D. A mask layer 294 is formed on top of the glass layer 292 and layers 270 and 2 are formed to form contact openings, as shown in Figure 14F.
92 is etched. Next, the mask layer 294 is removed.

15A-15F again represent another alternative starting with the structure shown in FIG. 13I. FIG. 15A corresponds to FIG. 13I. As shown in FIG. 15B, the polysilicon layer 278 is etched back to the level inside the trench. A second polysilicon layer 300 is then deposited over the entire structure as shown in Figure 15C. The polysilicon layer 300 is then etched back, but care must be taken not to expose a portion of the oxide layer 276 in the upper corners of the trench. The resulting structure is shown in Figure 15D. The oxide layer 270 is then removed as shown in FIG. 15E, forming an oxide layer 302 over the entire surface of the structure. A glass layer 304 is then deposited on the oxide layer 302, resulting in the structure shown in Figure 15F.

16A-16E represent an alternative process starting from the structure of FIG. 13F. FIG. 16A
Corresponds to FIG. 13F. A photoresist layer is formed over the structure, grown and rinsed so that the photoresist layer on the top of the structure is removed and left at the bottom of trench 268. This is trench 2
This utilizes the fact that the photoresist is difficult to remove from the bottom of 68. The resulting structure with the remaining portion of photoresist layer 310 at the bottom of trench 268 is shown in Figure 16B. An oxide etch is then performed to remove a portion of oxide layer 270 from the sidewalls of trench 268. A thorough rinse then acts to remove the photoresist 310, providing the structure shown in FIG. 16C. The structure then forms a thin oxide layer 31 on the sidewalls of the trench.
Oxidized to form 2 and the trench is filled with a polysilicon layer 314 as shown in FIGS. 16D and 16E. A two-step polysilicon deposition may be performed, as shown in FIGS. 15A-15C.

17A-17F illustrate yet another alternative embodiment process starting with the structure depicted in FIG. 13F. FIG. 17A corresponds to FIG. 13F. As shown in FIG. 17B, the sacrificial polysilicon layer 320 is deposited. Polysilicon layer 320 is etched back until only small portion 322 remains at the bottom of trench 268. Then, the part 322 of the polysilicon layer 320 is oxidized. Low temperature (e.g. 700-950 degrees) oxidation processes have been used because low temperature polysilicon oxide oxidizes silicon more rapidly than single crystals. Thus, oxide is formed in portion 322 faster than the sidewalls of trench 268. The resulting structure is shown in FIG. 17B with oxide layer 324 at the bottom of trench 268. A portion of oxide layer 270 has been removed from the sidewalls of trench 268 as shown in FIG. 17E and thin gate oxide layer 326 has been formed in trench 26 as shown in FIG. 17F.
8 side walls.

18A-18F represent another alternative process starting with the structure shown in FIG. 13B. FIG. 18A corresponds to FIG. 13D and has an oxide lining 272 formed. Instead of utilizing directional dielectric deposition as shown in FIG. 13E, sacrificial polysilicon layer 330 is deposited as shown in FIG. 18B. The polysilicon layer 330 is etched back until only a small portion 332 remains at the bottom of the trench 268, as shown in FIG. 18C. The structure is then subjected to low temperature oxidation as described above to remove polysilicon portion 332 into oxide layer 3 as shown in FIG. 18D.
Change to 34. The oxide lining 272 is then stripped from the sidewalls and top of the structure, and the gate oxide 336 is grown on the sidewalls of the trench 268, as shown in FIG. 18E. The resulting structure is shown in Figure 18F.

19A-19I represent processes including the super self-alignment process described in application Ser. No. 09 / 296,959, supra. The structure grows on the substrate 340
Formed in epi layer 342. A thin oxide layer 346 is formed on the surface of epi layer 342, which is covered with a layer 344 of a hard masking material such as silicon nitride.
As shown in FIG. 19A, openings have been etched in nitride layer 344 and oxide layer 346.

As shown in FIG. 19B, the trench 348 is epi removed using conventional processes.
Etched in layer 342. A sacrificial oxide layer (not shown) is formed in the walls of trench 348 and removed. An oxide lining 350 is then formed on the walls of the trench 348, as shown in FIG. 19C. As shown in FIG. 19D, FIG.
Directional deposition of the type described above in connection with E works to form oxide layer 352. As shown in FIGS. 19E and 19F, the oxide layer 352 and portions of the oxide lining 350 are removed from the sidewalls of the trench 348. This is, for example, 17
This is done by dipping the structure in 0 HF acid. Gate oxide layer 356 is then formed and the trench is filled with polysilicon layer 358. These steps are shown in Figure 19G.
And 19H.

The polysilicon layer 358 is then etched back to a level above the surface of the thin oxide layer 346, as shown in FIG. In FIG. 19J, the thick oxide layer 352 has been removed over the nitride layer 344 and the polysilicon layer 358 protects the thin oxide layer 356 at the edges of the trench 348. The structure is then annealed and a portion of polysilicon layer 358 is oxidized to form a thick oxide layer 360 in the upper region of the trench as shown in Figure 19K. Finally, the nitride layer 344 is removed as shown in Figure 19L.

21A-20F show a two-step polysilicon process with two trenches, one of which is the active array and the other is part of the gate bus. The process begins with the polysilicon layer 388 filling the trenches 374A and 374B at the point shown in FIG. 19H. 374A of trench
A thick oxide layer 384 was formed at the bottom of and 374B. A silicon nitride layer 374 covers the epi layer 372 surface and a nitride layer 374 is covered with an oxide layer 382.

The polysilicon layer 388 is etched back and the oxide layer 382 is removed, as shown in FIG. 20B. The second polysilicon layer 390 is the polysilicon layer 38.
A "hard" layer 392 of nitride or polyimide is deposited over the second polysilicon layer 390, for example. The resulting structure is shown in Figure 20C.

As shown in FIG. 20D, the polysilicon layer 390 and the hard layer 392 are etched from the active array (trench 374A) area, leaving them in the gate bus (trench 374B) area. The structure is heated to oxidize polysilicon layer 388 in trench 374A, producing a thick oxide layer 394 in the upper region of the trench. At the same time, an oxide layer 396 is formed on the exposed edge of the second polysilicon layer 390. This structure is shown in FIG. 20E.

Finally, the exposed portions of the hard layers 374 and 392 are removed, and FIG.
You will get the placement shown in.

21A-21E and 22A-22C illustrate two problems that need to be avoided. FIG. 21A shows a sacrificial oxide layer 400 along the walls of the trench, and a thin oxide layer 404 and nitride layer 402 on top of the epi layer. As shown in FIG. 21B, during the sacrificial oxide layer 400 elimination process, a portion of the thin oxide layer 404 has been removed under the nitride layer 402. The solution to this problem is to minimize the oxide overetch time, or to use the thinnest possible oxide layer 404, such as 15-90 Angstroms.

Gate oxide layer 4 with the formation of a thick oxide layer 408 at the bottom of the trench.
If 06 is formed, the gate oxide layer 406 may not fully cover the upper corners of the trench as shown in Figure 21C. 21D and 21E show the structure after the polysilicon layer 412 has been deposited and etched back from the active array of devices, with the polysilicon layer 412 at the upper corners of the trench.
A thin oxide layer is shown separating the epi layer.

22A-22C illustrate another potential problem area. FIG. 22A represents a device at the same stage as shown in FIG. 19D, with a thick directionally deposited oxide layer 352 forming a thick portion 354 at the bottom of the trench. In the process of removing oxide from the trench sidewalls, a portion of thin oxide layer 346 is removed from underneath nitride layer 344, as shown in FIG. 22B. Next, a gate oxide layer 356 is grown, and some of the oxide layer at the upper corners of the trench is extremely thin, which can lead to oxide defects and shorts between the gate and epi layers. . This problem is illustrated in Figure 22C.
Is shown in. Again, the solution is to minimize oxide overetching, or instead use plasma etching, which is chemically isotropic.

FIG. 23A illustrates the problem that occurs when polysilicon fills the cavity formed under the nitride layer as shown in FIG. 21E. Polysilicon layer 4
A portion 420A of 20 extends out of the trench and shorts to a subsequently deposited metal layer to contact the epi layer. During oxidation, oxide 422 does not attack the silicon that fills under the nitride overhang. Therefore, removal of the nitride exposes the gate and shorts to the source metal. FIG. 23B shows a part 4 of the polysilicon layer.
20B illustrates a variation where 20B is isolated from the main polysilicon layer 420 by an oxide. FIG. 23C illustrates the case where the polysilicon layer 420 forms an upwardly protruding spike 420C, which tends to cause a short circuit between the gate polysilicon layer 420 and a subsequently deposited metal layer. Again, the polysilicon layer that fills under the nitride remains after oxidation and is a potential gate-source short.

FIG. 23D shows the gate IV characteristics of the device in which the short circuit occurred. If the resistance is low, it is called a "hard" short circuit. FIG. 23E shows the characteristics of a "soft" or diode-like short circuit. Unlike hard shorts, where metal directly contacts the top surface of the polysilicon gate, diode-like shorts can occur in the gate bus region shown in Figure 23F. In this type of malfunction, N + regions or plumes are doped into the P body wherever the polysilicon touches the silicon mesas, thereby forming parasitic diodes and MOSFETs as schematically shown in Figure 23G. There is.

24A-24F show the process mechanism that causes a diode short circuit due to the over-etched first polysilicon layer and a malformed or distorted trench. In FIG. 24A, the active cell and gate bus regions are filled with a first layer of N + doped polysilicon and then etched back to produce the structure shown in FIG. 24B. If the polysilicon etchback is not uniform, one end of the trench oxide may be exposed, as shown in Figure 24C, which is then eroded during the top oxide removal dip process. , Etched.
In FIG. 24D, a second polysilicon layer has been deposited and patterned by masking, leaving the active cell on the left and the gate bus on the right. After oxidation of the top surface, FIG.
The active cell on the left is oxidized and self-repaired, as shown by, but in the gate bus region, the N + plume is doped by the polysilicon in contact with the silicon, leading to the diode-like gate short in FIG. 24F. A uniform etch back of polysilicon or a uniform shaped trench avoids this problem.

25A-25H describe a process for avoiding problems by using nitride sidewall spacers. The process begins with the epi layer 502 growing on the substrate 500. A thin oxide layer 504 is grown on top of the epi layer 502,
Nitride layer 506 (or another "hard" layer) and second oxide layer 508.
Are continuously formed on the oxide layer 504. Therefore, layers 504, 506,
And 508 form an oxide-nitride-oxide (ONO) sandwich known in the art. The resulting structure is shown in Figure 25A. Figure 25B
Openings are etched into the ONO sandwich as shown in FIG. Nitride layer 510 is then deposited on top of the structure, providing the alignment as seen in Figure 25C. The nitride layer is unevenly etched. Since the vertical thickness of nitride layer 510 is greater than the edges of the ONO sandwich, the anisotropic etch leaves sidewall spacers 512 at the exposed edges of oxide layer 504 and nitride layer 506. This structure is
After removal of oxide layer 508, shown in FIG. 25D.

Next, as shown in FIG. 25E, the trench 514 is then etched to form and remove a typical sacrificial oxide layer (not shown). FIG. 25F shows oxide layer 5
16 shows the structure after 16 directional deposition, which leaves a thick oxide layer 518 at the bottom of the trench 514. This is done after forming the gate oxide layer 520. afterwards,
The trench is filled with polysilicon layer 522 and is etched back with care not to attack the underlying oxide layer 520. The upper region where the polysilicon and silicon are almost in contact will be further oxidized in a later process. Also, some oxide grows underneath the "bird's beak" like nitride sidewall cap. This structure is shown in Figure 2.
Shown in 5G. The oxide layer 516 is removed, providing the example shown in FIG. 25H.

As shown in FIGS. 26A and 26B, growth of gate oxide on the sidewalls of the trench can lead to “distortion” in the sidewalls of the trench, as shown by the distortion 530 in FIG. 26B. The problem is that the oxide grows uniformly on the exposed sidewalls 532 of the trench, as shown in FIG. 26A. But thick oxide 534
Where the trench starts at the bottom of the trench, the oxidation does not proceed linearly due to the external morphology of the structure. This produces a reduced thickness oxide layer at distortion 530.

A solution to this problem is shown in Figures 27A-27D. FIG. 27A shows the structure after thermal growth of oxide lining 540 and directional deposition of oxide layer 542, as described above. The lining 540 and layer 542 are removed from the sidewalls of the trench as shown in Figure 27B. The structure is immersed in 170 HF acid (di
p) Since the deposited oxide is etched faster than the thermally grown oxide, the structure looks like FIG. 27C with the top of the lining 540 slightly above the top of the oxide layer 542 after immersion. Become. When the gate oxide layer is thermally grown on the trench sidewalls, the resulting oxide has a uniform thickness. There is no "distortion" on the walls of the trench. FIG. 27D represents the placement after the gate oxide layer 544 is grown on the sidewalls of the trench. The dotted line shows the original position of silicon prior to oxidation.

28-33 show various devices that can be manufactured using the principles of the present invention.

FIG. 28 represents a power MOSFET with a flat bottom P-body region and an N buried layer at the interface between the epi layer and the substrate. FIG. 28 shows a device that combines contacts that extend across the mesas between the trenches and a thick trench bottom oxide. It is also possible to use a contact mask or a non-planar top oxide layer. FIG. 29 shows a MOSFET similar to that shown in FIG. 28 except that each MOSFET cell includes a deep P + region as shown in US Pat. No. 5,072,266 to Bulucea et al. ing. The embodiment of FIG. 30 is a MOSF.
It has a flat bottom P + region in the ET cell and further has a diode cell containing a deep P + region used to provide voltage clamping for the MOSFET cell. Such a structure is described in application Ser. No. 08 / 846,688, which is hereby incorporated by reference.

In the device shown in FIG. 31, there is no contact between the P body region and the metal layer in each MOSFET cell. Instead, U.S. Pat. No. 5,877,53
8. Contact the body in a third direction, as described by Williams et al. This application is also incorporated by reference herein. MOSFET cell 1
Note that one has a deep P + region to limit the strength of the electric field at the bottom of the trench. In addition, a flat top oxide layer with self-aligned contacts is preferred, but not required.

In the example of FIG. 32, the trench extends to the N buried layer and only the thick oxide regions overlap the heavily doped buried layer.

The embodiment of FIG. 33 is a storage mode MOSFET (ACCUFET) such as the one disclosed by Williams et al. In US Pat. No. 5,856,692, which is hereby incorporated by reference. .

FIG. 34 is a conceptual diagram showing a process flow for a conventional contact mask and a trench MOSFET using an embedded thick trench bottom oxide. Process steps typically include drain and body region build, trench etch and gate build, body and source region fill, contact openings and metal layer deposition. In FIG. 34, the square corners lacking represent an optional process. Therefore, the introduction of deeper body regions by implantation or implantation and diffusion is consistent with this process.

This process is shown in FIGS. 35A-35L. Trench 552 is Nepi
Formed in layer 550 using oxide layer 554 as a mask. An oxide lining 556 is formed on the walls of the trench 552 (FIG. 35B), a directional oxide deposition is made as described above, and an oxide layer 558 having a thick portion 560 at the bottom of the trench.
Are formed (FIG. 35C). The sidewalls of trench 552 are then etched (FIG. 35D).
), A gate oxide layer thermally grows on the trench walls 552 (FIG. 35E).

Polysilicon layer 564 is then deposited to fill trench 552 (FIG. 35F). The polysilicon layer 564 is etched back into the trench (FIG. 35G). An oxide layer 566 is deposited on the top surface of the structure and extends to the top surface of the polysilicon layer 564 towards the trench (FIG. 35H). The oxide layer 566 is then etched back and a P-type dopant, such as boric acid, is implanted to form the P body region 568. The top surface is then masked (not shown) and an N-type dopant such as arsenic or phosphorus is implanted to form N + source region 570. Another oxide layer 572 is deposited on top and patterned to obtain the structure shown in FIG. 35L. The contacts can be filled with a top metal, but can alternatively be filled with a planarizing metal such as tungsten or a barrier metal such as Ti / TiN.

36-39 show multiple embodiments in which the cross-section of the polysilicon gate forms a "keyhole" shape. The thicker gate oxide extends not only along the bottom of the trench, but also along the sidewalls of the trench towards the junction between the P body region and the N epi layer. The thickened gate oxide along the sidewalls of the trench helps to relax the electric field at the junction.

FIG. 36 shows a MOSFET with a flat bottom P body region and diode cells incorporated at periodic intervals between the MOSFET cells. In a preferred modification of the MOSFET, a keyhole type gate is adopted. FIG. 37 shows an embodiment in which the P-body does not extend to the surface but instead contacts in a third direction. The shallow P + region can be seen deeper than the N + source region in the mesa. In Figure 38, the trench is e
An example is shown extending into the N-buried layer formed at the interface between the pi layer and the substrate. FIG. 39 shows an embodiment in which the P-body is connected in the third direction and the trench extends into the N-buried layer.

A process flow for forming a device having a keyhole-shaped trench is shown in FIG. 40A-40.
Indicated by L. The process begins with the epi layer 602 grown on the substrate 600.
An oxide layer 604 is formed on the top surface of the epi layer 602, as shown in FIG. 40A. The oxide layer 604 is patterned and etched as shown in Figure 40B. A sacrificial oxide layer (not shown) is then grown on the walls of trench 606 (FIG. 40).
Indicated by C).

As shown in FIGS. 40D and 40E, the polysilicon layer 610 has trenches 606.
Deposited to fill and then etched back to leave a portion 612 at the bottom of the trench. Oxide lining 608 is then etched from the sidewalls of trench 606 as shown in FIG. 40F. An anisotropic silicon etch is then performed to depress the top surface of polysilicon layer 612 below the top surface of oxide lining 608 as shown in FIG. 40G. A thermal oxidation process is then used to form an oxide layer 616 on the walls of the trench 606 and a polysilicon layer 6
An oxide layer 618 is formed on the upper surface of 12. The resulting structure is shown in FIG. 40H. Oxide layer 618 is then etched and a portion of oxide layer 616 is removed in the process, producing the structure shown in FIG. 40I.

Next, a second polysilicon layer 619 is deposited over the structure as shown in FIG. 40J. The polysilicon layer 619 is etched back, as shown in FIG. 40K. As shown in FIG. 40L, the top surface of polysilicon layer 619 is then oxidized.

A variation of this process is shown in FIGS. 41A-41F. Oxide lining 6
After 08 is formed on the walls of the trench, a photoresist layer is applied, grown, and removed, leaving only a portion 630 at the bottom of trench 606, as shown in FIG. 40C. This is shown in FIG. 41A. The oxide lining 608 is etched from the walls of the trench 606 as shown in FIG. 41B,
A portion of the photoresist layer 630 is removed from the bottom of the trench. With this,
The structure seen in FIG. 41C is obtained.

As shown in FIGS. 41D and 41F, oxide layer 632 thermally grows on the walls of trench 606 and trench 606 is filled with polysilicon layer 634. Polysilicon layer 634 is etched back to the level of the top surface of epi layer 602. Polysilicon layer 634 is then thermally oxidized to provide the device shown in Figure 41F.

42A-42C show a comparison of the electric field strength along the sidewalls of a prior art trench with that according to the present invention. FIG. 41A is a prior art device in which the electric field is
It is shown that it has two sharp peaks which respectively occur at the drain junction and the bottom of the gate electrode. FIG. 42B shows a device with a thick oxide layer at the bottom of the trench. As shown, the electric field still has a sharp peak at the body-drain junction, but the peak at the bottom of the gate electrode is somewhat lower compared to that of the prior art. Finally, FIG. 42C shows a device with a keyhole-shaped gate electrode. Even in this case, the electric field reaches the peak at the body-drain junction, but the sharp peak at the bottom of the gate electrode is removed.

While several embodiments have been described in accordance with the present invention, they are merely illustrative in all respects and should not be construed as limiting.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a prior art trench power MOSFET having a deep P + diode that acts as a voltage clamp.

FIG. 2 is a prior art trench power MOS with a flat body-drain junction.
It is sectional drawing of FET.

FIG. 3 is a cross-sectional view of a prior art trench power MOSFET having voltage clamps distributed in a plurality of MOSFET cells including a flat body-drain junction.

FIG. 4A is a cross-sectional view showing an electric field contour in a MOSFET having a thick gate oxide layer.

FIG. 4B is a cross-sectional view showing an electric field contour in a MOSFET having a thin gate oxide layer.

FIG. 4C is a cross-sectional view showing the ionization profile in a MOSFET with a thick gate oxide layer at the beginning of avalanche breakdown.

FIG. 4D is a cross-sectional view showing the ionization profile in a MOSFET with a thin gate oxide layer at the beginning of avalanche breakdown.

FIG. 4E is a cross-sectional view showing an ionization profile in a device including a deep P + region used as a voltage clamp.

FIG. 4F shows MO formed on epitaxial layers with different doping concentrations.
3 is a graph showing breakdown voltage in SFET as a function of gate oxide thickness.

FIG. 4G is a schematic diagram of a trench power MOSFET with an anti-parallel diode clamp.

FIG. 5A is a cross-sectional view showing an ionization profile in a trench power MOSFET having square trench corners.

FIG. 5B is a cross-sectional view showing an ionization profile in a trench power MOSFET with rounded trench corners.

FIG. 6A is a cross-sectional view showing an electric field contour in a trench power MOSFET having a flat body-drain junction.

FIG. 6B is a cross-sectional view showing equipotential lines in a trench power MOSFET having a flat body-drain junction.

FIG. 6C is a cross-sectional view showing electric field lines in a trench power MOSFET having a flat body-drain junction.

FIG. 6D is a cross-sectional view showing current flow lines in a trench power MOSFET having a flat body-drain junction.

FIG. 6E is a cross-sectional view showing an ionization profile in a trench power MOSFET at turn-on.

FIG. 6F is a graph showing IV curves for power MOSFETs at different gate voltages, showing how sustain voltage is reduced by impact ionization.

FIG. 7A   FIG. 7A is a schematic diagram of a gate charging circuit for a power MOSFET.

FIG. 7B is a graph showing stepwise addition of gate drive current to a power MOSFET.

FIG. 7C is a graph showing how the gate voltage and the drain voltage change under the conditions of FIG. 7B.

FIG. 7D is a graph showing how the drain current changes under the conditions of FIG. 7B.

FIG. 7E is a graph showing how the gate voltage changes as a function of charge.

FIG. 7F shows the effective input capacitance (effective in
is a graph showing how the put capacitance) changes.

FIG. 7G is a cross-sectional view showing the components of the gate capacitance in the trench power MOSFET.

[FIG. 7H]   FIG. 7H is an equivalent circuit diagram of the trench MOSFET showing the interelectrode capacitance.

8A-8C are cross-sectional views showing how a gate trench having rounded corners is formed.

8A-8C are cross-sectional views showing how a gate trench having rounded corners is formed.

8A-8C are cross-sectional views showing how a gate trench having rounded corners is formed.

9A-9D are cross-sectional views showing a process of etching a gate trench and filling the trench with polysilicon.

9A-9D are cross-sectional views showing a process of etching a gate trench and filling the trench with polysilicon.

9A-9D are cross-sectional views showing a process of etching a gate trench and filling the trench with polysilicon.

9A-9D are cross-sectional views showing a process of etching a gate trench and filling the trench with polysilicon.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

10A to 10F are cross-sectional views of a manufacturing process of a conventional trench power MOSFET.

FIG. 11A shows a trench power MOSFE with a thick oxide layer at the bottom of the trench.
It is sectional drawing of T.

FIG. 11B shows FIG. 11A with a thick oxide layer patterned on top of the semiconductor.
3 is a cross-sectional view showing the MOSFET of FIG.

FIG. 11C shows the M of FIG. 11A with a thick top oxide layer aligned to the walls of the trench.
It is sectional drawing which shows OSFET.

FIG. 12 is a schematic flow diagram showing many process sequences according to the present invention.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench that uses directional deposition of an oxide layer and etches polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the trench bottom that uses directional deposition of an oxide layer and etches polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the trench bottom using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the trench bottom using directional deposition of oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench that uses directional deposition of an oxide layer and etches polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench that uses directional deposition of an oxide layer and etches polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench using directional deposition of an oxide layer and etching polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

13A-13N show a trench power MOSFET with a thick oxide layer at the bottom of the trench that uses directional deposition of an oxide layer and etches polysilicon to the same level as the top surface of the semiconductor material. 3 illustrates a process sequence for forming.

14A-14F show an alternative process sequence in which polysilicon is etched to a level below the surface of the semiconductor material and then oxidized.

14A-14F show an alternative process sequence in which polysilicon is etched to a level below the surface of the semiconductor material and then oxidized.

14A-14F show an alternative process sequence in which polysilicon is etched to a level below the surface of the semiconductor material and then oxidized.

14A-14F show an alternative process sequence in which polysilicon is etched to a level below the surface of the semiconductor material and then oxidized.

14A-14F show an alternative process sequence in which polysilicon is etched below the surface of the semiconductor material and then oxidized.

14A-14F show an alternative process sequence in which polysilicon is etched to a level below the surface of the semiconductor material and then oxidized.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

15A-15F show an alternative process sequence in which polysilicon is deposited in two steps.

16A-16E show an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.

16A-16E show an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.

16A-16E show an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.

16A-16E show an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.

16A-16E show an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.

17A-17F show a process in which polysilicon is etched to a level near the trench bottom and subsequently oxidized.

17A-17F show a process in which polysilicon is etched to a level near the bottom of the trench, followed by oxidation.

17A-17F show a process in which polysilicon is etched to a level near the bottom of the trench, followed by oxidation.

17A-17F show a process in which polysilicon is etched to a level near the bottom of the trench, followed by oxidation.

17A-17F illustrate a process in which polysilicon is etched to a level near the bottom of the trench and subsequently oxidized.

17A-17F show a process in which polysilicon is etched to a level near the bottom of the trench, followed by oxidation.

18A-18F show an alternative process in which polysilicon is oxidized.

18A-18F show an alternative process in which polysilicon is oxidized.

18A-18F show an alternative process in which polysilicon is oxidized.

18A-18F show an alternative process in which polysilicon is oxidized.

18A-18F show an alternative process in which polysilicon is oxidized.

18A-18F show an alternative process in which polysilicon is oxidized.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L illustrate a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for making a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer provided on a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for making a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

19A-19L show a process for manufacturing a trench power MOSFET having an oxide layer overlying a gate electrode that is self-aligned with the walls of the trench.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

20A-20F show a process sequence for forming trench gates and gate buses in an active array of power MOSFETs.

21A-21E illustrate problems that can result from undercutting a thin oxide layer under a nitride.

21A-21E illustrate problems that may result from undercutting a thin oxide layer under a nitride.

21A-21E illustrate problems that can result from undercutting a thin oxide layer under a nitride.

21A-21E illustrate problems that may result from undercutting a thin oxide layer under a nitride.

21A-21E illustrate problems that can result from undercutting a thin oxide layer under a nitride.

FIG. 22A   22A-22C show a further example of this problem.

FIG. 22B   22A-22C show a further example of this problem.

FIG. 22C   22A-22C show a further example of this problem.

23A-23G illustrate other problems that may occur in the fabrication of power MOSFETs according to the present invention.

23A-23G show another problem that may occur in the fabrication of a power MOSFET according to the present invention.

23A-23G show other problems that may occur in the fabrication of power MOSFETs in accordance with the present invention.

23A-23G show another problem that may occur in the fabrication of a power MOSFET according to the present invention.

23A-23G show other problems that may occur in the fabrication of power MOSFETs in accordance with the present invention.

23A-23G illustrate another problem that may occur in manufacturing a power MOSFET according to the present invention.

23A-23G illustrate another problem that may occur in the fabrication of power MOSFETs in accordance with the present invention.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

24A-24F illustrate problems that can result from underetching a hard mask when removing top oxide in a self-aligned device.

25A-25H show a manufacturing process for a trench power MOSFET having a thick bottom oxide layer and a nitride side spacer.

25A-25H show a fabrication process for a trench power MOSFET with a thick bottom oxide layer and a nitride side spacer.

25A-25H show a manufacturing process for a trench power MOSFET having a thick bottom oxide layer and a nitride side spacer.

25A-25H show a manufacturing process for a trench power MOSFET with a thick bottom oxide layer and a nitride side spacer.

25A-25H show a fabrication process for a trench power MOSFET with a thick bottom oxide layer and a nitride side spacer.

25A-25H show a fabrication process for a trench power MOSFET with a thick bottom oxide layer and a nitride side spacer.

25A-25H show a manufacturing process for a trench power MOSFET having a thick bottom oxide layer and a nitride side spacer.

25A-25H show a manufacturing process for a trench power MOSFET having a thick bottom oxide layer and a nitride side spacer.

26A and 26B illustrate problems that may occur when forming a gate oxide layer on a thick bottom oxide.

26A and 26B illustrate problems that can occur when forming a gate oxide layer on a thick bottom oxide.

27A-27D show how to avoid the problem shown in FIGS. 26A and 26B.

27A-27D show how to avoid the problem shown in FIGS. 26A and 26B.

27A-27D show a method of avoiding the problem shown in FIGS. 26A and 26B.

27A-27D show how to avoid the problem shown in FIGS. 26A and 26B.

28-33 show various types of tie trench power MOSFETs that can be manufactured in accordance with the present invention.

FIGS. 28-33 show various tie trench power MOSFETs that can be manufactured in accordance with the present invention.

28-33 show various tie trench power MOSFETs that can be manufactured in accordance with the present invention.

28-33 show various tie trench power MOSFETs that can be manufactured in accordance with the present invention.

28-33 show various tie trench power MOSFETs that can be manufactured in accordance with the present invention.

FIGS. 28-33 illustrate various types of tie trench power MOSFETs that can be manufactured in accordance with the present invention.

FIG. 34 shows a flow diagram of a process sequence for manufacturing a trench power MOSFET with a thick bottom oxide layer while using a conventional contact mask.

FIG. 35A   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35B   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35C   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35D   35A to 35L are cross-sectional views showing the process of FIG.

[FIG. 35E]   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35F   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35G   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35H   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35I   35A to 35L are cross-sectional views showing the process of FIG.

[FIG. 35J]   35A to 35L are cross-sectional views showing the process of FIG.

[Fig. 35K]   35A to 35L are cross-sectional views showing the process of FIG.

FIG. 35L   35A to 35L are cross-sectional views showing the process of FIG.

36-39 show a trench power MOSFE with a "keyhole" shaped gate electrode.
It is sectional drawing which shows T.

36-39 show a trench power MOSFE with a "keyhole" shaped gate electrode.
It is sectional drawing which shows T.

FIGS. 36-39 show trench power MOSFEs with “keyhole” shaped gate electrodes.
It is sectional drawing which shows T.

FIGS. 36-39 show trench power MOSFE with “keyhole” shaped gate electrode.
It is sectional drawing which shows T.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A to 40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

40A-40L show a process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

41A-41F show an alternative process sequence for manufacturing a MOSFET having a keyhole-shaped gate electrode.

42A-42C show a conventional power MOSFET, a power MOSFET with a thick bottom gate oxide, and a power M with a keyhole-shaped gate electrode, respectively.
The strength of the electric field in the OSFET is shown.

42A-42C show a conventional power MOSFET, a power MOSFET with a thick bottom gate oxide, and a power M with a keyhole-shaped gate electrode, respectively.
The strength of the electric field in the OSFET is shown.

42A-42C show a conventional power MOSFET, a power MOSFET with a thick bottom gate oxide, and a power M with a keyhole-shaped gate electrode, respectively.
The strength of the electric field in the OSFET is shown.

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission date] December 15, 2000 (2000.12.15)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Contents of correction]

13A-13N represent a process using the oxide “dipback” method. The process begins with epi layer 262 formed on substrate 260. Mask layer 26
4 is formed on the upper surface of the epi layer 262 and has an opening in which a trench is formed. The mask layer 264 may be photoresist or some other material, which may be formed on top of the oxide layer 266. Trenches 268 are formed using conventional processes as shown in Figure 13A.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0080

[Correction method] Change

[Contents of correction]

FIG. 34 is a conceptual diagram showing a process flow for a conventional contact mask and a trench MOSFET using an embedded thick trench bottom oxide. Process steps typically include drain and deep body region build, trench etch and gate build, body and source region fill, contact openings and metal layer deposition. In FIG. 34, the square corners lacking represent an optional process. Therefore, the introduction of deeper body regions by implantation or implantation and diffusion is consistent with this process.

[Procedure 3]

[Document name to be corrected] Drawing

[Correction target item name] FIG. 19I

[Correction method] Change

[Contents of correction]

FIG. 19I

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission Date] July 11, 2001 (2001.7.11)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Contents of correction]

Gate oxide layer 4 with the formation of a thick oxide layer 408 at the bottom of the trench.
If 06 is formed, the gate oxide layer 406 may not fully cover the upper corners of the trench as shown in Figure 21C. 21D and 21E show the configuration after a polysilicon layer 412 has been deposited and etched back from the active array of devices using a nitride layer 414, with polysilicon layer 412 at the upper corners of the trench. A thin oxide layer is shown separating the epi layer.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, C H, CN, CR, CU, CZ, DE, DK, DM, DZ , EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, K G, KP, KR, KZ, LC, LK, LR, LS, LT , LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, S D, SE, SG, SI, SK, SL, TJ, TM, TR , TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Williams, Richard Kay             California 95014, USA             Coupertino Norwich Avenue             ー 10292 (72) Inventor Glabowski, Wayne Bee             United States California 94024             Los Altos Mirabell Avenue 1390 [Continued summary] (320) is oxidized and trench (268) is Filled with con. These processes depend on the orientation of the oxide To deposit polysilicon and oxidize subsequent to thermal deposition Can be combined. "Keyhole" shaped gate The method of forming the electrode (634) is based on the bottom of the trench (606). Process of depositing polysilicon on the top surface of polysilicon The process of oxidizing the silicon and etching the oxidized polysilicon And the trench (606) is filled with polysilicon. And the process of filling.

Claims (4)

[Claims] 1. A method of manufacturing a trench semiconductor device, comprising: preparing a semiconductor material; introducing the semiconductor material into a reaction chamber; forming a trench in the semiconductor material; A step of generating charged dielectric particles, a step of forming an electric field in the chamber, a step of forming a layer of the dielectric in the trench, and a step of forming the dielectric layer in the trench. So that the bottom is thicker than the side wall,
A step of accelerating charged particles toward the semiconductor material by using the electric field; and a step of forming a gate electrode by depositing a conductive material on the trench. Method. 2. The method of claim 1, wherein the step of producing charged particles comprises reacting at least two gases within the chamber. 3. The method of claim 2, wherein the step of producing charged particles comprises producing a plasma in the chamber. 4. The method of claim 1, wherein the step of producing charged particles comprises sputtering.