JP2018170441A - Semiconductor apparatus and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve withstand voltage performance of a semiconductor apparatus having a groove while improving device performance.SOLUTION: A trench 19 is a groove formed at a predetermined position of a semiconductor layer 20, which penetrates a second n layer 13, p layer 12 to reach a depth of a first n layer 11. A first insulating film 14A is made of SiOand is positioned by being in contact with the first n layer 11 exposed at a corner portion 19c of the trench 19. The first insulating film 14A is formed at a height that is not in contact with the p layer 12 on a side surface 19b of the trench 19. A second insulating film 14B is made of AlOand is continuously provided in a film shape on a bottom surface 19a of the trench 19, the first insulating film 14A, the side surface 19b of the trench 19, and a surface of the second n layer 13.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having a groove and a method for manufacturing the same.

  In a semiconductor device such as an FET, a trench gate structure capable of reducing the area of a unit cell and reducing on-resistance has been developed. In the semiconductor device having the trench gate structure, there is a problem that the electric field tends to concentrate on the corners of the trench and the withstand voltage performance cannot be sufficiently improved. Therefore, various techniques for improving the gate breakdown voltage have been developed.

  Patent Document 1 describes that, in the gate insulating film covering the trench side surface and the bottom surface, the pn interface region on the trench side surface and the thickness of the trench bottom surface portion are made thicker than the other portions.

  In Patent Document 2, a first insulating film is formed so as to cover a side surface and a bottom surface of a trench, and a second insulating film made of a material having a higher dielectric constant than the gate insulating film is formed on the first insulating film. It is described that it is formed only at the corners of the trench.

JP2012-216675A JP 2016-164906 A

  However, in the conventional trench gate structure, although the gate withstand voltage is improved, the on-resistance and gm (mutual conductance) characteristics at the time of conduction are insufficient or sometimes deteriorated.

  Accordingly, an object of the present invention is to improve gate breakdown voltage performance while improving device performance.

  The present invention provides a semiconductor layer having a body layer provided with a groove penetrating the body layer and in contact with a corner of the groove in a semiconductor device in which the body layer is exposed at a part of the side surface of the groove. A first insulating film that does not contact the body layer of the groove, a body layer exposed on a side surface of the groove, and a second insulating film provided so as to continuously cover the first insulating film, The semiconductor device is characterized in that the dielectric breakdown strength of one insulating film is higher than the dielectric breakdown strength of the second insulating film, and the relative dielectric constant of the second insulating film is higher than the relative dielectric constant of the first insulating film. It is.

  The groove may be of any purpose, may be a trench groove for a gate trench structure, or may be a mesa groove for a termination structure. In the case of the gate trench structure, the groove in the present invention is a trench groove, and has a structure in which a gate electrode is provided on the second insulating film along the bottom surface and the side surface of the groove. In the case of the termination structure, the groove in the present invention is a mesa groove provided in the termination portion of the semiconductor device.

  The ratio of the height of the first insulating film to the width of the first insulating film is preferably 0.2 to 0.5. By setting the ratio within this range, it is possible to further improve element performance and pressure resistance performance. It is more preferably 0.20 to 0.30, and further preferably 0.20 to 0.25.

The materials of the first insulating film and the second insulating film are such that the dielectric breakdown strength of the first insulating film is higher than the dielectric breakdown strength of the second insulating film, and the relative dielectric constant of the second insulating film is that of the first insulating film. Any combination of materials may be used as long as the ratio is higher. For example, SiO ₂ can be used for the first insulating film, and Al ₂ O ₃ , ZrON, AlON, ZrO ₂ , HfO _2, or HfON can be used for the second insulating film.

  As the semiconductor device of the present invention, various known structures can be adopted, but the present invention is suitable for a vertical structure that conducts in a direction perpendicular to the main surface of the semiconductor layer. In addition, the semiconductor layer material of the present invention may be any semiconductor material, but the present invention is suitable when using a high breakdown voltage group III nitride semiconductor or SiC, and particularly suitable for a group III nitride semiconductor. .

  The present invention also provides a method for manufacturing a semiconductor device in which a semiconductor layer having a body layer is provided with a groove penetrating the body layer and the body layer is exposed at a part of the side surface of the groove. And a first step of forming a first insulating film in the form of a film continuously on the surface of the semiconductor layer, and after the first step, etching is performed so as not to contact the body layer on the side surface of the groove by etching. The second step of leaving one insulating film and removing the first insulating film in other regions, and the body layer exposed on the side surface of the groove after the second step, and the first insulating film are continuously covered And a third step of forming a second insulating film.

  In the first step, the first insulating film is preferably formed such that the thickness of the region on the side surface of the groove is smaller than the thickness of the region on the bottom surface of the groove and the surface of the semiconductor layer. In the second step, it is easy to perform etching so as to leave the first insulating film at the corner of the groove.

  In the second step, anisotropic dry etching may be used for etching. It becomes easy to leave the first insulating film at the corner of the groove.

  In the third step, the second insulating film may be formed by an ALD method. Since the step coverage is excellent and a uniform amorphous film with a uniform thickness can be obtained, the device performance and the pressure resistance performance can be further improved.

  According to the present invention, since the first insulating film in contact with the corner of the groove is provided, the electric field concentration at the bent portion of the second insulating film can be alleviated, and the first insulating film has high dielectric breakdown strength. The pressure resistance performance can be improved. In addition, since the body layer exposed on the side surface of the groove is covered with the second insulating film having a high relative dielectric constant, the device performance can be improved. Thus, according to the present invention, it is possible to achieve both improvement in device performance and improvement in breakdown voltage performance.

FIG. 3 shows a configuration of a semiconductor device of Example 1. FIG. 3 is a diagram showing a planar pattern of the semiconductor device of Example 1; The figure which expanded and showed the corner | angular part 19c of the trench 19. FIG. The figure which showed the modification of the shape of 14 A of 1st insulating films. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device of Example 1; The figure which showed the structure of the trench 19 corner | angular part 19c of Comparative Examples 1-3. The graph which showed the electric field strength ratio of Example 1 and Comparative Examples 1-3. The graph which showed the drain current-gate voltage characteristic. The graph which showed the relationship between ratio of height H to width W, and electric field strength. The graph which showed the relationship between ratio of height H to width W, and electric field strength. The figure which showed the termination | terminus structure of the semiconductor device.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to the examples.

  1 is a diagram showing a configuration of a semiconductor device made of a group III nitride semiconductor of Example 1. FIG. The semiconductor device of Example 1 has a vertical structure that conducts in a direction perpendicular to the main surface of the substrate. The gate is an FET having a trench gate structure. As shown in FIG. 1, the semiconductor device of Example 1 includes a substrate 10, a semiconductor layer 20 located on the substrate 10, a first insulating film 14 </ b> A, a second insulating film 14 </ b> B, a gate electrode 15, and a source electrode 17. And a drain electrode 18, a p body electrode 21, a trench 19, and a recess 22. The semiconductor layer 20 has a structure in which a first n layer 11, a p layer 12, and a second n layer 13 are sequentially stacked. Each configuration will be described below.

  FIG. 1 shows a cross section in the structure of a unit cell of a semiconductor device. The entire device has a structure in which regular hexagonal unit cells are arranged in a honeycomb and connected in parallel. More specifically, as shown in FIG. 2, a regular hexagonal source electrode 17, a gate electrode 15, and a trench 19 are formed concentrically around the regular hexagonal p body electrode 21 so as to surround the p body electrode 21. The pattern is arranged. Of course, the unit cell pattern and the unit cell arrangement pattern are not limited to this, and may be any pattern. However, if the honeycomb pattern is used as described above, the efficiency of planar filling and the reduction of on-resistance can be reduced. This is advantageous.

The substrate 10 is a plate-shaped substrate made of Si-doped c-plane n-GaN and having a thickness of 300 μm. The Si concentration is 1 × 10 ¹⁸ / cm ³ . In addition to n-GaN, a substrate of any material having conductivity and serving as a group III nitride semiconductor growth substrate can be used. For example, ZnO, Si or the like can be used. However, from the point of lattice matching, it is desirable to use a GaN substrate as in this embodiment.

The first n layer (drift layer) 11 is a 10 μm thick Si-doped n-GaN layer stacked on the substrate 10. The Si concentration is 1 × 10 ¹⁶ / cm ³ .

The p layer 12 (p body layer) is a 1.0 μm thick Mg-doped p-GaN layer stacked on the n layer 11. The Mg concentration is 2 × 10 ¹⁸ / cm ³ .

The second n layer (ohmic layer) 13 is a 0.3 μm thick Si-doped n-GaN layer stacked on the p layer 12. The Si concentration is 1 × 10 ¹⁸ / cm ³ .

  The trench 19 is a groove formed at a predetermined position of the semiconductor layer 20 and has a depth that penetrates through the second n layer 13 and the p layer 12 and reaches the first n layer 11. The first n layer 11 is exposed at the bottom surface 19 a of the trench 19, and the first n layer 11, the p layer 12, and the second n layer 13 are exposed at the side surface 19 b of the trench 19. The side surface of the p layer 12 exposed at the side surface 19b of the trench 19 is a region that operates as the channel of the FET of the first embodiment.

  The cross-sectional shape of the trench 19 is arbitrary, but it is desirable that the side surface 19b of the trench 19 be an m-plane of GaN. When the trench 19 is formed by dry etching, damage to the GaN is reduced and gate leakage can be reduced. Further, the side surface 19b of the trench 19 does not need to be perpendicular to the main surface of the substrate 10 and may be inclined.

The first insulating film 14 </ _b > A is made of SiO ₂ and is in contact with the first n layer 11 exposed at the corner 19 c of the trench 19. The first insulating film 14A has a triangular cross-sectional shape as shown in FIG. The triangle has a side having a length W (bottom side 140) from the corner 19c of the trench 19 along the bottom surface 19a of the trench 19, and a side having a length H along the side surface 19b of the trench 19 from the corner 19c (side 141). ), An inclined side (an oblique side 142) connecting one end P of the base 140 opposite to the corner 19c and one end Q of the side 141 opposite to the corner 19c. . Hereinafter, H is referred to as the height of the first insulating film 14A, and W is referred to as the width of the first insulating film 14A.

  The height from the bottom surface 19a of the trench 19 to the junction interface (pn interface 23) between the first n layer 11 and the p layer 12 is H0, and the height H of the first insulating film 14A is set lower than H0. Any value can be used as long as it is. That is, the first insulating film 14 </ b> A only needs to be formed at a height that does not contact the p layer 12 on the side surface 19 b of the trench 19.

  In the first embodiment, the first insulating film 14A has a triangular cross-sectional shape, but may be any shape as long as it is in contact with the corner portion 19c. For example, the shape may be a trapezoid, a quarter circle, a quarter ellipse, or a rectangle (see FIGS. 4A to 4D). However, it is desirable to use a triangular shape as in Example 1 from the viewpoint of improving the breakdown voltage.

  The ratio of the height H to the width W of the first insulating film 14A is desirably 0.2 to 0.5. By setting it within this range, the breakdown voltage can be further improved while improving the device performance. More preferably, it is 0.23-0.5, and still more preferably 0.23-0.3.

The second insulating film 14B is made of Al ₂ O ₃ and is provided in a film shape continuously on the bottom surface 19a of the trench 19, the first insulating film 14A, the side surface 19b of the trench 19, and the surface of the second n layer 13. Yes. The second insulating film 14B functions as a gate insulating film. The thickness of the second insulating film 14B is the same for all of the bottom surface 19a portion of the trench 19, the side surface 19b portion of the trench 19, and the portion on the first insulating film 14A (the corner portion 19c portion of the trench 19). Thickness. Its thickness t is 100 nm.

  The second insulating film 14B desirably has a small variation in thickness. The device performance can be further improved, and the breakdown voltage can also be improved. More desirably, the film thickness distribution is 2% or less with respect to the peak value.

Further, the height H and width W of the first insulating film 14A and the thickness t of the second insulating film 14B are desirably set as follows. As shown in FIG. 3, since the second insulating film 14B is formed on the first insulating film 14A, the vicinity of one end P of the first insulating film 14A and the vicinity of the upper end Q of the first insulating film 14A at the corner 19c of the trench 19 Bends at two locations. Of the surface of the second insulating film 14B at this bent portion, the bending point near the upper end Q is R, and the bending point near the lower end P is S. That is, the intersection of the inclined surface 144 of the region located on the first insulating film 14A in the second insulating film 14B and the surface 145 of the region along the side surface 19b of the trench 19 in the second insulating film 14B is R, Let S be the intersection of the surface 146 of the region along the bottom surface 19a of the trench 19 in the two insulating films 14B. At this time, the height H1 from the bottom surface 19a of the trench 19 to the intersection R is set so that H1 is smaller than the height H0 to the pn interface 23. Thus, by setting the height H and width W of the first insulating film 14A and the thickness t of the second insulating film 14B, it is possible to further improve the element performance and the breakdown voltage performance. Specifically, it is only necessary to set W, H, and t so that H1 = (W ² + H ² ) ^1/2 · t / W + H and H 0> H 1.

In Example 1, SiO ₂ is used as the first insulating film 14A and Al ₂ O ₃ is used as the second insulating film 14B. However, the dielectric breakdown strength of the first insulating film 14A is higher than that of the second insulating film 14B. Any combination of materials may be used as long as the relative dielectric constant of the second insulating film 14B is higher than the relative dielectric constant of the first insulating film 14A. Depending on the film formation method, SIO ₂ has a relative dielectric constant of 4, a dielectric breakdown strength of 10 MV / cm, Al ₂ O ₃ has a relative dielectric constant of 8, and a dielectric breakdown strength of 5 MV / cm. Meet.

As a specific material, for example, Al ₂ O ₃ , SiN, SiON, AlN, AlON, etc. can be used as the first insulating film 14A in addition to SiO ₂ . In addition to Al ₂ O ₃ , ZrON, SiN, SiON, HfO ₂ , AlN, AlON, SiO ₂ , ZrO ₂ or the like can be used as the second insulating film 14B.

  The ratio of the dielectric breakdown strength of the second insulating film 14B to the dielectric breakdown strength of the first insulating film 14A is desirably 1.1 to 5.0 times. By setting it as this range, the element performance and pressure | voltage resistance performance of the semiconductor device of Example 1 can be improved more. The ratio is more desirably 1.2 to 3.0 times, and further desirably 1.5 to 2.0 times. The dielectric breakdown strength of the first insulating film 14A is desirably 5 MV / cm or more, and more desirably 10 MV / cm or more.

  The difference between the relative dielectric constant of the second insulating film 14B and the relative dielectric constant of the first insulating film 14A is desirably 1-30. By setting it as this range, the element performance and pressure | voltage resistance performance of the semiconductor device of Example 1 can be improved more. More preferably, it is 2-20, and more preferably 3-15. The relative dielectric constant of the second insulating film 14B is preferably 6 or more, and more preferably 8 or more.

  The first insulating film 14A and the second insulating film 14B are not limited to a single layer, and may be a stacked layer. In the case of lamination, the effective dielectric breakdown strength and relative dielectric constant as a whole need only be set so as to satisfy the above-described conditions.

  Further, the second insulating film 14B is provided so as to cover the surface of the second n layer 13, and functions as a passivation film for preventing current leakage on the surface of the second n layer 13. A film may be provided. In that case, the second insulating film 14 </ b> B only needs to be continuously provided at least on the bottom surface 19 a of the trench 19, the first insulating film 14 </ b> A, and the exposed region of the p layer 12 on the side surface 19 b of the trench 19. It does not need to be provided in other regions of 19b or on the surface of the second n layer 13. Further, the second insulating film 14B may not be provided on the bottom surface 19a of the trench 19, and in that case, the bottom surface 19a may be covered with the first insulating film 14A. Eventually, the second insulating film 14B only needs to be formed so as to cover at least the first insulating film 14A at the corner 19c of the trench 19 and the channel region of the side surface 19b of the trench 19. .

  By providing the first insulating film 14A and the second insulating film 14B as described above, the breakdown voltage performance can be improved while improving the device performance such as the on-resistance and gm.

  The first reason is that since the first insulating film 14A and the second insulating film 14B overlap each other at the corner 19c of the trench 19, the entire insulating film at the corner 19c becomes thick. As a result, the electric field concentration at the bending point R and the bending point S of the second insulating film 14B is relaxed, and the withstand voltage performance is improved.

  Second, since the first insulating film 14A has a relative dielectric constant lower than that of the second insulating film 14B, the electric field concentration is dispersed in the first insulating film 14A, and the bending points R and S of the second insulating film 14B are reduced. Electric field concentration is reduced. Even if the electric field concentration occurs in the first insulating film 14A, the dielectric breakdown strength of the first insulating film 14A is higher than that of the second insulating film 14B, and therefore the insulation between the second insulating film 14B and the first insulating film 14A. The breakdown voltage is higher than when the breakdown strength is the same, and the effect of improving the breakdown voltage due to the electric field relaxation at the bending points R and S of the second insulating film 14B can be sufficiently obtained. As a result, the pressure resistance performance is further improved.

  Third, the entire exposed surface of the p layer 12 exposed at the side surface 19b of the trench 19 is covered and covered with the second insulating film 14B. Therefore, the gate electrode 15 faces the p layer 12 on the side surface 19b of the trench 19 that is the channel region, with the second insulating film 14B interposed therebetween. Here, since the relative dielectric constant of the second insulating film 14B is higher than that of the first insulating film 14A, the gate capacitance becomes larger than the case where the first insulating film 14A is interposed between the gate electrode 15 and the channel region, Device performance such as on-resistance and gm is improved.

  The gate electrode 15 is provided in a film shape continuously on the bottom surface 19 a of the trench 19, the side surface 19 b of the trench 19, and the top surface of the trench 19 through the second insulating film 14 </ b> B. The upper surface of the trench 19 is a region on the surface of the second n layer 13 and in the vicinity of the side surface 19b of the trench 19. The gate electrode 15 is made of Al.

  The p body electrode 21 is continuously provided on a partial region of the second n layer 13 and on the p layer 12 exposed by the recess 22. The p body electrode 21 is made of Pd.

  The source electrode 17 is continuously provided over the p body electrode 21 and a partial region on the second n layer 13. The source electrode 17 is a conductive material that makes ohmic contact with the second n layer 13 and is made of Ti / Al. Ti / Al / Ni / Au, TiN / Al, Pd / Ti / Al, Ti / Al / Pd, and the like can also be used.

  The drain electrode 18 is provided in contact with the back surface of the substrate 10 (the surface opposite to the side on which the first n layer 11 is provided). The material of the drain electrode 18 is a conductive material that makes ohmic contact with the substrate 10, and is the same material as the source electrode 17. Of course, different materials may be used for the source electrode 17 and the drain electrode 18 as long as the material is in ohmic contact.

  As described above, in the semiconductor device of Example 1, the first insulating film 14A and the second insulating film 14B are provided as described above, whereby the breakdown voltage can be improved while improving the element performance.

  Next, a method for manufacturing the semiconductor device of Example 1 will be described with reference to FIG.

First, the first n layer 11, the p layer 12, and the second n layer 13 are sequentially stacked on the substrate 10 by MOCVD to form the semiconductor layer 20 (see FIG. 5.A). In the MOCVD method, the nitrogen source is ammonia, the Ga source is trimethylgallium (Ga (CH ₃ ) ₃ : TMG), the In source is trimethylindium (In (CH ₃ ) ₃ : TMI), and the Al source is trimethylaluminum. (Al (CH ₃ ) ₃ : TMA). The n-type dopant gas is silane (SiH ₄ ), and the p-type dopant gas is cyclopentadienyl magnesium (Mg (C ₅ H ₅ ) ₂ : CP ₂ Mg). The carrier gas is hydrogen or nitrogen. Thereafter, the p layer 12 is made p-type by heating in a nitrogen atmosphere.

  Next, the trench 19 and the recess 22 are formed by dry etching a predetermined position of the semiconductor layer 20 (see FIG. 5.B). The trench 19 is performed until the first n layer 11 is exposed through the second n layer 13 and the p layer 12. The recess 22 is performed until the p layer 12 is exposed. Either the trench 19 or the recess 22 may be formed first. Since the damaged layer is formed on the side surface 19b of the trench 19 and the side surface of the recess 22 by this dry etching, the damaged layer may be removed by wet etching. Current leakage through the side surface can be reduced. In this case, TMAH (tetramethylammonium hydroxide) or the like can be used as a wet etching solution.

Next, a first insulating film 14A made of SiO ₂ is formed on the entire surface of the semiconductor layer 20 by sputtering (see FIG. 5.C). That is, the first insulating film 14 </ b> A is formed in a film shape continuously from the bottom surface 19 a and the side surface 19 b of the trench 19, the surface of the second n layer 13, and the side surface and bottom surface of the recess 22. Besides the sputtering method, a CVD method or the like can be used. Here, the first insulating film 14A formed on the side surface 19b of the trench 19 and the side surface of the recess 22 is thinner than the first insulating film 14A formed on the bottom surface 19a of the trench 19 and the surface of the second n layer 13. It is good to form like this. In the next step, it is easy to leave the first insulating film 14 </ b> A only at the corner 19 c of the trench 19. Such a difference in thickness can be easily set by selecting a film forming method and film forming conditions for the first insulating film 14A. In particular, if it is formed by sputtering, such a thickness can be easily obtained.

  Next, the first insulating film 14A is dry-etched using a fluorine-based gas. Here, it is difficult for the etching gas to reach the corner 19 c of the trench 19. Therefore, by adjusting the etching conditions such as the etching time and the etching rate, the first insulating film 14A is left only in the corner portion 19c of the trench 19 so that the first insulating film 14A does not contact the p layer 12. Yes (see Fig. 5.D). Note that the etching of the first insulating film 14A may not be dry etching, but the use of dry etching makes it easy to leave the first insulating film 14A in this way. In particular, it is desirable to use anisotropic dry etching, and anisotropic dry etching using a fluorine-based gas as in Example 1 is suitable.

Next, the second insulating film 14B made of Al ₂ O ₃ is formed by the ALD method except for the region where the source electrode 17 and the p body electrode 21 are formed on the semiconductor layer 20 (see FIG. 5.E). . The second insulating film 14B is patterned by etching. As a result, the second insulating film is continuously formed in a film shape on the bottom surface 19 a of the trench 19, the first insulating film 14 A at the corner 19 c, the side surface 19 b, and the surface of the second n layer 13 (excluding the source electrode 17 formation region). 14B is formed. Note that ozone or oxygen plasma is preferably used as an oxygen source in the ALD method. The second insulating film 14B can be grown at a lower temperature, and the film thickness uniformity and film quality can be improved. Further, the second insulating film 14B may be formed not by the ALD method but by the CVD method or sputtering.

  Next, the gate electrode 15, the p body electrode 21, and the source electrode 17 are formed in this order using a lift-off method. Further, the drain electrode 18 is formed on the back surface of the substrate 10 using a lift-off method (see FIG. 5.F). The order of forming these electrodes is not limited to this order, and may be formed in any order.

  Next, a protective film (not shown) is formed so as to cover the entire upper surface of the element, and a contact hole is formed by dry-etching a region of the protective film that corresponds to the upper portion of the source electrode 17 to be connected to the source electrode 17. A wiring electrode (not shown) is formed. Thus, the semiconductor device of Example 1 is manufactured.

  Next, simulation results regarding the semiconductor device of Example 1 will be described.

For the semiconductor devices of Example 1 and Comparative Examples 1 to 3, the electric field strength applied to the bending point of the second insulating film 14B was calculated by simulation with a drain-source voltage of 500V. Comparative Example 1 is a semiconductor device of Example 1 in which only the second insulating film 14B made of Al ₂ O ₃ is provided without providing the first insulating film 14A. There is one bending point on the surface of the second insulating film 14B, and the intersection of the surface 145 of the region along the side surface 19b of the trench 19 and the surface 146 of the region along the bottom surface 19a of the trench 19 of the second insulating film 14B is the bending point. T (see FIG. 6A). In Comparative Example 2, in the semiconductor device of Example 1, the first insulating film 14A is made of the same material as the second insulating film 14B by replacing Al ₂ O ₃ instead of SiO ₂ (FIG. 6B). reference). In Comparative Example 3, in the semiconductor device of Example 1, the first insulating film 14A is provided not on the first n layer 11 but on the second insulating film 14B at the corner 19c of the trench 19 (FIG. 6). (See (c)). In Comparative Example 3, the intersection of the surface 145 of the region along the side surface 19b of the trench 19 in the second insulating film 14B and the oblique side of the first insulating film 14A is R, the surface 146 of the region along the bottom surface 19a of the trench 19 and the first Let S be the intersection with the hypotenuse of one insulating film 14A. In Example 1 and Comparative Examples 1 to 3, the height H0 from the bottom surface 19a of the trench 19 to the pn interface 23 was 300 nm, and the thickness of the Al ₂ O ₃ film of the second insulating film 14B was 100 nm. In Example 1 and Comparative Examples 2 and 3, the first insulating film 14A had a height H of 50 nm and a width W of 200 nm.

  7 shows the electric field strength applied to the bending point T of the second insulating film 14B in Comparative Example 1, the bending point R and the bending point of the second insulating film 14B in the semiconductor devices of Example 1 and Comparative Examples 2 and 3. FIG. 4 is a graph showing a higher electric field strength among electric field strengths applied to S. The electric field strength was expressed as a ratio where the electric field strength at the bending point T in Comparative Example 1 was 1.

  As shown in FIG. 7, it was found that the electric field strength was lower in Comparative Example 2 and Example 1 than in Comparative Example 1, and the electric field was relaxed. On the other hand, in Comparative Example 3, it was found that the electric field strength increased compared to Comparative Example 1. In Comparative Example 2, although the electric field is relaxed, the electric field strength is reduced by 6% compared to Comparative Example 1, and it cannot be said that the electric field is sufficiently relaxed. Further, in Example 1, the electric field strength was reduced by 12% compared to Comparative Example 1, and it was found that the electric field was sufficiently relaxed.

  In addition, the result of calculating the maximum electric field strength inside the first insulating film 14A of Example 1 under the conditions of FIG. 7 is only about 8% lower than the electric field strength at the bending point T of Comparative Example 1 of FIG. It was. For this reason, if the dielectric breakdown strength of the first insulating film 14A and the second insulating film 14B is the same, the effect of electric field relaxation cannot be sufficiently obtained. However, in Example 1, since the dielectric breakdown strength of the first insulating film 14A is sufficiently higher than that of the second insulating film 14B, the electric field relaxation effect at the bending point R and the bending point S of the second insulating film 14B is sufficient. It is possible to get to.

  Next, for the semiconductor devices of Comparative Examples 1 to 3 and Example 1, the drain-source voltage was calculated by setting the drain-source voltage to 0.5 V and changing the gate voltage. FIG. 8 is a graph showing drain current-gate voltage characteristics of the semiconductor devices of Example 1 and Comparative Examples 1-3.

  As shown in FIG. 8, it was found that the semiconductor device of Example 1 showed no significant deterioration in on-resistance or gm.

  From the above results, it was found that in the semiconductor device of Example 1, the gate breakdown voltage was improved while improving the element performance such as the on-resistance and gm.

Next, regarding the semiconductor device of Example 1, the electric field strength applied to the bending point R and the bending point S of the second insulating film 14B was examined by changing the height H and the width W of the first insulating film 14A. The height H0 from the bottom surface 19a of the trench 19 to the pn interface 23 was 700 nm, and the thickness of the Al ₂ O ₃ film as the second insulating film 14B was 100 nm. The drain-source voltage was 500V.

  First, the height H is fixed at 200 nm, the width W is changed, and the ratio of the height H to the width W (H / W) is 0.20, 0.25, 0.50, 1.00, 2. Changed to 00. As a result, among the electric field strengths applied to the bending point R and the bending point S of the second insulating film 14B, the higher electric field strength is as shown in FIG. In FIG. 9, the electric field strength is expressed as a ratio where the electric field strength at the bending point T of Comparative Example 1 is 1.

  As shown in FIG. 9, when the ratio of the height H to the width W is 0.20 and 0.25, the electric field strength is reduced by about 15% compared to the comparative example 1, and the electric field is relaxed. I understood it. When the ratio of the height H to the width W was 0.50, the electric field strength was about 5% lower than that of Comparative Example 1, and it was found that the electric field was slightly relaxed. On the other hand, when the ratio of the height H to the width W is 1.00, the electric field strength is increased as compared with Comparative Example 1, and when it is 2.00, the electric field strength is substantially equal to that of Comparative Example 1. Was found not to be relaxed.

  Further, the width W is fixed at 200 nm, the height H is changed, and the ratio of the height H to the width W (H / W) is 0.20, 0.25, 0.50, 1.00, 2. Changed to 00. As a result, as shown in FIG. 10, when the ratio of the height H to the width W is 0.20, the electric field strength is reduced by about 20% compared to the comparative example 1, and when the ratio is 0.25, it is about 15%. When the reduction ratio was 0.50, the electric field was reduced by about 25%. Further, it was found that when the ratio of the height H to the width W was 1.00 and 2.00, the electric field strength increased as compared with Comparative Example 1, and the electric field was not relaxed.

  From the above results, it was found that the ratio of the height H to the width W is preferably 0.2 to 0.5, and more preferably 0.2 to 0.25.

(Various modifications)
The present invention can be applied not only to a trench gate structure but also to a groove in which a body layer is exposed at a part of a side surface, and can also be applied to a mesa groove. For example, the present invention can be applied to a termination structure in which a mesa groove is provided on the outer periphery of the element. When applied to the termination structure, the second insulating film functions as a passivation film or a protective film. FIG. 11 illustrates a configuration in which the mesa groove 30 is provided as the termination structure in the semiconductor device according to the first embodiment. The mesa groove 30 is a groove obtained by etching the outer periphery of the element region until it reaches the first n layer 11 so that the first n layer 11, the p layer 12, and the second n layer 13 have a plateau shape. Similar to the first insulating film 14A of the first embodiment, the first insulating film 34A is provided at the corner 30c of the mesa groove 30. Further, a second insulating film 34B similar to the second insulating film 14B is formed continuously in a film shape on the bottom surface 30a of the mesa groove 30, the first insulating film 34A, the side surface 30b of the mesa groove 30, and the surface of the second n layer 13. Is provided. With such a termination structure, the breakdown voltage performance can be improved while improving the element performance.

  The semiconductor device of the embodiment is a MISFET, but the present invention is not limited to this, and any semiconductor device can be used as long as the semiconductor layer has a groove and the body layer is exposed on the side surface of the groove. Is possible. For example, the present invention can be applied to semiconductor devices such as IGBTs and HFETs. The present invention is also effective when the semiconductor device of Example 1 has a structure in which the conductivity type is reversed. Further, although the first embodiment is a vertical semiconductor device that conducts in the vertical direction of the substrate, the present invention can also be applied to a horizontal semiconductor device that conducts in the horizontal direction of the substrate.

  Although the semiconductor device of Example 1 uses a group III nitride semiconductor as a semiconductor layer, the present invention is not limited to this, and can be applied to a semiconductor device using any semiconductor material. For example, the present invention can also be applied to SiC, Si, SiGe, III-V semiconductors. The present invention is suitable when a group III nitride semiconductor or SiC, which is a high breakdown voltage semiconductor material, is used, and particularly when a group III nitride semiconductor is used.

  The semiconductor device of the present invention can be used for a power device or the like.

10: substrate 11: first n layer 12: p layer 13: second n layer 14A: first insulating film 14B: second insulating film 15: gate electrode 16: passivation film 17: source electrode 18: drain electrode 19 : Trench 20: Semiconductor layer 21: p body electrode

Claims (11)

In a semiconductor device in which a semiconductor layer having a body layer is provided with a groove penetrating the body layer, and the body layer is exposed at a part of a side surface of the groove.
A first insulating film provided in contact with a corner of the groove and not in contact with the body layer exposed on a side surface of the groove;
The body layer exposed on the side surface of the groove, and a second insulating film provided to continuously cover the first insulating film;
Have
The dielectric breakdown strength of the first insulating film is higher than the dielectric breakdown strength of the second insulating film,
The relative dielectric constant of the second insulating film is higher than the relative dielectric constant of the first insulating film,
A semiconductor device. The groove is a trench groove;
On the second insulating film, a gate electrode is provided along the bottom and side surfaces of the groove.
The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the groove is a mesa groove provided at a terminal portion of the semiconductor device.   4. The ratio according to claim 1, wherein a ratio of a height of the first insulating film to a width of the first insulating film is 0.2 to 0.5. 5. Semiconductor device. The first insulating film is made of SiO ₂ , and the second insulating film is Al ₂ O ₃ , ZrON, AlON, ZrO ₂ , HfO ₂ or HfON. 2. The semiconductor device according to claim 1.   6. The semiconductor device according to claim 1, wherein the semiconductor device has a vertical structure that conducts in a direction perpendicular to a main surface of the semiconductor layer.   The semiconductor device according to claim 1, wherein the semiconductor layer is made of a group III nitride semiconductor. In the semiconductor device manufacturing method in which a semiconductor layer having a body layer is provided with a groove penetrating the body layer, and the body layer is exposed at a part of a side surface of the groove.
A first step of forming a first insulating film in a film shape continuously on the bottom surface, side surface, and surface of the semiconductor layer of the groove;
After the first step, by etching, the first insulating film is left at the corner of the groove so as not to contact the body layer on the side surface of the groove, and the first insulating film in the other region is removed; ,
After the second step, a third step of forming the second insulating film so as to continuously cover the body layer exposed on the side surface of the groove and the first insulating film;
A method for manufacturing a semiconductor device, comprising:   In the first step, the first insulating film is formed so that a thickness of a side surface region of the groove is smaller than a thickness of a bottom surface of the groove and a surface region of the semiconductor layer. A method for manufacturing a semiconductor device according to claim 8.   10. The method of manufacturing a semiconductor device according to claim 8, wherein in the second step, the etching is anisotropic dry etching. 11. The method of manufacturing a semiconductor device according to claim 8, wherein, in the third step, the second insulating film is formed by an ALD method.