CN102024848A - Trench structure for power device and manufacturing method thereof - Google Patents
Trench structure for power device and manufacturing method thereof Download PDFInfo
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- CN102024848A CN102024848A CN 201010531584 CN201010531584A CN102024848A CN 102024848 A CN102024848 A CN 102024848A CN 201010531584 CN201010531584 CN 201010531584 CN 201010531584 A CN201010531584 A CN 201010531584A CN 102024848 A CN102024848 A CN 102024848A
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Abstract
The invention discloses a groove structure for a power device and a manufacturing method thereof. The groove structure disclosed by the invention has the characteristics that the side wall is vertical or slightly downslope (theta is 80-90 degrees), the silicon oxide film is thin, the bottom is smooth, the silicon oxide film is thick, doped polycrystal is filled without gaps, the interface defect is eliminated, and the surface of a silicon wafer at the groove is free of steps or has small steps. The manufacturing method of the groove structure comprises the steps of forming a groove through dry etching, removing defects on the surface of the groove through an oxidation process, forming a side wall of the groove through a silicon nitride film, forming a silicon oxide film with thick bottom and thin side wall in the groove through selective oxidation, wet etching and reoxidation, filling a polycrystalline silicon film with good conductivity in a gapless mode, and removing redundant polycrystalline silicon film outside the groove through an etching or chemical mechanical polishing process to form the groove structure required by the groove type power device. The manufacturing method has simple and stable process and is easy to realize; the manufactured device has the advantages of small area, good electrical property and performance and the like.
Description
Technical field
The present invention relates to the structure and the manufacture method of power device, particularly a kind of groove structure and manufacture method thereof that is used for power device.
Background technology
In order to dwindle the size of power device, improve the performance of power device, groove structure is introduced in the power device.As groove metal oxide semiconductor field effect transistor (Trench MOSFET), insulated trench gate bipolar transistor (Trench IGBT), groove MOS control thyristor similar devices such as (Trench MCT).
Aspect trench technique,, all had more patent no matter be to be applied in the MOSFET device, or to be applied in IGBT or other power device aspect.Just realize in the patent of channel bottom dielectric film thickness than trenched side-wall dielectric thickness; existing multinomial with silicon nitride film: 1, United States Patent (USP) (US4 as the patent of sidewall protection; 914; 058) discloses and a kind ofly protected as sidewall with silicon nitride film; do the secondary etching groove at channel bottom; and, realize the structure and the manufacture method thereof of the different silicon oxide film thickness of trenched side-wall with the bottom at bottom partial thermal oxidation grow thick silicon oxide film.2, United States Patent (USP) (US5; 442; 214) disclose and a kind ofly done trenched side-wall protection with silicon nitride film; trenched side-wall thin silicon oxide film is covered; at channel bottom grow thick silicon oxide film; silicon nitride film still is retained in trenched side-wall, realizes the structure and the manufacture method thereof of the different silicon oxide film thickness with the bottom of trenched side-wall.3, United States Patent (USP) (US5; 473; 176) disclosing a kind of groove top is V font structure, the gradual change of side wall silicon oxide film thickness; the bottom is vertical trench, is protected as sidewall by silicon nitride film; remove the silicon nitride of bottom and following silica thereof with dry etching; again at the thicker silicon oxide film of channel bottom growth fraction sidewall; remove the silicon nitride film of sidewall then; regrowth silicon oxide film is afterwards realized the groove structure and the manufacture method thereof of the different silicon oxide film thickness with the bottom of trenched side-wall.4, United States Patent (USP) (US5; 770; 878) a kind of sidewall protection of doing groove with silicon nitride film is disclosed; trenched side-wall thin silicon oxide film is covered; at channel bottom grow thick silicon oxide film; as dielectric insulating film, realize the structure and the manufacture method of the different silicon oxide film thickness of trenched side-wall with the thick silicon oxide film of thin silicon oxide film under the former silicon nitride film and channel bottom with the bottom.
With reference to accompanying drawing 1,2,3,4, in the foregoing invention patent, thick silicon oxide film 101 forms at lower channel 102 etching rear oxidations under the structure shown in the accompanying drawing 1, thin silicon oxide film 103 is that upper groove 104 forms rear oxidation formation, after lower channel is handled, kept time, inserted doped polycrystalline silicon 105 at last; Thick silicon oxide film 201 forms at channel bottom secondary etching groove rear oxidation under the structure shown in the accompanying drawing 2, be retained as the silicon nitride film 202 of secondary trenched side-wall protection and the thin silicon oxide film 203 that covers thereof, in groove, insert polysilicon membrane 204 afterwards, after the outer polysilicon membrane etching of groove, cover one deck silicon oxide film 205 in flute surfaces; Structure shown in the accompanying drawing 3 is to form top triangular groove 301 and silicon oxide film 302 earlier, form bottom U type groove 303 with dry etching more afterwards, form thin silicon oxide film 304 on the lower channel surface after the oxidation, form thick silicon oxide film 305 with silicon nitride film as being sequestered in the channel bottom selective oxidation, keep sidewall thin silicon oxide film 304 after removing silicon nitride film, in groove, insert doped polycrystalline silicon 305 at last; Structure shown in the accompanying drawing 4 is to form groove 401 earlier, oxidation afterwards forms very thin silicon oxide film, and with silicon nitride film as sheltering, form thick silicon oxide film 402 at the channel bottom selective oxidation, after removing silicon nitride film, on silicon oxide film basis very thin under the former silicon nitride, continue oxidation and form thin silicon oxide film 403, in groove, insert doped polycrystalline silicon film 404 at last.
In above-mentioned patent of invention, still there is certain deficiency.U.S. Pat 4,914,058 and US5,770,878 weak point is that the silicon oxide film under the silicon nitride film has kept at last, to keep the state thinner than bottom silicon oxide film, U.S. Pat 5,473,176 in the end carry out also not removing when oxidation forms sidewall thin silicon oxide film the silicon oxide film under the former silicon nitride film.And when channel bottom and silicon chip surface silicon nitride film are carried out dry etching, deterioration takes place in this layer silicon oxide film under the silicon nitride film easily in technology, especially when intact this layer silica of silicon nitride film etching is exposed in the plasma environment, such deterioration causes gate-to-source easily, and perhaps the leakage current between grid-emitter increases.U.S. Pat 5,442,214 weak point is, silicon nitride film still is retained in trenched side-wall, this gives capacitor C gs between the threshold voltage of device and gate-to-source, and perhaps capacitor C ge has increased the factor of change between grid-emitter, that is to say, these electrical quantitys also can be subjected to the influence of silicon nitride film change except the influence that is subjected to the silicon oxide film change; Simultaneously, the deterioration problem that also has silica under the aforesaid silicon nitride film.U.S. Pat 5,473,176 weak point be, on the one hand, difficult aligning the between lower channel and top V font structure, the difference that departs from generation both sides V font dielectric film thickness that engraves because of cover easily, thus device performance is changed; On the other hand, after the silicon nitride film etching of lower channel bottom, continue on the silicon face that exposes, to produce damage defect easily with the dry etching method that the silicon oxide film etching is intact, and under follow-up high-temperature oxydation condition, in device, grow easily, cause element leakage.
Summary of the invention
In order to overcome defective and the deficiency that above-mentioned prior art exists, the invention discloses a kind of groove structure and manufacture method thereof that is used for power device.Groove structure disclosed by the invention can be applicable in the multiple power device, power device with groove structure, can be by groove structure with horizontal raceway groove or other transversary part, change longitudinal channel into or realize with vertical structure, the lateral dimension of these parts can be dwindled like this, thereby realize dwindling of overall chip size; Perhaps under the situation of same size, place more unit and part, thereby can reach the raising current density, reduce conducting voltage, improve the effect of device electrical characteristics.
The characteristics of groove structure of the present invention are: according to the needs of design, etch groove at silicon chip surface with anisotropic method, insert one deck insulating medium layer, be generally silicon oxide film, perhaps silicon nitride film, the perhaps combination of these films, the polysilicon membrane that growth one deck conducts electricity very well on dielectric insulating film is removed the outer unnecessary polysilicon membrane of groove with etching or chemico-mechanical polishing (CMP) method at last then.
According to the characteristics of power device and groove structure as can be known: because its special shape makes electric field be easy to concentrate in this position, need thicker dielectric film thickness to puncture at this to prevent device at channel bottom; In addition, the dielectric film thickness that channel bottom is thicker can reduce parasitic capacitance Cgd between grid-drain electrode or the parasitic capacitance Cgc between grid-collector electrode, and this helps improving device performance.Therefore, require usually to realize such structure that promptly the dielectric layer thickness of channel bottom is more typically got 1 ~ 1.2 times more than or equal to the dielectric layer thickness of trenched side-wall.Trenched side-wall silicon oxide film thin thickness, in order to reduce the electric leakage of trenched side-wall, the trenched side-wall defective is eliminated, and growth is fine and close, high-quality sidewall oxidation silicon thin film is also extremely important.
Substrate, the perhaps face of epitaxial silicon chip different crystal orientations, oxidation rate is had nothing in common with each other.Usually the crystal orientation is that 100 face oxidation rate is slower than 110, and 110 then slow than 111.Therefore choosing the trenched side-wall crystal orientation is 100, and the crystal orientation, bottom also is 100; Perhaps the sidewall crystal orientation is 100, and the crystal orientation, bottom is 110; Perhaps the sidewall crystal orientation is 110, and the crystal orientation, bottom is 111, can be implemented under the identical heat-treat condition, and the silicon oxide film of channel bottom growth is greater than or equal to the silicon oxide film thickness of sidewall growth.Suitably choose the crystal orientation, can also realize that trench bottom corner is thicker than the silicon oxide film of sidewall growth with the silicon oxide film of top corner place growth.In addition, choosing trenched side-wall is 100 crystal orientation, can make sidewall silicon oxidation speed slower, and silicon oxide film is fine and close more, and the silicon face mobility is higher at the interface, and performance is better.
The present invention adopts the method etching groove of anisotropic dry etch (normally reactive ion etching is RIE), groove width and depth controlled, and sidewall is vertically or slightly along the slope, the bottom does not have obvious projection and depression; Behind sacrificial oxidation process and bottom selective oxidation processes, sidewall is still vertically or slightly along the slope, but the bottom becomes slick and sly, and the thicker silicon oxide film of one deck of having grown; After finishing final step oxidation technology of the present invention, realized the growth of sidewall high-quality silicon oxide film, and reached the design feature that the sidewall oxidation silicon thin film is thin, the bottom is slick and sly, silicon oxide film is thick.
After the groove dry etching, exist damage defect on the silicon top layer of groove, the present invention adopts sacrificial oxidation to remove these damage defects; In addition, when channel bottom silicon nitride film dry etching, though there is certain over etching amount in the silicon nitride dry etching, to guarantee that silicon nitride film still can be by fully etching is clean when certain technological fluctuation, but still kept certain thickness silicon oxide film under the channel bottom silicon nitride, thereby prevented that dry etching from bringing damage to silicon face.According to requirement on devices, the silicon oxide film that this layer remains also can be removed by wet etching.
After final step oxidation technology of the present invention was finished, the groove top of this moment had identical width with the groove bottom, and perhaps groove top is slightly wideer than the width of groove bottom.There is not cavity, seamless in the doped polycrystalline silicon film filling groove to conduct electricity very well, and groove then; Perhaps, impurity is mixed the un-doped polysilicon film, form the doped polycrystalline silicon film that conducts electricity very well, and do not have empty, seamless in the groove with the method for ion injection or High temperature diffusion with un-doped polysilicon film filling groove.Remove the outer doped polycrystalline silicon film of groove with the gaseous plasma dry etching method afterwards, perhaps remove the outer doped polycrystalline silicon film of groove, keep groove place silicon chip surface not have step, less step is perhaps arranged with chemico-mechanical polishing (CMP) method.
The technical scheme that the present invention is taked for achieving the above object is: a kind of groove structure that is used for power device, it is characterized in that: the sidewall on silicon chip vertically or sidewall slightly along the slope and along angle of slope θ=80～90 °, there is one deck to select the thick silicon oxide film and the thin silicon oxide film of sidewall in bottom of growth in the groove of bottom slyness, zero-clearance is filled polysilicon membrane on the silicon oxide film in groove, form no step or be formed on 1000 dusts at groove place silicon chip surface, stay one deck silicon oxide film on the silicon chip surface outside groove with interior less step appearance.
A kind of groove structure manufacture method that is used for power device is characterized in that: comprise the steps:
(1), selects silicon chip;
(2), masking graphics forms; Etching groove, remove photoresist or masking film is removed;
(3), cleaning, sacrificial oxidation, silica etching;
(4), cleaning, oxidation, silicon nitride growth; The silicon nitride dry etching;
(5), cleaning, oxidation; Silica etching, silicon nitride etch, silica etching;
(6), cleaning, oxidation;
(7), polysilicon deposit;
(8), the groove polysilicon is removed.
The beneficial effect that the present invention produced is: groove structure disclosed by the invention has sidewall and vertically or slightly approaches along slope, silicon oxide film, the bottom is slick and sly, silicon oxide film is thick, the silicon interface defective is eliminated, side wall silicon oxide film quality height, the good polysilicon membrane of zero-clearance filled conductive performance on the silicon oxide film in the groove, characteristics such as groove place surface step is little.There is not groove alignment problem in trench fabrication methods disclosed by the invention, and has removed the silicon oxide film under the silicon nitride film of deterioration, keeps the silicon nitride film that influences threshold voltage, and there is not etching injury in the channel bottom silicon face.This manufacturing approach craft is simple, stable, is easy to realize; The device that produces has advantages such as area is little, and the electrical characteristics performance is good.Thereby satisfy the quality requirements of market to slot type power device.
Description of drawings
Fig. 1: the groove structure schematic diagram of inventing (US4,914,058) in the past.
Fig. 2: the groove structure schematic diagram of inventing (US5,442,214) in the past.
Fig. 3: the groove structure schematic diagram of inventing (US5,473,176) in the past.
Fig. 4: the groove structure schematic diagram of inventing (US5,770,878) in the past.
Fig. 5: groove structure schematic diagram of the present invention.
Fig. 6 A～6J: the manufacturing embodiment schematic diagram of groove structure of the present invention.
Fig. 7: a kind of manufacture method flow chart of groove structure of the present invention.
Fig. 8: the another kind of manufacture method flow chart of groove structure of the present invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples:
With reference to Fig. 5, the groove structure that is used for power device be on silicon chip 500 sidewall vertically or sidewall slightly along the slope and along angle of slope θ=80～90 °, the groove of bottom slyness is (wide: micron or sub-micron, the degree of depth: 1～10 micron) there is in 501 one deck to select the thick silicon oxide film 502 and the thin high-quality silicon oxide film 503 of sidewall in bottom of growth, the good doped polycrystalline silicon film 504 of zero-clearance filled conductive performance on the silicon oxide film 503 in groove 501, after the polysilicon membrane of groove place silicon chip surface is removed, silicon chip surface forms no step or is formed on 1000 dusts with interior less step appearance 505, when removing the outer polysilicon membrane of groove, stay one deck silicon oxide film 506 on the silicon chip surface, injury-free to guarantee silicon face.
The groove structure manufacture method that is used for power device disclosed by the invention comprises two kinds, the fundamental difference of two kinds of manufacture methods be in above-mentioned eight steps second step.Following with reference to Fig. 6 A～6H and Fig. 7, the present invention is wherein a kind of, and to be used for the concrete processing step of groove structure manufacture method of power device as follows:
1, selects silicon chip: select to be used to realize that channel bottom, trench bottom corner and top corner place grow the substrate of the different crystal orientations of the silicon oxide film thicker than trenched side-wall, perhaps epitaxial silicon chip, according to requirement on devices, select molten (FZ) silicon substrate of vertical pulling (CZ) or district in suitable crystal orientation, perhaps epitaxial silicon chip, selecting silicon chip surface is 100, and locating flat limit (OrientationFlat) tangent plane also is 100; Perhaps selecting silicon chip surface is 110, and locating flat limit tangent plane is 100; Perhaps selecting silicon chip surface is 111, locating flat limit tangent plane is 110, the silicon chip that uses as the present invention (Fig. 6 A～6H 600), silicon chip surface are burnishing surface (Fig. 6 A～6H 601), add a certain amount of hydrogen peroxide cleaning silicon chip and keep the silicon chip cleaning with ammoniacal liquor, hydrochloric acid.
2, masking graphics forms: do at silicon chip surface elder generation growth one deck silica and shelter film, one deck silicon nitride of perhaps growing is done and is sheltered film, utilizing photoresist to do then shelters, utilize carbon tetrafluoride, fluoroform gaseous plasma to carry out dry etching to sheltering film, perhaps utilize the hydrofluoric acid inhibiting solution, perhaps hot phosphoric acid and hydrofluoric acid inhibiting solution combinatorial chemistry soup carry out wet etching to sheltering film, afterwards, with photoresist and shelter film as sheltering, perhaps remove photoresist, shelter film as sheltering with this figure.
With high temp. dry type oxidation, perhaps wet oxidation, the perhaps compound mode of dry type oxidation and wet oxidation, perhaps with low pressure chemical vapor deposition (LPCVD) method, perhaps plasma chemical vapour deposition method growing silicon oxide film on silicon chip surface 601, the perhaps combination of silicon oxide film and silicon nitride film is called masking film (Fig. 6 A 602) at this.On masking film 602, be coated with the last layer photoresist, perhaps other resist (Fig. 6 A 603), with exposure, develop or similarly method perhaps form needed figure on other resist 603 at photoresist.To form the photoresist of figure, perhaps other resist 603 is done and is sheltered, utilize carbon tetrafluoride, fluoroform, perhaps sulphur hexafluoride, fluoroform, perhaps their composition gas adds the plasma dry etching of mist generation of gas with some other, perhaps utilize the hydrofluoric acid inhibiting solution, the wet etching method of perhaps hot phosphoric acid and the combination of hydrofluoric acid inhibiting solution, masking film 602 etchings in masked place not are clean, afterwards with hot sulfuric acid, hydrogen peroxide admixing medical solutions corroding method, perhaps with oxygen gas plasma ashing and hot sulfuric acid, the method of hydrogen peroxide admixing medical solutions corrosion combination is removed photoresist, perhaps other resist 603; Perhaps keep photoresist, perhaps other resist 603 is on masking film 602.
3, etching groove, masking film are removed: utilize Nitrogen trifluoride, perhaps the chlorine gaseous plasma carries out anisotropic dry etching to the silicon chip top layer, form groove, remove then with photoresist and masking film and do photoresist and the masking film of sheltering, perhaps remove with masking film and do the masking film of sheltering.
With masking film 602 as sheltering, utilize Nitrogen trifluoride, perhaps chlorine, perhaps sulphur hexafluoride, perhaps their composition gas adds the plasma of mist generation of gas with some other, anisotropically silicon chip surface 601 is carried out dry etching (being generally reactive ion etching is RIE), form the groove that width, the degree of depth meet design requirement (Fig. 6 B～6H 604), silicon chip surface 601 stays the remaining masking film of dry etching (Fig. 6 B 605), the perhaps photoresist on it, perhaps other resist.With hot sulfuric acid, hydrogen peroxide admixing medical solutions corroding method, perhaps the method that makes up with oxygen gas plasma ashing and hot sulfuric acid, the corrosion of hydrogen peroxide admixing medical solutions is removed photoresist, perhaps other resist; With the hydrofluoric acid inhibiting solution, the wet etching method of perhaps hot phosphoric acid and the combination of hydrofluoric acid inhibiting solution is removed the remaining masking film 605 of dry etching.
4, clean, sacrificial oxidation, silica etching: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, with hydrofluoric acid inhibiting solution chemical liquid wet etching, remove the silicon oxide film of this secondary growth fully.
The chemical liquid that adds a certain amount of hydrogen peroxide with ammoniacal liquor, hydrochloric acid is to cleaning on the silicon chip surface 601 and in the groove 604, and with high temp. dry type oxidation, perhaps wet oxidation, perhaps the compound mode of dry type oxidation and the wet oxidation one deck silicon oxide film (Fig. 6 C 606) of growing in silicon chip surface and groove 604 is removed this layer silicon oxide film 606 with hydrofluoric acid inhibiting solution wet etching method afterwards.
5, clean, oxidation, silicon nitride growth: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out dry type oxidation or wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, more at high temperature, growth one deck silicon nitride film on silicon oxide film.
The chemical liquid that adds a certain amount of hydrogen peroxide with ammoniacal liquor, hydrochloric acid cleans silicon chip surface 601 and groove 604, and in silicon chip surface 601 and groove 604 with high temp. dry type oxidation, perhaps wet oxidation, the perhaps silicon oxide film that the compound mode of dry type oxidation and wet oxidation growth one deck is thin (Fig. 6 D 607), some other add gases with dichlorosilane, ammonia and, with low pressure chemical vapor deposition (LPCVD) the method one deck silicon nitride film (Fig. 6 D 608) of growing on silicon oxide film 607.
6, silicon nitride dry etching: utilize carbon tetrafluoride, fluoroform gaseous plasma that silicon chip surface, channel bottom are carried out anisotropic dry etching, remove these local silicon nitride films, keep the silicon nitride film on the sidewall, perhaps, after removing the silicon nitride film of silicon chip surface, channel bottom with dry etching, with hydrofluoric acid inhibiting solution wet etching, remove the silicon oxide film of channel bottom fully.
Utilize the mist of sulphur hexafluoride, fluoroform and some other interpolation gas, perhaps utilize the mist of carbon tetrafluoride, fluoroform and some other interpolation gas, dry etching (normally reactive ion etching is RIE) is optionally carried out in silicon chip surface 601, groove 604 bottoms, remove these local silicon nitride films 608, keep the silicon nitride film 608 on the sidewall.Perhaps, after removing the silicon nitride film of silicon chip surface 601, groove 604 bottoms, remove the silicon oxide film 607 of channel bottom fully with hydrofluoric acid inhibiting solution wet etching with dry etching.
7, clean oxidation: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to carrying out the dry type oxidation in silicon chip surface, the groove, the perhaps combination of dry type oxidation and wet oxidation is at silicon chip surface, channel bottom growth one deck silicon oxide film.
Add a certain amount of hydrogen peroxide cleaning silicon chip surface 601 with ammoniacal liquor, hydrochloric acid, and in silicon chip surface 601 and groove 604 with high temp. dry type oxidation, perhaps wet oxidation, the perhaps silicon oxide film that the compound mode of dry type oxidation and wet oxidation growth one deck is thicker (Fig. 6 E 609).
8, silica etching, silicon nitride etch, the silica etching: use the hydrofluoric acid inhibiting solution, hot phosphoric acid chemical liquid is removed silicon oxide film, the silicon nitride film on silicon nitride film surface and is removed the silicon oxide film of trenched side-wall fully, stays one deck silicon oxide film at silicon chip surface and channel bottom.
Remove the silicon oxide film on silicon nitride film 608 surfaces with hydrofluoric acid inhibiting solution wet etching, remove silicon nitride film 608 fully with hot phosphoric acid soup, remove the silicon oxide film 607 of trenched side-wall again with hydrofluoric acid inhibiting solution wet etching fully, keep one deck silicon oxide film at silicon chip surface and channel bottom.
9, clean, oxidation: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to carrying out dry type oxidation, perhaps wet oxidation in silicon chip surface, the groove, the perhaps combination of dry type oxidation and wet oxidation, growth one deck silicon oxide film in silicon chip surface, groove.
Add a certain amount of hydrogen peroxide cleaning silicon chip surface 601 with ammoniacal liquor, hydrochloric acid, at high temperature to 604 carrying out the dry type oxidation in silicon chip surface 601, the groove, perhaps wet oxidation, the perhaps combination of dry type oxidation and wet oxidation, at trenched side-wall growth one deck silicon oxide film (Fig. 6 F 610), on the basis of silicon chip surface, the original silicon oxide film of channel bottom, form thicker oxide-film film (Fig. 6 F 611).
10, polysilicon deposit: under the high temperature in silicon chip surface and groove zero-clearance, one deck doped polycrystalline silicon film of growing densely; Perhaps under the high temperature in silicon chip surface and groove zero-clearance, one deck non-impurity-doped polysilicon membrane of growing densely, inject by ion again, perhaps High temperature diffusion imports polysilicon membrane with impurity, forms the doped polycrystalline silicon film that conducts electricity very well.
Add the mist of gas with silane, phosphine and some other, under the high temperature with low pressure chemical vapor deposition (LPCVD) method zero-clearance, one deck doped polycrystalline silicon film (Fig. 6 G 612) of growing densely in silicon chip surface 601 and groove 604; Perhaps utilize silane and some other to add the mist of gas, under the high temperature with low pressure chemical vapor deposition (LPCVD) method zero-clearance, one deck non-impurity-doped polysilicon membrane of growing densely in silicon chip surface 601 and groove 604, inject by ion again, perhaps utilize phosphine and some other to add the mist of gas, under the high temperature diffusion of impurities is entered polysilicon membrane, form doped polycrystalline silicon film.
11, the outer polysilicon of groove is removed: utilize chlorine gaseous plasma dry etching, perhaps the doped polycrystalline silicon of silicon chip surface is removed in chemico-mechanical polishing, keeps the doped polycrystalline silicon film in the groove.
The plasma that produces with chlorine, hydrogen bromide and some other mist that adds gas, the doped polycrystalline silicon 612 of silicon chip surface 601 is removed, silicon oxide film 611 is by over etching under the polycrystalline, but still has certain thickness silicon oxide film (Fig. 6 H 613), the polysilicon membrane 612 that keeps growth in the groove 604, and smooth substantially (614) of guaranteeing groove place silicon chip surface; Perhaps the outer doped polycrystalline silicon film 612 of groove is ground with the method for chemico-mechanical polishing (CMP), remove the doped polycrystalline silicon film 612 on the outer silicon chip surface 601 of groove, stay certain thickness silicon oxide film 613, keep pattern smooth substantially 614 at the groove place.
Following with reference to Fig. 6 C～6H, 6I, 6J and Fig. 8, it is as follows that another kind of the present invention is used for the concrete processing step of groove structure manufacture method of power device:
1, the selection of silicon chip: select to be used to realize that channel bottom, trench bottom corner and top corner place grow the substrate of the different crystal orientations of the silicon oxide film thicker than trenched side-wall, perhaps epitaxial silicon chip, according to requirement on devices, select molten (FZ) silicon substrate of vertical pulling (CZ) or district in suitable crystal orientation, perhaps epitaxial silicon chip, selecting silicon chip surface is 100, and locating flat limit (OrientationFlat) tangent plane also is 100; Perhaps selecting silicon chip surface is 110, and locating flat limit tangent plane is 100; Perhaps selecting silicon chip surface is 111, locating flat limit tangent plane is 110, the silicon chip that uses as the present invention (Fig. 6 C～6H, 6I, 6J 600), silicon chip surface is burnishing surface (Fig. 6 C～6H, 6I, 6J 601), adds a certain amount of hydrogen peroxide cleaning silicon chip and keeps the silicon chip cleaning with ammoniacal liquor, hydrochloric acid.
2, masking graphics forms: be coated with the last layer photoresist at silicon chip surface, form needed figure with exposure, developing method on photoresist.
Directly on silicon chip surface 601, be coated with the last layer photoresist, perhaps other resist (Fig. 6 I 615), with exposure, develop or similarly method perhaps form needed figure on other resist 615 at photoresist.
3, etching groove, remove photoresist: utilize photoresist to do and shelter, utilize Nitrogen trifluoride, perhaps the chlorine gaseous plasma carries out anisotropic dry etching to the silicon chip top layer, forms groove, removes photoresist then.
To form the photoresist of figure, perhaps other resist 615 is as sheltering, utilize Nitrogen trifluoride, perhaps chlorine, perhaps sulphur hexafluoride, perhaps their composition gas adds the plasma of mist generation of gas with some other, anisotropically silicon chip surface is carried out dry etching (being generally reactive ion etching is RIE), form the groove that width, the degree of depth meet design requirement (Fig. 6 J, 6C～6H 604), stay the remaining photoresist of etching on the silicon chip surface 601, perhaps other resist (Fig. 6 J 616).With hot sulfuric acid, hydrogen peroxide admixing medical solutions corroding method, perhaps the method that makes up with oxygen gas plasma ashing and hot sulfuric acid, the corrosion of hydrogen peroxide admixing medical solutions is removed photoresist or other resist 616.
4, clean, sacrificial oxidation, silica etching: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, with hydrofluoric acid inhibiting solution chemical liquid wet etching, remove the silicon oxide film of this secondary growth fully.
The chemical liquid that adds a certain amount of hydrogen peroxide with ammoniacal liquor, hydrochloric acid is to cleaning on the silicon chip surface 601 and in the groove 604, and with high temp. dry type oxidation, perhaps wet oxidation, perhaps the compound mode of dry type oxidation and the wet oxidation one deck silicon oxide film (Fig. 6 C 606) of growing in silicon chip surface and groove 604 is removed this layer silicon oxide film 606 with hydrofluoric acid inhibiting solution wet etching method afterwards.
5, clean, oxidation, silicon nitride growth: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out dry type oxidation or wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, more at high temperature, growth one deck silicon nitride film on silicon oxide film.
The chemical liquid that adds a certain amount of hydrogen peroxide with ammoniacal liquor, hydrochloric acid cleans silicon chip surface 601 and groove 604, and in silicon chip surface 601 and groove 604 with high temp. dry type oxidation, perhaps wet oxidation, the perhaps silicon oxide film that the compound mode of dry type oxidation and wet oxidation growth one deck is thin (Fig. 6 D 607), some other add gases with dichlorosilane, ammonia and, with low pressure chemical vapor deposition (LPCVD) the method one deck silicon nitride film (Fig. 6 D 608) of growing on silicon oxide film 607.
6, silicon nitride dry etching: utilize carbon tetrafluoride, fluoroform gaseous plasma that silicon chip surface, channel bottom are carried out anisotropic dry etching, remove these local silicon nitride films, keep the silicon nitride film on the sidewall, perhaps, after removing the silicon nitride film of silicon chip surface, channel bottom with dry etching, with hydrofluoric acid inhibiting solution wet etching, remove the silicon oxide film of channel bottom fully.
Utilize the mist of sulphur hexafluoride, fluoroform and some other interpolation gas, perhaps utilize the mist of carbon tetrafluoride, fluoroform and some other interpolation gas, dry etching (normally reactive ion etching is RIE) is optionally carried out in silicon chip surface 601, groove 604 bottoms, remove these local silicon nitride films 608, keep the silicon nitride film 608 on the sidewall.Perhaps, after removing the silicon nitride film of silicon chip surface 601, groove 604 bottoms, remove the silicon oxide film 607 of channel bottom fully with hydrofluoric acid inhibiting solution wet etching with dry etching.
7, clean oxidation: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to carrying out the dry type oxidation in silicon chip surface, the groove, the perhaps combination of dry type oxidation and wet oxidation is at silicon chip surface, channel bottom growth one deck silicon oxide film.
Add a certain amount of hydrogen peroxide cleaning silicon chip surface 601 with ammoniacal liquor, hydrochloric acid, and in silicon chip surface 601 and groove 604 with high temp. dry type oxidation, perhaps wet oxidation, the perhaps silicon oxide film that the compound mode of dry type oxidation and wet oxidation growth one deck is thicker (Fig. 6 E 609).
8, silica etching, silicon nitride etch, the silica etching: use the hydrofluoric acid inhibiting solution, hot phosphoric acid chemical liquid is removed silicon oxide film, the silicon nitride film on silicon nitride film surface and is removed the silicon oxide film of trenched side-wall fully, stays one deck silicon oxide film at silicon chip surface and channel bottom.
Remove the silicon oxide film on silicon nitride film 608 surfaces with hydrofluoric acid inhibiting solution wet etching, remove silicon nitride film 608 fully with hot phosphoric acid soup, remove the silicon oxide film 607 of trenched side-wall again with hydrofluoric acid inhibiting solution wet etching fully, keep one deck silicon oxide film at silicon chip surface and channel bottom.
9, clean, oxidation: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to carrying out dry type oxidation, perhaps wet oxidation in silicon chip surface, the groove, the perhaps combination of dry type oxidation and wet oxidation, growth one deck silicon oxide film in silicon chip surface, groove.
Add a certain amount of hydrogen peroxide cleaning silicon chip surface 601 with ammoniacal liquor, hydrochloric acid, at high temperature to 604 carrying out the dry type oxidation in silicon chip surface 601, the groove, perhaps wet oxidation, the perhaps combination of dry type oxidation and wet oxidation, at trenched side-wall growth one deck silicon oxide film (Fig. 6 F 610), on the basis of silicon chip surface, the original silicon oxide film of channel bottom, form thicker oxide-film film (Fig. 6 F 611).
10, polysilicon deposit: under the high temperature in silicon chip surface and groove zero-clearance, one deck doped polycrystalline silicon film of growing densely; Perhaps under the high temperature in silicon chip surface and groove zero-clearance, one deck non-impurity-doped polysilicon membrane of growing densely, inject by ion again, perhaps High temperature diffusion imports polysilicon membrane with impurity, forms the doped polycrystalline silicon film that conducts electricity very well.
Add the mist of gas with silane, phosphine and some other, under the high temperature with low pressure chemical vapor deposition (LPCVD) method zero-clearance, one deck doped polycrystalline silicon film (Fig. 6 G 612) of growing densely in silicon chip surface 601 and groove 604; Perhaps utilize silane and some other to add the mist of gas, under the high temperature with low pressure chemical vapor deposition (LPCVD) method zero-clearance, one deck non-impurity-doped polysilicon membrane of growing densely in silicon chip surface 601 and groove 604, inject by ion again, perhaps utilize phosphine and some other to add the mist of gas, under the high temperature diffusion of impurities is entered polysilicon membrane, form doped polycrystalline silicon film.
11, the outer polysilicon of groove is removed: utilize chlorine gaseous plasma dry etching, perhaps the doped polycrystalline silicon of silicon chip surface is removed in chemico-mechanical polishing, keeps the doped polycrystalline silicon film in the groove.
The plasma that produces with chlorine, hydrogen bromide and some other mist that adds gas, the doped polycrystalline silicon 612 of silicon chip surface 601 is removed, silicon oxide film 611 is by over etching under the polycrystalline, but still has certain thickness silicon oxide film (Fig. 6 H 613), the polysilicon membrane 612 that keeps growth in the groove 604, and smooth substantially (614) of guaranteeing groove place silicon chip surface; Perhaps the outer doped polycrystalline silicon film 612 of groove is ground with the method for chemico-mechanical polishing (CMP), remove the doped polycrystalline silicon film 612 on the outer silicon chip surface 601 of groove, stay certain thickness silicon oxide film 613, keep pattern smooth substantially 614 at the groove place.
Claims (10)
1. groove structure that is used for power device, it is characterized in that: the sidewall on silicon chip (500) vertically or sidewall slightly along the slope and along angle of slope θ=80～90 °, there is one deck to select the thick silicon oxide film (502) and the thin silicon oxide film (503) of sidewall in bottom of growth in the groove (501) of bottom slyness, zero-clearance is filled polysilicon membrane (504) on the silicon oxide film (503) in groove (501), form no step or be formed on 1000 dusts at groove place silicon chip surface, stay one deck silicon oxide film (506) on the silicon chip surface outside groove with interior less step appearance (505).
2. a groove structure manufacture method that is used for power device is characterized in that: comprise the steps:
(1), selects silicon chip;
(2), masking graphics forms; Etching groove, remove photoresist or masking film is removed;
(3), cleaning, sacrificial oxidation, silica etching;
(4), cleaning, oxidation, silicon nitride growth; The silicon nitride dry etching;
(5), cleaning, oxidation; Silica etching, silicon nitride etch, silica etching;
(6), cleaning, oxidation;
(7), polysilicon deposit;
(8), the groove polysilicon is removed.
3. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: select to be used to realize that channel bottom, trench bottom corner and top corner place grow the substrate of the different crystal orientations of the silicon oxide film thicker than trenched side-wall, perhaps epitaxial silicon chip, selecting silicon chip surface is 100, and locating flat limit tangent plane also is 100; Perhaps selecting silicon chip surface is 110, and locating flat limit tangent plane is 100; Perhaps selecting silicon chip surface is 111, and locating flat limit tangent plane is 110.
4. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: be coated with the last layer photoresist at silicon chip surface, on photoresist, form needed figure with exposure, developing method, utilizing photoresist to do shelters, utilize Nitrogen trifluoride, perhaps the chlorine gaseous plasma carries out anisotropic dry etching to the silicon chip top layer, forms groove, removes photoresist then; Perhaps do and shelter film at silicon chip surface elder generation growth one deck silica, one deck silicon nitride of perhaps growing is done and is sheltered film, utilizing photoresist to do then shelters, utilize carbon tetrafluoride, the fluoroform gaseous plasma carries out dry etching to sheltering film, perhaps utilize the hydrofluoric acid inhibiting solution, perhaps hot phosphoric acid and hydrofluoric acid inhibiting solution combinatorial chemistry soup carry out wet etching to sheltering film, afterwards, with photoresist and shelter film as sheltering, perhaps remove photoresist, shelter film as sheltering with this figure, utilize Nitrogen trifluoride, perhaps the chlorine gaseous plasma carries out anisotropic dry etching to the silicon chip top layer, forms groove, remove then with photoresist and masking film and do photoresist and the masking film of sheltering, perhaps remove with masking film and do the masking film of sheltering.
5. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, with hydrofluoric acid inhibiting solution chemical liquid wet etching, remove the silicon oxide film of this secondary growth fully.
6. the trench fabrication methods that is used for power device according to claim 2, it is characterized in that: use ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, then at high temperature to carrying out dry type oxidation or wet oxidation in silicon chip surface and the groove, at silicon chip surface, trenched side-wall and bottom growth one deck silicon oxide film, afterwards, again at high temperature, growth one deck silicon nitride film on silicon oxide film, utilize carbon tetrafluoride, the fluoroform gaseous plasma is to silicon chip surface, channel bottom carries out anisotropic dry etching, remove these local silicon nitride films, keep the silicon nitride film on the sidewall, perhaps, removing silicon chip surface with dry etching, after the silicon nitride film of channel bottom,, remove the silicon oxide film of channel bottom fully with hydrofluoric acid inhibiting solution wet etching.
7. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: use ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to silicon chip surface, carry out the dry type oxidation in the groove, the perhaps combination of dry type oxidation and wet oxidation, at silicon chip surface, channel bottom growth one deck silicon oxide film, afterwards, use the hydrofluoric acid inhibiting solution, hot phosphoric acid chemical liquid is removed the silicon oxide film on silicon nitride film surface, silicon nitride film and remove the silicon oxide film of trenched side-wall fully stays one deck silicon oxide film at silicon chip surface and channel bottom.
8. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: with ammoniacal liquor, hydrochloric acid and hydrogen peroxide chemical liquid cleaning silicon chip, at high temperature to carrying out the dry type oxidation in silicon chip surface, the groove, perhaps wet oxidation, the perhaps combination of dry type oxidation and wet oxidation, growth one deck silicon oxide film in silicon chip surface, groove.
9. the groove structure manufacture method that is used for power device according to claim 2 is characterized in that: under the high temperature in silicon chip surface and groove zero-clearance, one deck doped polycrystalline silicon film of growing densely; Perhaps under the high temperature in silicon chip surface and groove zero-clearance, one deck non-impurity-doped polysilicon membrane of growing densely, inject by ion again, perhaps High temperature diffusion imports polysilicon membrane with impurity, forms the doped polycrystalline silicon film that conducts electricity very well.
10. the groove structure manufacture method that is used for power device according to claim 2, it is characterized in that: utilize chlorine gaseous plasma dry etching, perhaps the doped polycrystalline silicon of silicon chip surface is removed in chemico-mechanical polishing, keeps the doped polycrystalline silicon film in the groove.
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| CN 201110175118 CN102290343B (en) | 2010-11-04 | 2011-06-27 | Manufacturing method of trench gate for power device |
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| CN1205658C (en) * | 1999-05-25 | 2005-06-08 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
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| CN102290343B (en) | 2013-01-16 |
| CN102290343A (en) | 2011-12-21 |
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