WO2014206177A1 - Method for preparing insulated gate bipolar transistor of trench fs structure - Google Patents

Method for preparing insulated gate bipolar transistor of trench fs structure Download PDF

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Publication number
WO2014206177A1
WO2014206177A1 PCT/CN2014/078906 CN2014078906W WO2014206177A1 WO 2014206177 A1 WO2014206177 A1 WO 2014206177A1 CN 2014078906 W CN2014078906 W CN 2014078906W WO 2014206177 A1 WO2014206177 A1 WO 2014206177A1
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trench
oxide layer
layer
wafer
bipolar transistor
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PCT/CN2014/078906
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French (fr)
Chinese (zh)
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王根毅
张硕
芮强
邓小社
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无锡华润上华半导体有限公司
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Publication of WO2014206177A1 publication Critical patent/WO2014206177A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

  • the present invention relates to the field of semiconductor fabrication and processing, and more particularly to a method for preparing an insulated gate bipolar transistor of a Trench FS structure .
  • Insulated Gate Bipolar Transistor is a device composed of a MOSFET and a bipolar transistor.
  • the input is extremely MOSFET and the output is extremely PNP transistor. Therefore, the IGBT can be regarded as a Darlington tube of MOS input.
  • IGBT has the advantages of MOSFET device voltage driving, high withstand voltage, simple driving and fast switching speed. At the same time, it has the advantages of strong current capability and reduced conduction voltage of bipolar devices, so it has been obtained in modern power electronics technology. The more widely used.
  • Planar FS Planar gate field termination
  • FS trench gate field termination
  • a method for preparing an insulated gate bipolar transistor of a Trench FS structure includes the following steps:
  • a source region precursor the region in which the Pbody region is in direct contact with the dense gate oxide layer and exposed is referred to as a source region precursor, and each of the Pbody regions is formed.
  • Photolithography is performed on the source region precursor, and then the source region precursor is implanted and diffused to obtain a source region;
  • the back surface of the wafer is metallized to form a metal layer laminated on the P+ anode layer.
  • the forming of the FS layer is performed by backside phosphorus ion implantation and pushing the well at a temperature of 1100 ° C to 1250 ° C to form an FS layer on the back side of the wafer.
  • the etching trench is formed by first growing an oxide layer on the front surface of the wafer, applying a photoresist, exposing through the photolithography process, etching the Trench portion, and performing dry etching. An oxide layer, removing the photoresist, using the oxide layer as a barrier layer during Trench etching, etching the wafer to generate a Trench trench, and then removing the oxide layer by controlling the etching time by wet etching, An etching groove is formed.
  • the oxide layer is an oxide layer formed by deposition and annealing in a furnace tube, or the oxide layer is an oxide layer formed by chemical vapor deposition.
  • the photoresist is a positive photoresist or a negative photoresist.
  • the forming of the dense gate oxide layer is performed by growing a dense gate oxide layer of 600A to 1500A through a furnace tube of 750 ° C to 1100 ° C.
  • the depositing the polysilicon gate is performed by depositing polysilicon on the dense gate oxide layer by a high temperature furnace tube method, the dense gate oxide layer and the polysilicon completely filling the etching trench Then, the polysilicon outside the etching trench is etched away by a dry polycrystalline etching process to obtain the polysilicon gate.
  • the obtaining of the Pbody region is performed by implanting a Pbody region at 800 ° C to 1000 ° C by boron ion implantation.
  • the operation of obtaining the source region is: selectively implanting N-type ions by a photolithography process, and forming an N-type doped source region by a push-well process.
  • the N-type ion is a phosphorus ion or an arsenic ion.
  • the operation of forming the dielectric block is: depositing an oxide layer by means of a furnace tube, and then selectively etching the oxide layer by photolithography and etching to form a dielectric block, adjacent to each other.
  • a source contact hole is formed between the two dielectric blocks.
  • the material of the oxide layer is borophosphosilicate glass.
  • the forming of the P+ anode layer stacked on the FS layer is performed by performing boron ion implantation on the back side of the wafer and annealing at a temperature of 300 ° C to 500 ° C to activate the implanted boron ions. Forming a P+ anode layer.
  • the metal layer in the operation of laminating a metal layer on the P+ layer, is Al, Ti, Ni, and Ag which are sequentially stacked.
  • This Trench FS The preparation method of the structure insulated gate bipolar transistor can not only ensure the performance of the IGBT structure, but also reduce the processing time of the wafer, improve the production efficiency and reduce the cost. Relative to traditional Trench The production of FS structure IGBT, long process time and high cost, the preparation method of the Trench FS structure of the insulated gate bipolar transistor does not require an epitaxial process, and the productivity is high and the cost is low.
  • FIG. 1 is a flow chart showing a method of fabricating an insulated gate bipolar transistor of a Trench FS structure according to an embodiment
  • Figure 2a ⁇ Figure 2d is the use of Trench as shown in Figure 1.
  • Trench of an embodiment comprises the following steps:
  • Wafer 10 can be purchased directly or processed by itself.
  • the operation of forming the FS layer 20 is to form a FS layer 20 on the back surface of the wafer 10 by backside phosphorus ion implantation and pushing the well at a temperature of 1100 ° C to 1250 ° C.
  • the etching trench is formed by first growing an oxide layer on the front surface of the wafer 10, applying a photoresist, and exposing the Trench portion by a photolithography process, and performing dry etching.
  • An etching bath 12 is formed.
  • a Pboldy region precursor 14 is formed between two adjacent etching grooves 12.
  • the oxide layer may be an oxide layer formed by deposition and annealing in a furnace tube or an oxide layer by PECVD (Chemical Vapor Deposition).
  • the photoresist can be a positive photoresist or a negative photoresist.
  • the operation of forming the dense gate oxide layer 30 is to grow a dense gate oxide layer 30 of 600A to 1500A through a furnace tube of 750 ° C to 1100 ° C.
  • the dense gate oxide layer 30 may be grown by a first dry rewet method, or a dry method, or a dry method followed by a wet method and a dry method.
  • a polysilicon gate 40 is deposited on the dense gate oxide layer 30, and the polysilicon gate 30 and the dense gate oxide layer 40 are filled with the full etching trench 12.
  • the operation of depositing the polysilicon gate 40 is: depositing polysilicon on the dense gate oxide layer 30 by means of a high temperature furnace tube, and the dense gate oxide layer 30 and polysilicon completely fill the etching trench 12, and then utilizing The dry polycrystalline etching process etches away polysilicon outside the etched trench 12 to obtain a polysilicon gate 40.
  • the region where the Pbody region 50 is in direct contact with the dense gate oxide layer 30 and exposed is referred to as the source region precursor 52, and two unconnected source region precursors 52 are formed in each of the Pbody regions 50.
  • the operation of the Pbody region 50 is performed to: push the well to form the Pbody region 50 at 800 ° C to 1000 ° C by boron ion implantation.
  • the operation of the source region 60 is performed by selectively implanting N-type ions by a photolithography process, and forming an N-doped source region 60 by a push-well process.
  • the N-type ion may be a phosphorus ion or an arsenic ion.
  • a dielectric block 70 is formed on the front side of the wafer 10.
  • the dielectric block 70 completely covers the dense gate oxide layer 30, and the polysilicon gate 40 and the source region 60 are separated by the dielectric block 70.
  • an oxide layer is deposited by means of a furnace tube, and then an oxide layer is selectively etched by photolithography and etching to form a dielectric block 70 between two adjacent dielectric blocks 70.
  • a source contact hole 72 is formed.
  • the oxide layer may be BPSG (borophosphosilicate glass), and the oxide layer is isolated as a dielectric layer over the polysilicon deposition and metal emitter electrodes.
  • BPSG borophosphosilicate glass
  • the deposited metal is typically Al.
  • the P+ anode layer 80 laminated on the FS layer 20 is formed by performing boron ion implantation on the back surface of the wafer 10 and annealing at a temperature of 300 ° C to 500 ° C to activate the implantation. Boron ions form a P+ anode layer 80.
  • the metal layer 90 is Al, Ti, Ni, and Ag which are sequentially laminated.
  • This Trench FS The preparation method of the structure insulated gate bipolar transistor can not only ensure the performance of the IGBT structure, but also reduce the process time of the wafer 10, improve the production efficiency and reduce the cost. Relative to traditional Trench The production of FS structure IGBT, long process time and high cost, the preparation method of the Trench FS structure of the insulated gate bipolar transistor does not require an epitaxial process, and the productivity is high and the cost is low.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
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Abstract

A method for preparing an insulated gate bipolar transistor of a Trench FS structure comprises the following steps: forming an FS layer (20) on the back surface of a wafer (10); forming etching slots (12) on the front surface of the wafer (10), and forming a Pbody area precursor (14) between two adjacent etching slots (12); forming through deposition a dense gate oxide layer (30) on the etching slot (12); depositing a polycrystalline silicon gate (40) on the dense gate oxide layer (30); performing injection and spreading on the Pbody area precursor (14), to obtain a Pbody area (50), an area in which the Pbody area (50) directly contacts with the dense gate oxide layer (30) and that is exposed being referred to as a source area precursor (52); performing photoetching, injection, and spreading on the source area precursor (52), to obtain a source area (60); forming a medium block (70) on the front surface of the wafer (10); forming, on the front surface of the wafer (10), a source (16) and a gate (18) that are disposed at intervals; and forming a P+ anode layer (80) and a metal layer (90) on the back surface of the wafer (10). The method for preparing an insulated gate bipolar transistor of a Trench FS structure does not need an epitaxy technique, the productivity is high, and the cost is low.

Description

Trench FS结构的绝缘栅双极型晶体管的制备方法Method for preparing insulated gate bipolar transistor of Trench FS structure
【技术领域】[Technical Field]
本发明涉及半导体制造加工领域，尤其涉及一种 Trench FS 结构的绝缘栅双极型晶体管的制备方法 。 The present invention relates to the field of semiconductor fabrication and processing, and more particularly to a method for preparing an insulated gate bipolar transistor of a Trench FS structure .
【背景技术】【Background technique】
绝缘栅双极型晶体管（Insulated Gate Bipolar Transistor，IGBT）是由MOSFET和双极型晶体管复合而成的一种器件，其输入极为MOSFET，输出极为PNP晶体管。因此，可以把IGBT看作是MOS输入的达林顿管。IGBT既具有MOSFET器件电压驱动、高耐压且驱动简单、开关速度快的优点，同时又具有双极型器件电流能力强、且导通压降低的优点，因而在现代电力电子技术中得到了越来越广泛的应用。Insulated Gate Bipolar Transistor (IGBT) is a device composed of a MOSFET and a bipolar transistor. The input is extremely MOSFET and the output is extremely PNP transistor. Therefore, the IGBT can be regarded as a Darlington tube of MOS input. IGBT has the advantages of MOSFET device voltage driving, high withstand voltage, simple driving and fast switching speed. At the same time, it has the advantages of strong current capability and reduced conduction voltage of bipolar devices, so it has been obtained in modern power electronics technology. The more widely used.
随着IGBT向高压大电流方向的发展，虽然 Planar FS （平面栅场终止）结构IGBT因其较NPT、PT结构而言，具有在更薄的厚度上承受更大的耐压，更好的开关特性等优点，但是其相对于Trench FS（沟槽栅场终止）结构IGBT来说，相同的电流能力的情况下占用了较大的芯片面积。With the development of IGBTs towards high voltage and high current, although Planar FS (Plane gate field termination) structure IGBT has the advantages of being more withstand voltage and thinner switching characteristics in a thinner thickness than the NPT and PT structures, but it is opposite to Trench. In the case of FS (trench gate field termination) structure IGBTs, a larger chip area is occupied with the same current capability.
传统的Trench FS结构的IGBT的制作工艺一般通过外延实现，但外延工艺时间较长，影响生产产能，且外延成本较高。Traditional Trench The fabrication process of the FS structure IGBT is generally realized by epitaxy, but the epitaxial process time is long, affecting the production capacity, and the epitaxial cost is high.
【发明内容】 [Summary of the Invention]
基于此，有必要提供一种产能较高且成本较低的Trench FS结构的绝缘栅双极型晶体管的制备方法。Based on this, it is necessary to provide a method for preparing an insulated gate bipolar transistor of a high-capacity and low-cost Trench FS structure.
一种Trench FS结构的绝缘栅双极型晶体管的制备方法，包括如下步骤：A method for preparing an insulated gate bipolar transistor of a Trench FS structure includes the following steps:
提供待加工的晶圆，并在所述晶圆背面形成FS层；Providing a wafer to be processed and forming an FS layer on the back side of the wafer;
在所述晶圆正面进行Trench光刻刻蚀，形成蚀刻槽，相邻的两个蚀刻槽之间形成Pboldy区前体；Performing a Trench lithography etch on the front side of the wafer to form an etched trench, and forming a Pboldy region precursor between the adjacent two etched trenches;
通过栅氧生长在所述蚀刻槽上沉积形成致密性栅氧层；Depositing a dense gate oxide layer on the etching trench by gate oxide growth;
在所述致密性栅氧层上沉积多晶硅栅，并且所述多晶硅栅和所述致密性栅氧层填充满所述蚀刻槽；Depositing a polysilicon gate on the dense gate oxide layer, and filling the etch trench with the polysilicon gate and the dense gate oxide layer;
对所述Pbody区前体进行注入和扩散，得到Pbody区，所述Pbody区与所述致密性栅氧层直接接触且裸露在外的区域称为源区前体，每个所述Pbody区中形成两个不相连的源区前体；Injecting and diffusing the precursor of the Pbody region to obtain a Pbody region, the region in which the Pbody region is in direct contact with the dense gate oxide layer and exposed is referred to as a source region precursor, and each of the Pbody regions is formed. Two unconnected source precursors;
对所述源区前体进行光刻，接着对所述源区前体进行注入和扩散，得到源区；Photolithography is performed on the source region precursor, and then the source region precursor is implanted and diffused to obtain a source region;
在所述晶圆的正面形成介质块，所述介质块完全覆盖所述致密性栅氧层，所述多晶硅栅和所述源区被所述介质块隔开；Forming a dielectric block on a front side of the wafer, the dielectric block completely covering the dense gate oxide layer, the polysilicon gate and the source region being separated by the dielectric block;
在所述晶圆正面沉积金属，接着对所述金属进行光刻和刻蚀，形成间隔设置的源电极和栅电极，所述源电极覆盖所述Pbody区和所述源区，所述栅电极覆盖所述多晶硅栅；Depositing a metal on the front side of the wafer, then photolithography and etching the metal to form spaced apart source and gate electrodes, the source electrode covering the Pbody region and the source region, the gate electrode Covering the polysilicon gate;
在所述晶圆背面进行硼离子注入和退火，形成层叠在所述FS层上的P+阳极层；Performing boron ion implantation and annealing on the back side of the wafer to form a P+ anode layer laminated on the FS layer;
对所述晶圆背面进行金属化，形成层叠在所述P+阳极层上的金属层。The back surface of the wafer is metallized to form a metal layer laminated on the P+ anode layer.
在一个实施例中，所述形成FS层的操作为：通过背面磷离子注入，并在1100℃~1250℃的温度下推阱，在所述晶圆的背面形成FS层。In one embodiment, the forming of the FS layer is performed by backside phosphorus ion implantation and pushing the well at a temperature of 1100 ° C to 1250 ° C to form an FS layer on the back side of the wafer.
在一个实施例中，所述形成蚀刻槽的操作为：先在所述晶圆正面生长一层氧化层，涂光刻胶，经过光刻工艺曝光出需要刻蚀Trench部位，通过干法刻蚀氧化层，去除光刻胶，利用氧化层作为Trench刻蚀时的阻挡层，刻蚀所述晶圆，产生Trench沟槽，之后利用湿法刻蚀，通过控制刻蚀时间去除所述氧化层，形成蚀刻槽。In one embodiment, the etching trench is formed by first growing an oxide layer on the front surface of the wafer, applying a photoresist, exposing through the photolithography process, etching the Trench portion, and performing dry etching. An oxide layer, removing the photoresist, using the oxide layer as a barrier layer during Trench etching, etching the wafer to generate a Trench trench, and then removing the oxide layer by controlling the etching time by wet etching, An etching groove is formed.
在一个实施例中，所述氧化层为通过炉管中淀积并退火形成的氧化层，或者所述氧化层为通过化学气相淀积形成的氧化层。In one embodiment, the oxide layer is an oxide layer formed by deposition and annealing in a furnace tube, or the oxide layer is an oxide layer formed by chemical vapor deposition.
在一个实施例中，所述光刻胶为正性光刻胶或负性光刻胶。In one embodiment, the photoresist is a positive photoresist or a negative photoresist.
在一个实施例中，所述形成致密性栅氧层的操作为：通过750℃~1100℃的炉管，生长600A~1500A的致密性栅氧化层。In one embodiment, the forming of the dense gate oxide layer is performed by growing a dense gate oxide layer of 600A to 1500A through a furnace tube of 750 ° C to 1100 ° C.
在一个实施例中，所述沉积多晶硅栅的操作为：通过高温炉管方式，在所述致密性栅氧层上沉积多晶硅，所述致密性栅氧层和所述多晶硅完全填充所述蚀刻槽，接着利用干法多晶刻蚀工艺刻蚀掉所述蚀刻槽之外的多晶硅，得到所述多晶硅栅。In one embodiment, the depositing the polysilicon gate is performed by depositing polysilicon on the dense gate oxide layer by a high temperature furnace tube method, the dense gate oxide layer and the polysilicon completely filling the etching trench Then, the polysilicon outside the etching trench is etched away by a dry polycrystalline etching process to obtain the polysilicon gate.
在一个实施例中，所述得到Pbody区的操作为：通过硼离子注入，在800℃~1000℃下推阱形成Pbody区。In one embodiment, the obtaining of the Pbody region is performed by implanting a Pbody region at 800 ° C to 1000 ° C by boron ion implantation.
在一个实施例中，所述得到源区的操作为：通过光刻工艺选择性的注入N型离子，通过推阱工艺形成N型掺杂的源区。In one embodiment, the operation of obtaining the source region is: selectively implanting N-type ions by a photolithography process, and forming an N-type doped source region by a push-well process.
在一个实施例中，所述N型离子为磷离子或者砷离子。In one embodiment, the N-type ion is a phosphorus ion or an arsenic ion.
在一个实施例中，所述形成介质块的操作为：通过炉管的方式淀积氧化层，接着利用光刻、刻蚀工艺选择性的刻蚀所述氧化层，形成介质块，相邻的两个介质块之间形成源区接触孔。In one embodiment, the operation of forming the dielectric block is: depositing an oxide layer by means of a furnace tube, and then selectively etching the oxide layer by photolithography and etching to form a dielectric block, adjacent to each other. A source contact hole is formed between the two dielectric blocks.
在一个实施例中，所述氧化层的材料为硼磷硅玻璃。In one embodiment, the material of the oxide layer is borophosphosilicate glass.
在一个实施例中，所述形成层叠在所述FS层上的P+阳极层的操作为：在晶圆背面进行硼离子注入，并在300℃~500℃的温度下退火，激活注入的硼离子，形成P+阳极层。In one embodiment, the forming of the P+ anode layer stacked on the FS layer is performed by performing boron ion implantation on the back side of the wafer and annealing at a temperature of 300 ° C to 500 ° C to activate the implanted boron ions. Forming a P+ anode layer.
在一个实施例中，所述层叠在所述P+层上的金属层的操作中，所述金属层为依次层叠的Al、Ti、Ni和Ag。In one embodiment, in the operation of laminating a metal layer on the P+ layer, the metal layer is Al, Ti, Ni, and Ag which are sequentially stacked.
这种 Trench FS 结构的绝缘栅双极型晶体管的制备方法，既可以很好的保证IGBT结构的性能，又减小了晶圆的工艺时间，提高了生产效率，降低了成本。相对于传统Trench FS结构IGBT的生产，工艺时间长，成本高的现状，这种Trench FS结构的绝缘栅双极型晶体管的制备方法不需要外延工艺，产能较高且成本较低。This Trench FS The preparation method of the structure insulated gate bipolar transistor can not only ensure the performance of the IGBT structure, but also reduce the processing time of the wafer, improve the production efficiency and reduce the cost. Relative to traditional Trench The production of FS structure IGBT, long process time and high cost, the preparation method of the Trench FS structure of the insulated gate bipolar transistor does not require an epitaxial process, and the productivity is high and the cost is low.
【附图说明】[Description of the Drawings]
图1为一实施方式的Trench FS结构的绝缘栅双极型晶体管的制备方法的流程图；1 is a flow chart showing a method of fabricating an insulated gate bipolar transistor of a Trench FS structure according to an embodiment;
图2a~图2d为采用如图1所示的Trench FS结构的绝缘栅双极型晶体管的制备方法处理后的晶圆的剖面结构示意图。Figure 2a ~ Figure 2d is the use of Trench as shown in Figure 1. Schematic diagram of the cross-sectional structure of the processed wafer after the FS structure of the insulated gate bipolar transistor.
【具体实施方式】 【detailed description】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。The above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims. Numerous specific details are set forth in the description below in order to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the invention, and thus the invention is not limited by the specific embodiments disclosed below.
如图1和图2a~图2d所示，一实施方式的Trench FS结构的绝缘栅双极型晶体管的制备方法，包括如下步骤：As shown in FIG. 1 and FIG. 2a to FIG. 2d, Trench of an embodiment The method for preparing an insulated gate bipolar transistor of the FS structure comprises the following steps:
S10、提供待加工的晶圆10，并在晶圆10背面形成FS层20。S10, providing a wafer 10 to be processed, and forming an FS layer 20 on the back surface of the wafer 10.
晶圆10可以直接购买得到，也可以自行加工得到。Wafer 10 can be purchased directly or processed by itself.
结合图2a，本实施方式中，形成FS层20的操作为：通过背面磷离子注入，并在1100℃~1250℃的温度下推阱，在晶圆10的背面形成FS层20。2a, in the present embodiment, the operation of forming the FS layer 20 is to form a FS layer 20 on the back surface of the wafer 10 by backside phosphorus ion implantation and pushing the well at a temperature of 1100 ° C to 1250 ° C.
S20、在晶圆10正面进行Trench光刻刻蚀，形成蚀刻槽12，相邻的两个蚀刻槽12之间形成Pboldy区前体14。S20, performing Trench lithography etching on the front side of the wafer 10 to form an etched trench 12, and forming a Pboldy region precursor 14 between the adjacent two etched trenches 12.
结合图2a，本实施方式中，形成蚀刻槽的操作为：先在晶圆10正面生长一层氧化层，涂光刻胶，经过光刻工艺曝光出需要刻蚀Trench部位，通过干法刻蚀氧化层，去除光刻胶，利用氧化层作为Trench刻蚀时的阻挡层，刻蚀所述晶圆，产生Trench沟槽，之后利用湿法刻蚀，通过控制刻蚀时间去除所述氧化层，形成蚀刻槽12。相邻的两个蚀刻槽12之间形成Pboldy区前体14。Referring to FIG. 2a, in the embodiment, the etching trench is formed by first growing an oxide layer on the front surface of the wafer 10, applying a photoresist, and exposing the Trench portion by a photolithography process, and performing dry etching. An oxide layer, removing the photoresist, using the oxide layer as a barrier layer during Trench etching, etching the wafer to generate a Trench trench, and then removing the oxide layer by controlling the etching time by wet etching, An etching bath 12 is formed. A Pboldy region precursor 14 is formed between two adjacent etching grooves 12.
氧化层可以为通过炉管中淀积并退火形成的氧化层也可以为通过PECVD（化学气相淀积）的氧化层。The oxide layer may be an oxide layer formed by deposition and annealing in a furnace tube or an oxide layer by PECVD (Chemical Vapor Deposition).
光刻胶可以为正性光刻胶，亦可以为负性光刻胶The photoresist can be a positive photoresist or a negative photoresist.
S30、通过栅氧生长在蚀刻槽12上沉积形成致密性栅氧层30。S30, depositing a dense gate oxide layer 30 on the etching trench 12 by gate oxide growth.
结合图2b，本实施方式中，形成致密性栅氧层30的操作为：通过750℃~1100℃的炉管，生长600A~1500A的致密性栅氧化层30。Referring to FIG. 2b, in the present embodiment, the operation of forming the dense gate oxide layer 30 is to grow a dense gate oxide layer 30 of 600A to 1500A through a furnace tube of 750 ° C to 1100 ° C.
具体而言，可以采用先干法再湿法，或者干法，或者先干法后湿法再干法的方式，生长致密性栅氧化层30。Specifically, the dense gate oxide layer 30 may be grown by a first dry rewet method, or a dry method, or a dry method followed by a wet method and a dry method.
S40、在致密性栅氧层30上沉积多晶硅栅40，并且多晶硅栅30和致密性栅氧层40填充满蚀刻槽12。S40, a polysilicon gate 40 is deposited on the dense gate oxide layer 30, and the polysilicon gate 30 and the dense gate oxide layer 40 are filled with the full etching trench 12.
结合图2b，本实施方式中，沉积多晶硅栅40的操作为：通过高温炉管方式，在致密性栅氧层30上沉积多晶硅，致密性栅氧层30和多晶硅完全填充蚀刻槽12，接着利用干法多晶刻蚀工艺刻蚀掉蚀刻槽12之外的多晶硅，得到多晶硅栅40。2b, in the present embodiment, the operation of depositing the polysilicon gate 40 is: depositing polysilicon on the dense gate oxide layer 30 by means of a high temperature furnace tube, and the dense gate oxide layer 30 and polysilicon completely fill the etching trench 12, and then utilizing The dry polycrystalline etching process etches away polysilicon outside the etched trench 12 to obtain a polysilicon gate 40.
S50、对Pbody区前体14进行注入和扩散，得到Pbody区50。S50, implanting and diffusing the precursor 14 of the Pbody region to obtain a Pbody region 50.
结合图2b，Pbody区50与致密性栅氧层30直接接触且裸露在外的区域称为源区前体52，每个Pbody区50中形成两个不相连的源区前体52。2b, the region where the Pbody region 50 is in direct contact with the dense gate oxide layer 30 and exposed is referred to as the source region precursor 52, and two unconnected source region precursors 52 are formed in each of the Pbody regions 50.
本实施例中，得到Pbody区50的操作为：通过硼离子注入，在800℃~1000℃下推阱形成Pbody区50。In the present embodiment, the operation of the Pbody region 50 is performed to: push the well to form the Pbody region 50 at 800 ° C to 1000 ° C by boron ion implantation.
S60、对源区前体52进行光刻，接着对源区前体52进行注入和扩散，得到源区60。S60, photolithography is performed on the source region precursor 52, and then the source region precursor 52 is implanted and diffused to obtain a source region 60.
结合图2c，本实施方式中，得到源区60的操作为：通过光刻工艺选择性的注入N型离子，通过推阱工艺形成N型掺杂的源区60。2c, in the present embodiment, the operation of the source region 60 is performed by selectively implanting N-type ions by a photolithography process, and forming an N-doped source region 60 by a push-well process.
N型离子可以为磷离子或者砷离子。The N-type ion may be a phosphorus ion or an arsenic ion.
S70、在晶圆10的正面形成介质块70，介质块70完全覆盖致密性栅氧层30，多晶硅栅40和源区60被介质块70隔开。S70, a dielectric block 70 is formed on the front side of the wafer 10. The dielectric block 70 completely covers the dense gate oxide layer 30, and the polysilicon gate 40 and the source region 60 are separated by the dielectric block 70.
结合图2c，本实施方式中，通过炉管的方式淀积氧化层，接着利用光刻、刻蚀工艺选择性的刻蚀氧化层，形成介质块70，相邻的两个介质块70之间形成源区接触孔72。Referring to FIG. 2c, in the embodiment, an oxide layer is deposited by means of a furnace tube, and then an oxide layer is selectively etched by photolithography and etching to form a dielectric block 70 between two adjacent dielectric blocks 70. A source contact hole 72 is formed.
氧化层可以为BPSG（硼磷硅玻璃），氧化层作为介质层隔离过多晶硅淀积和金属发射极电极。The oxide layer may be BPSG (borophosphosilicate glass), and the oxide layer is isolated as a dielectric layer over the polysilicon deposition and metal emitter electrodes.
S80、在晶圆10正面沉积金属，接着对金属进行光刻和刻蚀，形成间隔设置的源电极16和栅电极18，源电极16覆盖Pbody区50和源区60，栅电极18覆盖多晶硅栅40。S80, depositing a metal on the front side of the wafer 10, then photolithography and etching the metal to form a spaced-apart source electrode 16 and a gate electrode 18. The source electrode 16 covers the Pbody region 50 and the source region 60, and the gate electrode 18 covers the polysilicon gate. 40.
结合图2d，本实施方式中，沉积的金属通常为Al。In connection with Figure 2d, in the present embodiment, the deposited metal is typically Al.
S90、在晶圆10背面进行硼离子注入和退火，形成层叠在FS层20上的P+阳极层80。S90, boron ion implantation and annealing are performed on the back surface of the wafer 10 to form a P+ anode layer 80 laminated on the FS layer 20.
结合图2d，本实施方式中，形成层叠在FS层20上的P+阳极层80的操作为：在晶圆10背面进行硼离子注入，并在300℃~500℃的温度下退火，激活注入的硼离子，形成P+阳极层80。Referring to FIG. 2d, in the present embodiment, the P+ anode layer 80 laminated on the FS layer 20 is formed by performing boron ion implantation on the back surface of the wafer 10 and annealing at a temperature of 300 ° C to 500 ° C to activate the implantation. Boron ions form a P+ anode layer 80.
S100、对晶圆10背面进行金属化，形成层叠在P+阳极层80上的金属层90。S100, metallizing the back surface of the wafer 10 to form a metal layer 90 laminated on the P+ anode layer 80.
结合图2d，本实施方式中，金属层90为依次层叠的Al、Ti、Ni和Ag。2d, in the present embodiment, the metal layer 90 is Al, Ti, Ni, and Ag which are sequentially laminated.
这种 Trench FS 结构的绝缘栅双极型晶体管的制备方法，既可以很好的保证IGBT结构的性能，又减小了晶圆10的工艺时间，提高了生产效率，降低了成本。相对于传统Trench FS结构IGBT的生产，工艺时间长，成本高的现状，这种Trench FS结构的绝缘栅双极型晶体管的制备方法不需要外延工艺，产能较高且成本较低。This Trench FS The preparation method of the structure insulated gate bipolar transistor can not only ensure the performance of the IGBT structure, but also reduce the process time of the wafer 10, improve the production efficiency and reduce the cost. Relative to traditional Trench The production of FS structure IGBT, long process time and high cost, the preparation method of the Trench FS structure of the insulated gate bipolar transistor does not require an epitaxial process, and the productivity is high and the cost is low.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (14)

  1. 一种Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，包括如下步骤：A method for preparing an insulated gate bipolar transistor of a Trench FS structure, comprising the steps of:
    提供待加工的晶圆，并在所述晶圆背面形成FS层；Providing a wafer to be processed and forming an FS layer on the back side of the wafer;
    在所述晶圆正面进行Trench光刻刻蚀，形成蚀刻槽，相邻的两个蚀刻槽之间形成Pboldy区前体；Performing a Trench lithography etch on the front side of the wafer to form an etched trench, and forming a Pboldy region precursor between the adjacent two etched trenches;
    通过栅氧生长在所述蚀刻槽上沉积形成致密性栅氧层；Depositing a dense gate oxide layer on the etching trench by gate oxide growth;
    在所述致密性栅氧层上沉积多晶硅栅，并且所述多晶硅栅和所述致密性栅氧层填充满所述蚀刻槽；Depositing a polysilicon gate on the dense gate oxide layer, and filling the etch trench with the polysilicon gate and the dense gate oxide layer;
    对所述Pbody区前体进行注入和扩散，得到Pbody区，所述Pbody区与所述致密性栅氧层直接接触且裸露在外的区域称为源区前体，每个所述Pbody区中形成两个不相连的源区前体；Injecting and diffusing the precursor of the Pbody region to obtain a Pbody region, the region in which the Pbody region is in direct contact with the dense gate oxide layer and exposed is referred to as a source region precursor, and each of the Pbody regions is formed. Two unconnected source precursors;
    对所述源区前体进行光刻，接着对所述源区前体进行注入和扩散，得到源区；Photolithography is performed on the source region precursor, and then the source region precursor is implanted and diffused to obtain a source region;
    在所述晶圆的正面形成介质块，所述介质块完全覆盖所述致密性栅氧层，所述多晶硅栅和所述源区被所述介质块隔开；Forming a dielectric block on a front side of the wafer, the dielectric block completely covering the dense gate oxide layer, the polysilicon gate and the source region being separated by the dielectric block;
    在所述晶圆正面沉积金属，接着对所述金属进行光刻和刻蚀，形成间隔设置的源电极和栅电极，所述源电极覆盖所述Pbody区和所述源区，所述栅电极覆盖所述多晶硅栅；Depositing a metal on the front side of the wafer, then photolithography and etching the metal to form spaced apart source and gate electrodes, the source electrode covering the Pbody region and the source region, the gate electrode Covering the polysilicon gate;
    在所述晶圆背面进行硼离子注入和退火，形成层叠在所述FS层上的P+阳极层；Performing boron ion implantation and annealing on the back side of the wafer to form a P+ anode layer laminated on the FS layer;
    对所述晶圆背面进行金属化，形成层叠在所述P+阳极层上的金属层。The back surface of the wafer is metallized to form a metal layer laminated on the P+ anode layer.
  2. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成FS层的操作为：通过背面磷离子注入，并在1100℃~1250℃的温度下推阱，在所述晶圆的背面形成FS层。Trench according to claim 1 The method for fabricating an IGBT structure of an insulated gate bipolar transistor is characterized in that the operation of forming the FS layer is: by backside phosphorus ion implantation, and pushing the well at a temperature of 1100 ° C to 1250 ° C, in the wafer The back side forms the FS layer.
  3. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成蚀刻槽的操作为：先在所述晶圆正面生长一层氧化层，涂光刻胶，经过光刻工艺曝光出需要刻蚀Trench部位，通过干法刻蚀氧化层，去除光刻胶，利用氧化层作为Trench刻蚀时的阻挡层，刻蚀所述晶圆，产生Trench沟槽，之后利用湿法刻蚀，通过控制刻蚀时间去除所述氧化层，形成蚀刻槽。Trench according to claim 1 The method for fabricating an IGBT structure of an insulated gate bipolar transistor is characterized in that the etching trench is formed by first growing an oxide layer on the front surface of the wafer, applying a photoresist, and exposing through a photolithography process. The Trench portion needs to be etched, the oxide layer is removed by dry etching, the photoresist is removed, and the oxide layer is used as a barrier layer during Trench etching to etch the wafer to produce a Trench trench, which is then wet etched. The oxide layer is removed by controlling the etching time to form an etching bath.
  4. 根据权利要求3所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述氧化层为通过炉管中淀积并退火形成的氧化层，或者所述氧化层为通过化学气相淀积形成的氧化层。Trench according to claim 3 A method of fabricating an insulated gate bipolar transistor of the FS structure, characterized in that the oxide layer is an oxide layer formed by deposition and annealing in a furnace tube, or the oxide layer is an oxide layer formed by chemical vapor deposition .
  5. 根据权利要求3所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述光刻胶为正性光刻胶或负性光刻胶。Trench according to claim 3 A method of fabricating an insulated gate bipolar transistor of the FS structure, characterized in that the photoresist is a positive photoresist or a negative photoresist.
  6. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成致密性栅氧层的操作为：通过750℃~1100℃的炉管，生长600A~1500A的致密性栅氧化层。Trench according to claim 1 The method for fabricating an insulated gate bipolar transistor of the FS structure is characterized in that the operation of forming the dense gate oxide layer is: growing a dense gate oxide layer of 600A to 1500A through a furnace tube of 750 ° C to 1100 ° C.
  7. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述沉积多晶硅栅的操作为：通过高温炉管方式，在所述致密性栅氧层上沉积多晶硅，所述致密性栅氧层和所述多晶硅完全填充所述蚀刻槽，接着利用干法多晶刻蚀工艺刻蚀掉所述蚀刻槽之外的多晶硅，得到所述多晶硅栅。Trench according to claim 1 The method for fabricating an insulated gate bipolar transistor of the FS structure is characterized in that the operation of depositing the polysilicon gate is: depositing polysilicon on the dense gate oxide layer by a high temperature furnace tube method, the dense gate oxide The layer and the polysilicon completely fill the etching trench, and then the polysilicon outside the etching trench is etched away by a dry polycrystalline etching process to obtain the polysilicon gate.
  8. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述得到Pbody区的操作为：通过硼离子注入，在800℃~1000℃下推阱形成Pbody区。Trench according to claim 1 The method for preparing an insulated gate bipolar transistor of the FS structure is characterized in that the operation of obtaining the Pbody region is: pushing a well to form a Pbody region at 800 ° C to 1000 ° C by boron ion implantation.
  9. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述得到源区的操作为：通过光刻工艺选择性的注入N型离子，通过推阱工艺形成N型掺杂的源区。Trench according to claim 1 The method for fabricating an IGBT structure of an insulated gate bipolar transistor is characterized in that the operation of obtaining the source region is: selectively implanting N-type ions by a photolithography process, and forming an N-type doped source region by a push-well process .
  10. 根据权利要求9所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述N型离子为磷离子或者砷离子。Trench according to claim 9 A method of fabricating an insulated gate bipolar transistor of the FS structure, characterized in that the N-type ion is a phosphorus ion or an arsenic ion.
  11. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成介质块的操作为：通过炉管的方式淀积氧化层，接着利用光刻、刻蚀工艺选择性的刻蚀所述氧化层，形成介质块，相邻的两个介质块之间形成源区接触孔。Trench according to claim 1 The method for fabricating an insulated gate bipolar transistor of the FS structure is characterized in that the operation of forming the dielectric block is: depositing an oxide layer by means of a furnace tube, followed by selective etching by photolithography and etching The oxide layer is formed to form a dielectric block, and a source contact hole is formed between two adjacent dielectric blocks.
  12. 根据权利要求11所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述氧化层的材料为硼磷硅玻璃。Trench according to claim 11 A method of fabricating an insulated gate bipolar transistor of the FS structure, characterized in that the material of the oxide layer is borophosphosilicate glass.
  13. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成层叠在所述FS层上的P+阳极层的操作为：在晶圆背面进行硼离子注入，并在300℃~500℃的温度下退火，激活注入的硼离子，形成P+阳极层。Trench according to claim 1 The method for fabricating an insulated gate bipolar transistor of the FS structure is characterized in that the operation of forming the P+ anode layer stacked on the FS layer is: performing boron ion implantation on the back side of the wafer, and at 300 ° C ~ 500 Annealing at a temperature of °C activates the implanted boron ions to form a P+ anode layer.
  14. 根据权利要求1所述的Trench FS结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述层叠在所述P+层上的金属层的操作中，所述金属层为依次层叠的Al、Ti、Ni和Ag。Trench according to claim 1 A method of fabricating an insulated gate bipolar transistor of the FS structure, characterized in that, in the operation of laminating a metal layer on the P+ layer, the metal layer is Al, Ti, Ni, and Ag which are sequentially stacked.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409895A (en) * 2016-06-27 2017-02-15 电子科技大学 Insulated gate bipolar transistor and manufacturing method thereof
CN108922885A (en) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 A kind of high-power unidirectional TVS device
CN113838756A (en) * 2021-09-24 2021-12-24 南瑞联研半导体有限责任公司 Device manufacturing method for improving micro-deformation of Trench-IGBT wafer
CN115424926A (en) * 2022-09-26 2022-12-02 深圳安森德半导体有限公司 IGBT based on Trench structure and IGBT manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790737A (en) * 2004-12-15 2006-06-21 上海华虹Nec电子有限公司 IGBT and method for making same
US20100038675A1 (en) * 2008-08-14 2010-02-18 Fuji Electric Device Technology Co., Ltd. Power semiconductor devices and methods for manufacturing the same
CN102024848A (en) * 2010-11-04 2011-04-20 天津环鑫科技发展有限公司 Trench structure for power device and manufacturing method thereof
CN102420133A (en) * 2011-09-30 2012-04-18 上海华虹Nec电子有限公司 Method for manufacturing insulated gate bipolar transistor (IGBT) device
CN102800591A (en) * 2012-08-31 2012-11-28 电子科技大学 Preparation method for FS-IGBT device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283818A (en) * 2008-05-26 2009-12-03 Sanken Electric Co Ltd Semiconductor device and method of manufacturing the same
JP5589263B2 (en) * 2008-05-29 2014-09-17 富士電機株式会社 Method for forming trench in silicon carbide semiconductor substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790737A (en) * 2004-12-15 2006-06-21 上海华虹Nec电子有限公司 IGBT and method for making same
US20100038675A1 (en) * 2008-08-14 2010-02-18 Fuji Electric Device Technology Co., Ltd. Power semiconductor devices and methods for manufacturing the same
CN102024848A (en) * 2010-11-04 2011-04-20 天津环鑫科技发展有限公司 Trench structure for power device and manufacturing method thereof
CN102420133A (en) * 2011-09-30 2012-04-18 上海华虹Nec电子有限公司 Method for manufacturing insulated gate bipolar transistor (IGBT) device
CN102800591A (en) * 2012-08-31 2012-11-28 电子科技大学 Preparation method for FS-IGBT device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409895A (en) * 2016-06-27 2017-02-15 电子科技大学 Insulated gate bipolar transistor and manufacturing method thereof
CN106409895B (en) * 2016-06-27 2019-05-10 电子科技大学 A kind of insulated gate bipolar transistor and its manufacturing method
CN108922885A (en) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 A kind of high-power unidirectional TVS device
CN113838756A (en) * 2021-09-24 2021-12-24 南瑞联研半导体有限责任公司 Device manufacturing method for improving micro-deformation of Trench-IGBT wafer
CN115424926A (en) * 2022-09-26 2022-12-02 深圳安森德半导体有限公司 IGBT based on Trench structure and IGBT manufacturing method
CN115424926B (en) * 2022-09-26 2024-04-26 深圳安森德半导体有限公司 IGBT based on Trench structure and IGBT manufacturing method

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