WO2012065515A1 - Vdmos device and method for fabricating the same - Google Patents

Vdmos device and method for fabricating the same Download PDF

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Publication number
WO2012065515A1
WO2012065515A1 PCT/CN2011/081743 CN2011081743W WO2012065515A1 WO 2012065515 A1 WO2012065515 A1 WO 2012065515A1 CN 2011081743 W CN2011081743 W CN 2011081743W WO 2012065515 A1 WO2012065515 A1 WO 2012065515A1
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region
isolating
layer
source
epitaxial layer
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PCT/CN2011/081743
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French (fr)
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Le Wang
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Csmc Technologies Fab1 Co., Ltd
Csmc Technologies Fab2 Co., Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Definitions

  • the present disclosure relates to semiconductor fabrication and, more particularly, to a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device and a method for fabricating a VDMOS device.
  • VDMOS Vertical Double-diffused Metal-Oxide-Semiconductor
  • VDMOS devices are used more and more widely in analog circuits and driving circuits, especially in high-voltage power parts of such circuits, due to their small switching loss, high input impedance, small driving power, good frequency characteristic, highly linear transconductance, and etc.
  • Figure 1 shows a structure of a conventional N-type VDMOS device.
  • the conventional N-type VDMOS device includes:
  • a substrate including a body layer 101 having a drain region and an epitaxial layer 102 formed on the body layer 101, where the body layer 101 and the epitaxial layer 102 are N-type doped;
  • first body region 103 and a second body region 104 formed in the epitaxial layer 102, where the first body region 103 and the second body region 104 are P-type doped;
  • first source region 105 formed in the first body region 103 and a second source region 106 formed in the second body region 104, where the first source region 105 and the second source region 106 are N-type doped;
  • first source 107 formed on an upper surface of the first source region 105, and a second source 108 formed on an upper surface of the second source region 106 ;
  • a gate oxide layer 109 formed on an upper surface of the epitaxial layer 102 and located between the first source 107 and the second source 108;
  • a gate 110 formed on an upper surface of the gate oxide layer 109;
  • the drain region may be able to withstand high voltage, that is, high voltage and large current can be applied to the drain region.
  • a conducting channel of the VDMOS device is perpendicular to the surface of the VDMOS device. Therefore, when performing a lithography process on the surface of the device, a relatively low accuracy is required.
  • a relatively high level of integration can be achieved, that is, a larger width-to-length ratio (W/L) can be realized in a small region.
  • W/L width-to-length ratio
  • a length of the conducting channel is determined by a depth of the junction formed by two diffusions during forming the body regions 103 and 104 and the source regions 105 and 106. Therefore, the conducting channel may be made very short.
  • the VDMOS device with the above-described structure has a long life, and is thus widely used.
  • the VDMOS devices with the above structure generally have an electric performance worse than the theoretical value.
  • VDMOS Vertical Double-diffused Metal-Oxide-Semiconductor
  • the VDMOS device includes a substrate, which includes a body layer and an epitaxial layer formed over the body layer.
  • the body layer has a drain region.
  • the VDMOS device further includes an isolating region formed in the epitaxial layer, a first body region and a second body region formed in the epitaxial layer and located at two sides of the isolating region, a first source region and a second source region formed in the first body region and the second body region, respectively, and a gate region formed above the isolating region and located between the first source region and the second source region.
  • VDMOS Vertical Double-diffused Metal-Oxide-Semiconductor
  • Figure 1 is a schematic view showing a conventional VDMOS device.
  • Figure 2 is a schematic view showing a VDMOS device consistent with an embodiment of the present disclosure .
  • Figures 3-12 are schematic cross-sectional views showing a method for fabricating a VDMOS device consistent with an embodiment of the present disclosure.
  • the electric performance of the conventional VDMOS device is worse than the theoretical value. This may be mainly due to a parasitic JFET in the current path of the conventional VDMOS device with the above structure shown in Figure 1.
  • a parasitic resistance resulting from the parasitic JFET contributes to a large proportion of the series on-state resistance in the conventional VDMOS device.
  • the parasitic resistance due to the parasitic resistance, the total on-state resistance of the conventional VDMOS device is increased, resulting in higher input resistance and lower electric performance.
  • the parasitic resistance region to being broken down, the lateral dimension of the conventional VDMOS device cannot be too small.
  • a conventional VDMOS device occupies a large area, which reduces a utilization ratio of the substrate surface .
  • FIG. 2 shows a VDMOS device consistent with embodiments of the present disclosure.
  • the VDMOS device shown in Figure 2 includes :
  • a substrate including a body layer 201 having a drain region and an epitaxial layer 202 formed on the body layer;
  • first body region 204 and a second body region 205 formed in the epitaxial layer 202 and located at two sides of the isolating region 203, respectively, where the first body region 204 and the second body region 205 may be in a same doping state and have a conduction type opposite to that of the epitaxial layer 202 ;
  • first source region 206 formed in the first body region 204 and a second source region 207 formed in the second body region 205, where the first source region 206 and the second source region 207 may be in a same doping state and have a conduction type opposite to that of the first body region 204 and the second body region 205;
  • a gate region formed above the isolating region 203 and located between the first source region 206 and the second source region 207 .
  • a drain 211 is formed on a lower surface of the body layer 201.
  • a first source 208 and a second source 209 are formed on an upper surface of the substrate at locations corresponding to the first source region 206 and the second source region 207.
  • a gate 210 is formed on an upper surface of the gate region .
  • the gate region includes a gate oxide layer 212, a gate poly-silicon layer 213, and sidewall spacers 214 formed on sidewalls of the gate poly-silicon layer 213.
  • a silicide layer (not shown) may be formed on the gate poly-silicon layer 213.
  • the gate region may further include the silicide layer.
  • the doping state may include doping concentration and impurity type.
  • the first body region 204 and the second body region 205 may have a same doping state.
  • the first source region 206 and the second source region 207 may have a same doping state.
  • the doping ions, the doping concentrations, etc. of the first body region 204 and the second body region 205 may be the same.
  • the doping ions, the doping concentrations, etc of the first source region 206 and the second source region 207 may be the same.
  • the VDMOS device shown in Figure 2 may be an N-type VDMOS device.
  • the body layer 201 and the epitaxial layer 202 may be N-type doped
  • the first body region 204 and the second body region 205 may be P-type doped
  • the first source region 206 and the second source region 207 may be N-type doped.
  • the N-type dopant may be phosphorus or other pentavalent elements.
  • the P-type dopant may be boron or other trivalent elements.
  • the first body region 204 and the second body region 205 may be doped with boron at a doping concentration of about 2E 13cm -3 .
  • the first source region 204 and the second source region 205 may be doped with phosphorus or arsenic at a doping concentration of about 1E15cm -3 - about 1E16cm -3 .
  • the epitaxial layer 202 may be an N-type epitaxial layer. The doping concentration of the epitaxial layer 202 may be controlled during the growing process.
  • the VDMOS device consistent with embodiments of the present disclosure may also be a P-type VDMOS device , in which the body layer 201 and the epitaxial layer 202 may be P-type doped, the first body region 204 and the second body region 205 may be N-type doped, and the first source region 206 and the second source region 207 may be P-type doped.
  • the parasitic resistance region is formed in the conducting channel.
  • the isolating region 203 is formed in the conducting channel of the VDMOS device and is perpendicular to the surface of the gate region. In a direction parallel to the surface of the gate region, a width of the isolating region 203 may be smaller than a width of the gate region. Since an extension exists between the first body region 204 and the second body region 205, a depletion region with a certain extent may be kept between the isolating region 203 and the first body region 204, and between the isolating region 203 and the second body region 205.
  • the isolating region 203 may be adjusted according to the requirement of the specific device, and generally may be about 1-3 ⁇ m.
  • the isolating region 203 may be formed of silicon oxide, silicon nitride, or any other insulation material.
  • the insulative isolating region 203 formed in the epitaxial layer 202 and located between the first body region 204 and the second body region 205 may help to cut off the conducting channel between the first body region 204 and the second body region 205, removing the parasitic JFET, and thus eliminating the parasitic resistance. As a result, the total on-state resistance of the VDMOS device may be reduced and the electric performance thereof may be improved.
  • the parasitic resistance affects the selection of the critical dimension (CD) of the gate region. If the CD of the gate region increases, the parasitic capacitance increases and the gain of the device decreases. On the other hand, if the CD of the gate region decreases, the parasitic resistance increases rapidly and the maximum current in the device at the on state decreases rapidly.
  • the CD of the gate region may be made relatively small, so that the lateral dimension of the device may be smaller than that of the conventional VDMOS device. Therefore, the footprint for the cell of the device is reduced and the utilization ratio of the substrate surface is increased .
  • Figures 3-12 are sectional views showing a method for fabricating the VDMOS device consistent with embodiments of the present disclosure.
  • a substrate is provided.
  • the substrate includes a body layer 301 and an epitaxial layer 302 formed on the body layer 301.
  • the body layer 301 includes a drain region.
  • the body layer 301 and the epitaxial layer 302 may be N-type doped.
  • the substrate may be formed of an elementary semiconductor material, such as silicon or SiGe of monocrystalline, polycrystalline, or amorphous structure.
  • the substrate may be formed of a compound semiconductor material, such as silicon carbide, indium antimonide,lead telluride,indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, semiconductor alloy, or any combination thereof.
  • the substrate may be a Silicon On Insulator (SOI).
  • SOI Silicon On Insulator
  • the semiconductor substrate may include a multiple-layered structure including an epitaxial layer or a buried layer.
  • the epitaxial layer 302 may be an N-type epitaxial layer grown on the body layer 301 by a CVD process. A thickness of the epitaxial layer 302 may be determined according to the specific application of the device.
  • the body layer 301 may be formed of silicon.
  • a layer of thin oxide layer is grown on the epitaxial layer 302 as an implantation oxide layer 303.
  • the implantation oxide layer 303 may prevent the impurities from diffusing out of the epitaxial layer 302 during the ion implantation.
  • the implantation oxide layer 303 may be formed by a CVD or thermal oxidation process.
  • Figures 4 and 5 show a process for forming an isolating region 305 in the epitaxial layer 302 .
  • a photoresist layer is spin coated on the implantation oxide layer 303.
  • an anti-reflecting layer (not shown) to reduce unnecessary reflection may be formed on the implantation oxide layer 303, and the photoresist layer is formed on the anti-reflecting layer.
  • An exposure is performed on the photoresist layer using a mask with a pattern corresponding to the isolating region 305 to form a photoresist pattern 330, as shown in Figure 4.
  • ion implantation is performed using the photoresist pattern 330 as a mask to form an ion implantation layer 304 in the epitaxial layer 302.
  • the implanted ions may be oxygen ions or nitrogen ions.
  • An ion concentration in the ion implantation layer 304 may be about 1E13cm -3 to about 1E15cm -3 .
  • the ion implantation may be performed using a high power ion implanter, with the implanting power being about 80kev to about 100kev.
  • the photoresist pattern 330 is removed. Thereafter, an annealing, for example, a rapid thermal annealing, is performed to activate the ions in the ion implantation layer 304, turning the ion implantation layer 304 into the isolating region 305.
  • an annealing for example, a rapid thermal annealing
  • the material of the isolating region 305 may be different.
  • the material of the isolating region 305 may be silicon oxide if the implanted ions are oxygen ions, or silicon nitride if the implanted ions are nitrogen ions.
  • the rapid thermal annealing process may be performed under a high temperature of about 1000° ⁇ to about 1100° ⁇ for about 30 minutes.
  • the temperature and time may be controlled based on the requirement for the isolating region 305 of the device.
  • Figures 6 and 7 show a process for forming a first body region 308 and a second body region 309 at two sides of the isolating region 305 in the epitaxial layer 302.
  • the first body region 308 and the second body region 309 may be in a same doping state and have a conduction type opposite to that of the epitaxial layer 302.
  • the first body region 308 and the second body region 309 are P-type doped.
  • a photoresist pattern 340 corresponding to the first body region 308 and the second body region 309 is formed on the surface of the implanting oxide layer 303 by a lithography process. Then, an ion implantation is performed using the photoresist pattern 340 as a mask to form a first ion implantation layer 306 and a second ion implantation layer 307 for the first body region 308 and the second body region 309, respectively, in the epitaxial layer 302.
  • the photoresist pattern 340 is removed.
  • a thermal annealing process is performed to activate the implanted ions.
  • the first ion implantation layer 306 and the second ion implantation layer 307 extend further into the epitaxial layer 302, forming the first body region 308 and the second body region 309, respectively.
  • the thermal annealing process may be a rapid thermal annealing process.
  • Figures 8-10 show a process for forming a gate region on the epitaxial layer 302 above the isolating region 305.
  • the gate region includes a gate oxide layer 310, a gate poly-silicon layer 311, and sidewall spacers 312 formed on sidewalls of the gate poly-silicon layer 311.
  • the gate region may include a doped poly-silicon, or a laminated layer formed of poly-silicon and metal silicides on the poly-silicon.
  • the implantation oxide layer 303 is removed and a gate oxide layer 310 is grown on the surface of the epitaxial layer 302.
  • the gate oxide layer 310 may include silicon oxide. Removing the implantation oxide layer 303 before growing the gate oxide layer 310 may ensure a uniformity of the gate oxide layer 310 and a material uniqueness thereof, and may avoid pollution by the previously implanted impurities left in the implantation oxide layer 303.
  • the implantation oxide layer 303 may be removed by wet chemical etching or other suitable methods.
  • a poly-silicon layer is deposited on the gate oxide layer 310.
  • the poly-silicon layer may be formed by chemical vapor deposition, physical vapor deposition, or any other suitable processes.
  • a photoresist pattern (not shown) corresponding to the gate pattern is formed on the surface of the poly-silicon layer by a lithography process.
  • a dry etching process is performed on the poly-silicon layer using the photoresist pattern as a mask, forming the gate poly-silicon layer 311, as shown in Figure 9.
  • the photoresist pattern for forming the gate poly-silicon layer 311 is then removed.
  • a sidewall oxide layer is formed on the gate poly-silicon layer 311 and a photoresist pattern (not shown) corresponding to the gate pattern is formed on the surface of the sidewall oxide layer by a lithography process. Then, a dry etching process is performed using the photoresist pattern as a mask to form the sidewall spacers 312 on both sidewalls of the gate poly-silicon layer 311. At the same time, a portion of the gate oxide layer 310 not covered by the gate poly-silicon layer 311 and the sidewall spacers 312 is also removed by the dry etching. Thus a gate region including the gate oxide layer 310, the gate poly-silicon layer 311, and the sidewall spacers 312 is formed.
  • the side wall oxide layer may include silicon oxide and may be formed by depositing tetraethyl orthosilicate. In some embodiments, the side wall oxide layer may further includesilicon nitrogen deposited on the silicon oxide .
  • a first source region 313 is formed in the first body region 308, and a second source region 314 is formed in the second body region 309.
  • the first source region 313 and the second source region 314 may be in the same doping state and have a conduction type opposite to that of the first body region 308 and the second body region 309.
  • the first source region 313 and the second source region 314 may be N-type doped.
  • the first source region 313 and the second source region 314 may be formed by ion implantation using a photoresist pattern (not shown) corresponding to the first source region 313 and the second source region 314 as a mask .
  • the first and second body regions 308 and 309, and the first and second source regions 313 and 314 are formed by ion implantation.
  • these regions may also be formed by doping in melt growth, vapor phase doping, neutron transmutation, ion implanting, surface coating, etc .
  • the method for fabricating the VDMOS device further includes the following steps:
  • first source 315 and a second source 316 on an upper surface of the epitaxial layer 302 at locations corresponding to the first source region 313 and the second source region 314;
  • a gate 317 on an upper surface of the gate region (i.e. an upper surface of the gate poly-silicon layer 311).
  • the drain 318 may be formed by sputtering metal on the body layer 301 after thinning the back of the body layer 301 .
  • the process for forming the first source 315 and the second source 316 may include the following steps. First, a dielectric layer, i.e. an inter-layer dielectric layer, may be deposited on the upper surface of the epitaxial layer 302. Second, a photoresist pattern corresponding to a first through-hole and a second through-hole may be formed on the surface of the inter-layer dielectric layer by a lithography process. Third, an etching process is performed on the dielectric layer using the photoresist pattern as a mask to form the first through-hole and the second through-hole in the dielectric layer.
  • a dielectric layer i.e. an inter-layer dielectric layer
  • metal is filled in the first through-hole and the second through hole to be connected with the first source region 313 and the second source region 314, forming the first source 315 and the second source 316.
  • the gate 317 may be formed using a process similar to that for forming the first source 315 and the second source 316 .
  • the isolating region 305 is formed by ion implantation. However, in practice, the isolating region 305 may also be formed by selective etching, as described below. This method may include the following steps:
  • Step 1 forming a trench the epitaxial layer 302.
  • the trench may be formed by forming a resist pattern corresponding to the trench on the surface of the epitaxial layer 302 by lithography process, and then etching the epitaxial layer 302 using the photoresist pattern corresponding to the trench as a mask .
  • Step 2 coating an isolating material on the surface of the epitaxial layer 302, and filling the trench.
  • the isolating material may be formed by chemical vapor deposition, physical vapor deposition, or any other suitable method.
  • the trench may be filled by high density plasma-enhanced chemical vapor deposition (HD-PECVD) .
  • HD-PECVD high density plasma-enhanced chemical vapor deposition
  • Step 3 removing the isolating material outside the trench.
  • the isolating material outside the trench may be removed by a chemical mechanical polish process, so as to make the isolating region 305 flush with the surface of the epitaxial layer 302.
  • the isolating material outside the trench may be removed by an etch-back process.
  • a silicon oxide film may be formed outside the trench and between the isolating material and the surface of the epitaxial layer 302.
  • the isolating material on the silicon oxide film may be removed by an etch-back process using the silicon oxide film as an etch-stop layer, to make the surface of the isolating region 305 flush with the surface of the epitaxial layer 302 to ensure the smoothness of the surface of the substrate. Thereafter, the silicon oxide film may be removed by wet etching or other suitable methods.

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Abstract

A Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device and a method for fabricating the same are provided. The VDMOS device includes a substrate which includes a body layer (201) and an epitaxial layer (202) formed over the body layer (201). The body layer (201) has a drain region. The VDMOS device further includes an isolating region (203) formed in the epitaxial layer (202), a first body region (204) and a second body region (205) formed in the epitaxial layer (202) and located at two sides of the isolating region (203), a first source region (206) and a second source region (207) formed in the first body region (204) and the second body region (205) respectively, and a gate region formed above the isolating region (203) and located between the first source region (206) and the second source region (207).

Description

VDMOS DEVICE AND METHOD FOR FABRICATING THE SAME
TECHNICAL FIELD
The present disclosure relates to semiconductor fabrication and, more particularly, to a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device and a method for fabricating a VDMOS device.
BACKGROUND
With the continuing development of semiconductor techniques, VDMOS devices are used more and more widely in analog circuits and driving circuits, especially in high-voltage power parts of such circuits, due to their small switching loss, high input impedance, small driving power, good frequency characteristic, highly linear transconductance, and etc.
Figure 1 shows a structure of a conventional N-type VDMOS device. The conventional N-type VDMOS device includes:
a substrate, including a body layer 101 having a drain region and an epitaxial layer 102 formed on the body layer 101, where the body layer 101 and the epitaxial layer 102 are N-type doped;
a first body region 103 and a second body region 104 formed in the epitaxial layer 102, where the first body region 103 and the second body region 104 are P-type doped;
a first source region 105 formed in the first body region 103 and a second source region 106 formed in the second body region 104, where the first source region 105 and the second source region 106 are N-type doped;
a first source 107 formed on an upper surface of the first source region 105, and a second source 108 formed on an upper surface of the second source region 106;
a gate oxide layer 109 formed on an upper surface of the epitaxial layer 102 and located between the first source 107 and the second source 108;
a gate 110 formed on an upper surface of the gate oxide layer 109; and
a drain 111 formed on a lower surface of the body layer 101.
In the VDMOS device shown in Figure 1, the drain region may be able to withstand high voltage, that is, high voltage and large current can be applied to the drain region. A conducting channel of the VDMOS device is perpendicular to the surface of the VDMOS device. Therefore, when performing a lithography process on the surface of the device, a relatively low accuracy is required. In addition, with a device structure as shown in Figure 1, a relatively high level of integration can be achieved, that is, a larger width-to-length ratio (W/L) can be realized in a small region. Furthermore, a length of the conducting channel is determined by a depth of the junction formed by two diffusions during forming the body regions 103 and 104 and the source regions 105 and 106. Therefore, the conducting channel may be made very short. The VDMOS device with the above-described structure has a long life, and is thus widely used.
However, in practical use, the VDMOS devices with the above structure generally have an electric performance worse than the theoretical value.
SUMMARY
In accordance with the present disclosure, there is provided a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device. The VDMOS device includes a substrate, which includes a body layer and an epitaxial layer formed over the body layer. The body layer has a drain region. The VDMOS device further includes an isolating region formed in the epitaxial layer, a first body region and a second body region formed in the epitaxial layer and located at two sides of the isolating region, a first source region and a second source region formed in the first body region and the second body region, respectively, and a gate region formed above the isolating region and located between the first source region and the second source region.
Also in accordance with the present disclosure, there is provided a method for fabricating a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device. The method includes providing a substrate, which includes a body layer and an epitaxial layer formed over the body layer. The body layer has a drain region. The method further includes forming an isolating region in the epitaxial layer, forming a first body region and a second body region in the epitaxial layer at two sides of the isolating region, forming a gate region over the epitaxial layer and above the isolating region, and forming a first source region in the first body region and a second source region in the second body region.
Features consistent with the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Such features will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The above features of the present disclosure will be more explained with reference to the drawings. In all drawings, similar reference numerals indicate similar parts. The drawings may not be drawn to scale, but merely show the concept of the present disclosure.
Figure 1 is a schematic view showing a conventional VDMOS device.
Figure 2 is a schematic view showing a VDMOS device consistent with an embodiment of the present disclosure.
Figures 3-12 are schematic cross-sectional views showing a method for fabricating a VDMOS device consistent with an embodiment of the present disclosure.
DETAILED DESCRIPTION OF EMBODIMENTS
Hereinafter, embodiments of the present disclosure will be described in detail in conjunction with the drawings .
To facilitate the sufficient understanding of the disclosure, details are set forth in the following description. However, the present disclosure can be implemented in other manners than those described herein. Those skilled in the art can extend the applications of the present disclosure without deviating from the spirit thereof, and thus the disclosure is not limited to particular embodiments disclosed hereinafter.
Furthermore, the present disclosure is described in detail in conjunction with schematic diagrams. For ease of illustration, sectional views showing the structure of the device are not drawn to scale, and are only examples and should not limit the scope of the present disclosure. Moreover, in actual manufacture process, the sizes in all three dimensions, including length, width, and depth, should be provided.
As mentioned in the background section of the present disclosure, the electric performance of the conventional VDMOS device is worse than the theoretical value. This may be mainly due to a parasitic JFET in the current path of the conventional VDMOS device with the above structure shown in Figure 1. A parasitic resistance resulting from the parasitic JFET contributes to a large proportion of the series on-state resistance in the conventional VDMOS device. On the one hand, due to the parasitic resistance, the total on-state resistance of the conventional VDMOS device is increased, resulting in higher input resistance and lower electric performance. On the other hand, to prevent the parasitic resistance region from being broken down, the lateral dimension of the conventional VDMOS device cannot be too small. Thus, a conventional VDMOS device occupies a large area, which reduces a utilization ratio of the substrate surface.
Figure 2 shows a VDMOS device consistent with embodiments of the present disclosure. The VDMOS device shown in Figure 2 includes:
a substrate, including a body layer 201 having a drain region and an epitaxial layer 202 formed on the body layer;
an isolating region 203 formed in the epitaxial layer 202, where the isolating region 203 may be beneath a surface of the epitaxial layer 202 with no material of the isolating region above the surface of the epitaxial layer 202;
a first body region 204 and a second body region 205 formed in the epitaxial layer 202 and located at two sides of the isolating region 203, respectively, where the first body region 204 and the second body region 205 may be in a same doping state and have a conduction type opposite to that of the epitaxial layer 202;
a first source region 206 formed in the first body region 204 and a second source region 207 formed in the second body region 205, where the first source region 206 and the second source region 207 may be in a same doping state and have a conduction type opposite to that of the first body region 204 and the second body region 205; and
a gate region formed above the isolating region 203 and located between the first source region 206 and the second source region 207.
Furthermore, consistent with embodiments of the present disclosure, a drain 211 is formed on a lower surface of the body layer 201. A first source 208 and a second source 209 are formed on an upper surface of the substrate at locations corresponding to the first source region 206 and the second source region 207. A gate 210 is formed on an upper surface of the gate region.
Consistent with embodiments of the present disclosure, the gate region includes a gate oxide layer 212, a gate poly-silicon layer 213, and sidewall spacers 214 formed on sidewalls of the gate poly-silicon layer 213. Furthermore, in some embodiments, a silicide layer (not shown) may be formed on the gate poly-silicon layer 213. In such embodiments, the gate region may further include the silicide layer.
Consistent with embodiments of the present disclosure, the doping state may include doping concentration and impurity type. In some embodiments, the first body region 204 and the second body region 205 may have a same doping state. The first source region 206 and the second source region 207 may have a same doping state. Thus, the doping ions, the doping concentrations, etc. of the first body region 204 and the second body region 205 may be the same. The doping ions, the doping concentrations, etc of the first source region 206 and the second source region 207 may be the same.
In some embodiments, the VDMOS device shown in Figure 2 may be an N-type VDMOS device. In the N-type VDMOS device consistent with embodiments of the present disclosure, the body layer 201 and the epitaxial layer 202 may be N-type doped, the first body region 204 and the second body region 205 may be P-type doped, and the first source region 206 and the second source region 207 may be N-type doped.
The N-type dopant may be phosphorus or other pentavalent elements. The P-type dopant may be boron or other trivalent elements. The first body region 204 and the second body region 205 may be doped with boron at a doping concentration of about 2E 13cm -3. The first source region 204 and the second source region 205 may be doped with phosphorus or arsenic at a doping concentration of about 1E15cm-3 - about 1E16cm-3. The epitaxial layer 202 may be an N-type epitaxial layer. The doping concentration of the epitaxial layer 202 may be controlled during the growing process.
The VDMOS device consistent with embodiments of the present disclosure may also be a P-type VDMOS device , in which the body layer 201 and the epitaxial layer 202 may be P-type doped, the first body region 204 and the second body region 205 may be N-type doped, and the first source region 206 and the second source region 207 may be P-type doped.
In the conventional VDMOS devices, the parasitic resistance region is formed in the conducting channel. Consistent with embodiments of the present disclosure, the isolating region 203 is formed in the conducting channel of the VDMOS device and is perpendicular to the surface of the gate region. In a direction parallel to the surface of the gate region, a width of the isolating region 203 may be smaller than a width of the gate region. Since an extension exists between the first body region 204 and the second body region 205, a depletion region with a certain extent may be kept between the isolating region 203 and the first body region 204, and between the isolating region 203 and the second body region 205. That is, there may be a certain space between the isolating region 203 and the first body region 204, and between the isolating region 203 and the second body region 205. The sizes of the spaces may be determined by the specific size of the device. Consistent with embodiments of the present disclosure, the thickness of the isolating region 203 may be adjusted according to the requirement of the specific device, and generally may be about 1-3μm.
Various insulating materials may be used for the isolating region 203. For example, the isolating region 203 may be formed of silicon oxide, silicon nitride, or any other insulation material.
In the VDMOS device consistent with embodiments of the present disclosure, the insulative isolating region 203 formed in the epitaxial layer 202 and located between the first body region 204 and the second body region 205 may help to cut off the conducting channel between the first body region 204 and the second body region 205, removing the parasitic JFET, and thus eliminating the parasitic resistance. As a result, the total on-state resistance of the VDMOS device may be reduced and the electric performance thereof may be improved.
In the conventional VDMOS device, the parasitic resistance affects the selection of the critical dimension (CD) of the gate region. If the CD of the gate region increases, the parasitic capacitance increases and the gain of the device decreases. On the other hand, if the CD of the gate region decreases, the parasitic resistance increases rapidly and the maximum current in the device at the on state decreases rapidly. In the VDMOS device consistent with embodiments of the present disclosure, since the parasitic resistance is eliminated, the CD of the gate region may be made relatively small, so that the lateral dimension of the device may be smaller than that of the conventional VDMOS device. Therefore, the footprint for the cell of the device is reduced and the utilization ratio of the substrate surface is increased.
Figures 3-12 are sectional views showing a method for fabricating the VDMOS device consistent with embodiments of the present disclosure.
As shown in Figure 3, a substrate is provided. The substrate includes a body layer 301 and an epitaxial layer 302 formed on the body layer 301. The body layer 301 includes a drain region. In some embodiments, the body layer 301 and the epitaxial layer 302 may be N-type doped.
In some embodiments, the substrate may be formed of an elementary semiconductor material, such as silicon or SiGe of monocrystalline, polycrystalline, or amorphous structure. In some embodiments, the substrate may be formed of a compound semiconductor material, such as silicon carbide, indium antimonide,lead telluride,indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, semiconductor alloy, or any combination thereof. In some embodiments, the substrate may be a Silicon On Insulator (SOI). In some embodiments, the semiconductor substrate may include a multiple-layered structure including an epitaxial layer or a buried layer. Although several examples of the material suitable for the substrate are described above, any other materials that can be used as a semiconductor substrate fall within the spirit and scope of the present disclosure.
In some embodiments, the epitaxial layer 302 may be an N-type epitaxial layer grown on the body layer 301 by a CVD process. A thickness of the epitaxial layer 302 may be determined according to the specific application of the device. In some embodiments, the body layer 301 may be formed of silicon.
Subsequently, a layer of thin oxide layer is grown on the epitaxial layer 302 as an implantation oxide layer 303. The implantation oxide layer 303 may prevent the impurities from diffusing out of the epitaxial layer 302 during the ion implantation. The implantation oxide layer 303 may be formed by a CVD or thermal oxidation process.
Figures 4 and 5 show a process for forming an isolating region 305 in the epitaxial layer 302.
Referring to Figure 4, a photoresist layer is spin coated on the implantation oxide layer 303. In some embodiments, before coating the photoresist layer, an anti-reflecting layer (not shown) to reduce unnecessary reflection may be formed on the implantation oxide layer 303, and the photoresist layer is formed on the anti-reflecting layer. An exposure is performed on the photoresist layer using a mask with a pattern corresponding to the isolating region 305 to form a photoresist pattern 330, as shown in Figure 4. Then, ion implantation is performed using the photoresist pattern 330 as a mask to form an ion implantation layer 304 in the epitaxial layer 302. In some embodiments, the implanted ions may be oxygen ions or nitrogen ions. An ion concentration in the ion implantation layer 304 may be about 1E13cm-3 to about 1E15cm-3. The ion implantation may be performed using a high power ion implanter, with the implanting power being about 80kev to about 100kev.
Referring to Figure 5, the photoresist pattern 330 is removed. Thereafter, an annealing, for example, a rapid thermal annealing, is performed to activate the ions in the ion implantation layer 304, turning the ion implantation layer 304 into the isolating region 305. Depending on the type of implanted ions, the material of the isolating region 305 may be different. For example, the material of the isolating region 305 may be silicon oxide if the implanted ions are oxygen ions, or silicon nitride if the implanted ions are nitrogen ions.
In some embodiments, the rapid thermal annealing process may be performed under a high temperature of about 1000°С to about 1100°С for about 30 minutes. The temperature and time may be controlled based on the requirement for the isolating region 305 of the device.
Figures 6 and 7 show a process for forming a first body region 308 and a second body region 309 at two sides of the isolating region 305 in the epitaxial layer 302. The first body region 308 and the second body region 309 may be in a same doping state and have a conduction type opposite to that of the epitaxial layer 302. In some embodiments, the first body region 308 and the second body region 309 are P-type doped.
Referring to Figure 6, a photoresist pattern 340 corresponding to the first body region 308 and the second body region 309 is formed on the surface of the implanting oxide layer 303 by a lithography process. Then, an ion implantation is performed using the photoresist pattern 340 as a mask to form a first ion implantation layer 306 and a second ion implantation layer 307 for the first body region 308 and the second body region 309, respectively, in the epitaxial layer 302.
Referring to Figure 7, the photoresist pattern 340 is removed. A thermal annealing process is performed to activate the implanted ions. In the same time, the first ion implantation layer 306 and the second ion implantation layer 307 extend further into the epitaxial layer 302, forming the first body region 308 and the second body region 309, respectively. In some embodiments, the thermal annealing process may be a rapid thermal annealing process.
Figures 8-10 show a process for forming a gate region on the epitaxial layer 302 above the isolating region 305. In some embodiments, the gate region includes a gate oxide layer 310, a gate poly-silicon layer 311, and sidewall spacers 312 formed on sidewalls of the gate poly-silicon layer 311. In some embodiments, the gate region may include a doped poly-silicon, or a laminated layer formed of poly-silicon and metal silicides on the poly-silicon.
As shown in Figure 8, the implantation oxide layer 303 is removed and a gate oxide layer 310 is grown on the surface of the epitaxial layer 302. In some embodiments, the gate oxide layer 310 may include silicon oxide. Removing the implantation oxide layer 303 before growing the gate oxide layer 310 may ensure a uniformity of the gate oxide layer 310 and a material uniqueness thereof, and may avoid pollution by the previously implanted impurities left in the implantation oxide layer 303. The implantation oxide layer 303 may be removed by wet chemical etching or other suitable methods.
After the gate oxide layer 310 is formed, a poly-silicon layer is deposited on the gate oxide layer 310. The poly-silicon layer may be formed by chemical vapor deposition, physical vapor deposition, or any other suitable processes. A photoresist pattern (not shown) corresponding to the gate pattern is formed on the surface of the poly-silicon layer by a lithography process. Then, a dry etching process is performed on the poly-silicon layer using the photoresist pattern as a mask, forming the gate poly-silicon layer 311, as shown in Figure 9. The photoresist pattern for forming the gate poly-silicon layer 311 is then removed.
Thereafter, a sidewall oxide layer is formed on the gate poly-silicon layer 311 and a photoresist pattern (not shown) corresponding to the gate pattern is formed on the surface of the sidewall oxide layer by a lithography process. Then, a dry etching process is performed using the photoresist pattern as a mask to form the sidewall spacers 312 on both sidewalls of the gate poly-silicon layer 311. At the same time, a portion of the gate oxide layer 310 not covered by the gate poly-silicon layer 311 and the sidewall spacers 312 is also removed by the dry etching. Thus a gate region including the gate oxide layer 310, the gate poly-silicon layer 311, and the sidewall spacers 312 is formed.
The side wall oxide layer may include silicon oxide and may be formed by depositing tetraethyl orthosilicate. In some embodiments, the side wall oxide layer may further includesilicon nitrogen deposited on the silicon oxide.
Referring to Figure 11, a first source region 313 is formed in the first body region 308, and a second source region 314 is formed in the second body region 309. The first source region 313 and the second source region 314 may be in the same doping state and have a conduction type opposite to that of the first body region 308 and the second body region 309. In some embodiments, the first source region 313 and the second source region 314 may be N-type doped.
In some embodiments, the first source region 313 and the second source region 314 may be formed by ion implantation using a photoresist pattern (not shown) corresponding to the first source region 313 and the second source region 314 as a mask.
In the embodiments described above, the first and second body regions 308 and 309, and the first and second source regions 313 and 314 are formed by ion implantation. However, the scope of the present disclosure is not so limited. For example, these regions may also be formed by doping in melt growth, vapor phase doping, neutron transmutation, ion implanting, surface coating, etc.
Consistent with embodiments of the present disclosure, the method for fabricating the VDMOS device further includes the following steps:
forming a drain 318 on a lower surface of the body layer 301;
forming a first source 315 and a second source 316 on an upper surface of the epitaxial layer 302 at locations corresponding to the first source region 313 and the second source region 314; and
forming a gate 317 on an upper surface of the gate region (i.e. an upper surface of the gate poly-silicon layer 311).
In some embodiments, the drain 318 may be formed by sputtering metal on the body layer 301 after thinning the back of the body layer 301.
In some embodiments, the process for forming the first source 315 and the second source 316 may include the following steps. First, a dielectric layer, i.e. an inter-layer dielectric layer, may be deposited on the upper surface of the epitaxial layer 302. Second, a photoresist pattern corresponding to a first through-hole and a second through-hole may be formed on the surface of the inter-layer dielectric layer by a lithography process. Third, an etching process is performed on the dielectric layer using the photoresist pattern as a mask to form the first through-hole and the second through-hole in the dielectric layer. Finally, metal is filled in the first through-hole and the second through hole to be connected with the first source region 313 and the second source region 314, forming the first source 315 and the second source 316. The gate 317 may be formed using a process similar to that for forming the first source 315 and the second source 316.
In the embodiments described above, the isolating region 305 is formed by ion implantation. However, in practice, the isolating region 305 may also be formed by selective etching, as described below. This method may include the following steps:
Step 1: forming a trench the epitaxial layer 302. In some embodiments, the trench may be formed by forming a resist pattern corresponding to the trench on the surface of the epitaxial layer 302 by lithography process, and then etching the epitaxial layer 302 using the photoresist pattern corresponding to the trench as a mask.
Step 2: coating an isolating material on the surface of the epitaxial layer 302, and filling the trench. In some embodiments, the isolating material may be formed by chemical vapor deposition, physical vapor deposition, or any other suitable method. The trench may be filled by high density plasma-enhanced chemical vapor deposition (HD-PECVD).
Step 3: removing the isolating material outside the trench. In some embodiments, the isolating material outside the trench may be removed by a chemical mechanical polish process, so as to make the isolating region 305 flush with the surface of the epitaxial layer 302. Alternatively, the isolating material outside the trench may be removed by an etch-back process. In these embodiments, a silicon oxide film may be formed outside the trench and between the isolating material and the surface of the epitaxial layer 302. The isolating material on the silicon oxide film may be removed by an etch-back process using the silicon oxide film as an etch-stop layer, to make the surface of the isolating region 305 flush with the surface of the epitaxial layer 302 to ensure the smoothness of the surface of the substrate. Thereafter, the silicon oxide film may be removed by wet etching or other suitable methods.
The above embodiments are merely for exemplification purpose, and are not intended to limit the present disclosure in any form.
Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims (14)

  1. A Vertical Double-diffused Metal-Oxide-Semiconductor ( VDMOS) device, comprising:
    a substrate, comprising:
    a body layer comprising a drain region, and
    an epitaxial layer formed over the body layer;
    an isolating region formed in the epitaxial layer;
    a first body region and a second body region formed in the epitaxial layer and located at two sides of the isolating region;
    a first source region and a second source region formed in the first body region and the second body region, respectively; and
    a gate region formed above the isolating region and located between the first source region and the second source region.
  2. The VDMOS device according to claim 1, wherein the first body region and the second body region are in a same doping state and have a conduction type opposite to that of the epitaxial layer.
  3. The VDMOS device according to claim 1, wherein the first source region and the second source region are in a same doping state and have a conduction type opposite to that of the first body region and the second body region.
  4. The VDMOS device according to claim 1, wherein the isolating region is located in a conducting channel of the VDMOS device and is perpendicular to a surface of the gate region.
  5. The VDMOS device according to claim 1, wherein :
    a width of the isolating region in a direction parallel to a surface of the gate region is smaller than a width of the gate region, and
    a space is formed between the isolating region and the first body region and between the isolating region and the second body region.
  6. The VDMOS device according to claim 1, wherein the isolating region has a thickness of about 1-3μm.
  7. The VDMOS device according to claim 1, wherein the isolating region is formed of silicon oxide.
  8. The VDMOS device according to claim 1, wherein the isolating region is formed of silicon nitride.
  9. The VDMOS device according to any one of claims 1 to 8, further comprising:
    a drain formed on a lower surface of the substrate;
    a first source and a second source formed over the substrate at locations corresponding to the first source region and the second source region;
    and a gate formed over the gate region.
  10. A method for fabricating a Vertical Double-diffused Metal-Oxide-Semiconductor ( VDMOS) device, comprising:
    providing a substrate, the substrate comprising:
    a body layer comprising a drain region, and
    an epitaxial layer formed over the body layer;
    forming an isolating region in the epitaxial layer;
    forming a first body region and a second body region in the epitaxial layer, the first body region and the second body region being located at two sides of the isolating region;
    forming a gate region over the epitaxial layer, the gate region being above the isolating region; and
    forming a first source region in the first body region and a second source region in the second body region.
  11. The method according to claim 10, wherein forming the first body region and the second body region includes forming the first body region and the second body region to be in a same doping state and have a conduction type opposite to that of the epitaxial layer.
  12. The method according to claim 10, wherein forming the first source region and the second source region includes forming the first source region and the second source region to be in a same doping state and have a conduction type opposite to that of the first body region and the second body region.
  13. The method according claim 8, wherein forming the isolating region includes forming the isolating region by an ion implantation.
  14. The method according claim 8, wherein forming the isolating region comprises:
    forming a trench in the epitaxial layer;
    forming an isolating material on a surface of the epitaxial layer, and filling the trench with the isolating material; and
    removing a part of the isolating material outside the trench.
PCT/CN2011/081743 2010-11-19 2011-11-03 Vdmos device and method for fabricating the same WO2012065515A1 (en)

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