CN105161534A - Silicon carbide VDMOS device and manufacturing method - Google Patents
Silicon carbide VDMOS device and manufacturing method Download PDFInfo
- Publication number
- CN105161534A CN105161534A CN201510388855.0A CN201510388855A CN105161534A CN 105161534 A CN105161534 A CN 105161534A CN 201510388855 A CN201510388855 A CN 201510388855A CN 105161534 A CN105161534 A CN 105161534A
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- China
- Prior art keywords
- pbase
- district
- epitaxial loayer
- contact zone
- source region
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 46
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention belongs to the semiconductor technology and particularly relates to a silicon carbide VDMOS device and a manufacturing method. The silicon carbide VDMOS device comprises a silicon carbide N type heavily-doped substrate, a first silicon carbide N-epitaxial layer above the silicon carbide N type heavily-doped substrate, a bury medium groove in the first silicon carbide N-epitaxial layer, a second silicon carbide N-epitaxial layer, Pbase regions arranged at the upper portion of the second silicon carbide N-epitaxial layer, a source electrode formed by a silicon carbide P+ contact region in the Pbase regions and an N+ source region, a poly-silicon gate electrode, and a silicon dioxide medium between a poly-silicon and a semi-conductor. According to the silicon carbide VDMOS device, the bury medium groove is arranged at a lower portion of a JFET region, a gate-oxide electric field is optimized, and reliability of the device is improved.
Description
Technical field
The invention belongs to power semiconductor technologies, relate to vertical DMOS field-effect transistor (VDMOSFET) device architecture specifically, especially a kind of high reliability carborundum VDMOS device and preparation method thereof.
Background technology
Carbofrax material has excellent physics and electrology characteristic, with particular advantages such as its large energy gap, high critical breakdown electric field, high heat conductance and high saturation drift velocities, become the ideal semiconductor material making high pressure, high power, high temperature resistant, high frequency, Flouride-resistani acid phesphatase device, military and civil in have broad application prospects.The power electronic device prepared with carbofrax material has become one of the focus device and research frontier of current semiconductor applications.
Carborundum is the compound semiconductor that uniquely can directly be thermally oxidized, so can become the suitable material making metals-oxides-semiconductor structure.But, the SiO of carborundum heat growth
2quality is but not so good as silicon, SiC/SiO
2interface charge compare Si/SiO
2approximately high two orders of magnitude, especially SiC-SiO
2interface, near the high interface state density of conduction band edge, can make MOSFET channel electron mobility very low, and this will reduce the performance of device greatly.So carborundum VDMOS device has low channel mobility and serious gate medium integrity problem.
In addition, because SiC is compared to SiO
2have higher dielectric constant, according to the continuity of electric displacement vector, the electric field in gate medium silicon dioxide is about 2.5 times in carborundum.For carborundum VDMOS device, device is critical puncture time, JFET district can reach 1.5-2MV/cm usually near the electric field strength of grid oxygen, therefore, electric field strength in gate oxide will be easy to reach the minimum electric field affecting grid oxygen reliability, thus cause semi-conducting material and grid metal to inject electronics to gate medium, produce Fowler-Nordheim (FN) tunnelling current, cause becoming during medium puncturing (time-dependentdielectric-breakdown, TDDB), carborundum VDMOS device is made to face very serious gate medium integrity problem.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, propose a kind of high reliability carborundum VDMOS device and preparation method thereof.
For achieving the above object, the present invention adopts following technical scheme:
A kind of carborundum VDMOS device, comprise set gradually from bottom to top metal leakage pole 12, N
+substrate 11, a N
-epitaxial loayer 10 and the 2nd N
-epitaxial loayer 8; Described 2nd N
-one end, epitaxial loayer 8 upper strata has a Pbase district 7, and its upper strata other end has the 2nd Pbase district 71; In a described Pbase district 7, there is a separate N
+source region 6 and a P
+contact zone 5; In described 2nd Pbase district 71, there is the 2nd separate N
+source region 61 and the 2nd P
+contact zone 51; A described N
+source region 6 and a P
+contact zone 5 upper surface has the first metal source 3; Described 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface has the second metal source 31; Between described first metal source 3 and the second metal source 31, there is grid structure; Described grid structure is made up of gate oxide 4, the polysilicon gate 2 being positioned at gate oxide 4 upper surface and the gate electrode 1 that is positioned at polysilicon gate 2 upper surface; A described N
-have in epitaxial loayer 10 and bury media slot 9, described in bury two N of media slot 9 between the first Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 8 lower surface; A wherein Pbase district 7 and the 2nd Pbase district 71, a N
+source region 6 and the 2nd N
+source region 61, a P
+contact zone 5 and the 2nd P
+contact zone 51, first metal source 3 and the second metal source 31 are all symmetricly set on the 2nd N
-epitaxial loayer 8 center line both sides.
Further, burying the dielectric material of filling in media slot 9 described in is SiO
2, HfO
2, Si
3n
4, TiO
2, Al
2o
3and ZrO
2in one
A manufacture method for carborundum VDMOS device, is characterized in that, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate 11 upper surface generates a N
-epitaxial loayer 10;
Second step: adopt etching technics, at a N
-epitaxial loayer 10 etches groove in the middle part of upper strata, and filled media is formed and buries media slot 9 in the trench;
3rd step: adopt epitaxy technique, at a N
-epitaxial loayer 10 upper surface generates the 2nd N
-epitaxial loayer 8;
4th step: adopt ion implantation technology, at the 2nd N
-one end, epitaxial loayer 8 upper strata implanting p-type semiconductor impurities forms a Pbase district 7, and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district 71 thereon;
5th step; Adopt ion implantation technology, form a P in upper strata, a Pbase district 7 implanting p-type semiconductor impurities
+contact zone 5, forms the 2nd P in the 2nd upper strata, Pbase district 71 implanting p-type semiconductor impurities
+contact zone 51;
6th step: adopt ion implantation technology, injects N type semiconductor impurity on a upper strata, Pbase district 7 and forms a N
+source region 6, injects N type semiconductor impurity on the 2nd upper strata, Pbase district 71 and forms the 2nd N
+source region 61; A described P
+contact zone 5 and a N
+source region 6 is separate, described 2nd P
+contact zone 51 and the 2nd N
+source region 61 is separate;
7th step: at the 2nd N
-epitaxial loayer 8 grows gate oxide 4 in the middle part of upper strata, and at gate oxide 4 upper surface depositing polysilicon, and etching forms polysilicon gate 2;
8th step: at a N
+source region 6 and a P
+contact zone 5 upper surface generates the first metal source 3; At the 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface generates the second metal source 31; Polysilicon gate 2 generates gate electrode 1.
Beneficial effect of the present invention is, the present invention introduces media slot on the downside of device JFET district, and this media slot has certain shielding action to oxide field, by producing and the rightabout electric field of oxide field, reduce oxide field, thus improve the reliability of gate medium.
Accompanying drawing explanation
Fig. 1 is Conventional silicon carbide VDMOS device structural representation;
Fig. 2 is a kind of carborundum VDMOS device structural representation provided by the invention;
Fig. 3 is at silicon carbide N
+substrate forms a N
-silicon carbide epitaxial layers schematic diagram;
Fig. 4 is at the first silicon carbide N
-epitaxial loayer is formed and buries media slot schematic diagram;
Fig. 5 is at the first silicon carbide N
-epitaxial loayer forms the 2nd N
-silicon carbide epitaxial layers schematic diagram;
Fig. 6 is at the second silicon carbide N
-epitaxial loayer forms Liang Ge Pbase district schematic diagram by ion implantation;
Fig. 7 forms P respectively by ion implantation in Liang Ge Pbase district
+contact zone schematic diagram;
Fig. 8 forms N respectively by ion implantation in Liang Ge Pbase district
+source region schematic diagram;
Fig. 9 grows one deck gate medium silicon dioxide at semiconductor surface, and depositing polysilicon, etch polysilicon forms gate shapes schematic diagram;
Figure 10 is device architecture schematic diagram after generation drain electrode, gate electrode and source electrode.
Figure 11 is carborundum VDMOS device structure of the present invention and Conventional silicon carbide VDMOS device structure oxide field distributed simulation comparison diagram.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
A kind of carborundum VDMOS device of the present invention, as shown in Figure 2, comprise set gradually from bottom to top metal leakage pole 12, N
+substrate 11, a N
-epitaxial loayer 10 and the 2nd N
-epitaxial loayer 8; Described 2nd N
-one end, epitaxial loayer 8 upper strata has a Pbase district 7, and its upper strata other end has the 2nd Pbase district 71; In a described Pbase district 7, there is a separate N
+source region 6 and a P
+contact zone 5; In described 2nd Pbase district 71, there is the 2nd separate N
+source region 61 and the 2nd P
+contact zone 51; A described N
+source region 6 and a P
+contact zone 5 upper surface has the first metal source 3; Described 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface has the second metal source 31; Between described first metal source 3 and the second metal source 31, there is grid structure; Described grid structure is made up of gate oxide 4, the polysilicon gate 2 being positioned at gate oxide 4 upper surface and the gate electrode 1 that is positioned at polysilicon gate 2 upper surface; A described N
-have in epitaxial loayer 10 and bury media slot 9, described in bury two N of media slot 9 between the first Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 8 lower surface.
The manufacture method of a kind of carborundum VDMOS device of the present invention, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate 11 upper surface generates a N
-epitaxial loayer 10, as shown in Figure 3;
Second step: adopt etching technics, at a N
-epitaxial loayer 10 etches groove in the middle part of upper strata, and filled media is formed and buries media slot 9 in the trench, as shown in Figure 4;
3rd step: adopt epitaxy technique, at a N
-epitaxial loayer 10 upper surface generates the 2nd N
-epitaxial loayer 8, as shown in Figure 5;
4th step: adopt ion implantation technology, at the 2nd N
-one end, epitaxial loayer 8 upper strata implanting p-type semiconductor impurities forms a Pbase district 7, and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district 71 thereon, as shown in Figure 6;
5th step; Adopt ion implantation technology, form a P in upper strata, a Pbase district 7 implanting p-type semiconductor impurities
+contact zone 5, forms the 2nd P in the 2nd upper strata, Pbase district 71 implanting p-type semiconductor impurities
+contact zone 51, as shown in Figure 7;
6th step: adopt ion implantation technology, injects N type semiconductor impurity on a upper strata, Pbase district 7 and forms a N
+source region 6, injects N type semiconductor impurity on the 2nd upper strata, Pbase district 71 and forms the 2nd N
+source region 61; A described P
+contact zone 5 and a N
+source region 6 is separate, described 2nd P
+contact zone 51 and the 2nd N
+source region 61 is separate, as shown in Figure 8;
7th step: at the 2nd N
-epitaxial loayer 8 grows gate oxide 4 in the middle part of upper strata, and at gate oxide 4 upper surface depositing polysilicon, and etching forms polysilicon gate 2, as shown in Figure 9;
8th step: at a N
+source region 6 and a P
+contact zone 5 upper surface generates the first metal source 3; At the 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface generates the second metal source 31; Polysilicon gate 2 generates gate electrode 1, as shown in Figure 10.
The present invention by introducing media slot on the downside of carborundum VDMOS device JFET district, this media slot has certain shielding action to oxide field, by producing and the rightabout electric field of oxide field, reduce oxide field, Figure 11 is carborundum VDMOS device structure provided by the invention and Conventional silicon carbide VDMOS device structure oxide field distributed simulation comparison diagram, abscissa is the distance apart from JFET center, ordinate is oxide field size, simulation result shows, adopt and there is the carborundum VDMOS device structure of burying media slot, electric field in grid oxygen can be reduced to 2.7MV/cm from 3.7MV/cm, the oxide field achieving 1MV/cm reduces.
Claims (3)
1. a carborundum VDMOS device, comprise set gradually from bottom to top metal leakage pole (12), N
+substrate (11), a N
-epitaxial loayer (10) and the 2nd N
-epitaxial loayer (8); Described 2nd N
-epitaxial loayer (8) one end, upper strata has a Pbase district (7), and its upper strata other end has the 2nd Pbase district (71); In a described Pbase district (7), there is a separate N
+source region (6) and a P
+contact zone (5); In described 2nd Pbase district (71), there is the 2nd separate N
+source region (61) and the 2nd P
+contact zone (51); A described N
+source region (6) and a P
+contact zone (5) upper surface has the first metal source (3); Described 2nd N
+source region (61) and the 2nd P
+contact zone (51) upper surface has the second metal source (31); Between described first metal source (3) and the second metal source (31), there is grid structure; Described grid structure is made up of gate oxide (4), the polysilicon gate (2) being positioned at gate oxide (4) upper surface and the gate electrode (1) that is positioned at polysilicon gate (2) upper surface; A described N
-have in epitaxial loayer (10) and bury media slot (9), described in bury media slot (9) and be positioned at the 2nd N between a Pbase district (7) and the 2nd Pbase district (71)
-epitaxial loayer (8) lower surface.
2. a kind of carborundum VDMOS device according to claim 1, is characterized in that, described in bury the dielectric material of filling in media slot (9) be SiO
2, HfO
2, Si
3n
4, TiO
2, Al
2o
3and ZrO
2in one.
3. a manufacture method for carborundum VDMOS device, is characterized in that, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate (11) upper surface generates a N
-epitaxial loayer (10);
Second step: adopt etching technics, at a N
-etch groove in the middle part of epitaxial loayer (10) upper strata, filled media is formed and buries media slot (9) in the trench;
3rd step: adopt epitaxy technique, at a N
-epitaxial loayer (10) upper surface generates the 2nd N
-epitaxial loayer (8);
4th step: adopt ion implantation technology, at the 2nd N
-epitaxial loayer (8) one end, upper strata implanting p-type semiconductor impurities forms a Pbase district (7), and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district (71) thereon;
5th step; Adopt ion implantation technology, form a P in Pbase district (7) upper strata implanting p-type semiconductor impurities
+contact zone (5), forms the 2nd P in the 2nd Pbase district (71) upper strata implanting p-type semiconductor impurities
+contact zone (51);
6th step: adopt ion implantation technology, injects N type semiconductor impurity on Pbase district (7) upper strata and forms a N
+source region (6), injects N type semiconductor impurity on the 2nd Pbase district (71) upper strata and forms the 2nd N
+source region (61); A described P
+contact zone (5) and a N
+source region (6) is separate, described 2nd P
+contact zone (51) and the 2nd N
+source region (61) is separate;
7th step: at the 2nd N
-grow gate oxide (4) in the middle part of epitaxial loayer (8) upper strata, at gate oxide (4) upper surface depositing polysilicon, and etching forms polysilicon gate (2);
8th step: at a N
+source region (6) and a P
+contact zone (5) upper surface generates the first metal source (3); At the 2nd N
+source region (61) and the 2nd P
+contact zone (51) upper surface generates the second metal source (31); Polysilicon gate (2) generates gate electrode (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510388855.0A CN105161534A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510388855.0A CN105161534A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105161534A true CN105161534A (en) | 2015-12-16 |
Family
ID=54802348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510388855.0A Pending CN105161534A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
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| Country | Link |
|---|---|
| CN (1) | CN105161534A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302024A (en) * | 2017-07-26 | 2017-10-27 | 电子科技大学 | A kind of carborundum VDMOS device |
| CN112670182A (en) * | 2020-12-24 | 2021-04-16 | 中国电子科技集团公司第五十八研究所 | Preparation method and structure of split gate SiC VDMOS device with source field plate |
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| CN102468334A (en) * | 2010-11-19 | 2012-05-23 | 无锡华润上华半导体有限公司 | VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor Structure) device and manufacturing method thereof |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN104392932A (en) * | 2014-12-10 | 2015-03-04 | 中国电子科技集团公司第四十七研究所 | VDMOS (Vertical Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
-
2015
- 2015-07-02 CN CN201510388855.0A patent/CN105161534A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030235942A1 (en) * | 2002-06-14 | 2003-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102468334A (en) * | 2010-11-19 | 2012-05-23 | 无锡华润上华半导体有限公司 | VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor Structure) device and manufacturing method thereof |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN104392932A (en) * | 2014-12-10 | 2015-03-04 | 中国电子科技集团公司第四十七研究所 | VDMOS (Vertical Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302024A (en) * | 2017-07-26 | 2017-10-27 | 电子科技大学 | A kind of carborundum VDMOS device |
| CN112670182A (en) * | 2020-12-24 | 2021-04-16 | 中国电子科技集团公司第五十八研究所 | Preparation method and structure of split gate SiC VDMOS device with source field plate |
| CN112670182B (en) * | 2020-12-24 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Preparation method and structure of split gate SiC VDMOS device with source field plate |
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Application publication date: 20151216 |