CN102290344A - Trench type MOS (metal oxide semiconductor) tube manufacturing process - Google Patents
Trench type MOS (metal oxide semiconductor) tube manufacturing process Download PDFInfo
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- CN102290344A CN102290344A CN2011102574172A CN201110257417A CN102290344A CN 102290344 A CN102290344 A CN 102290344A CN 2011102574172 A CN2011102574172 A CN 2011102574172A CN 201110257417 A CN201110257417 A CN 201110257417A CN 102290344 A CN102290344 A CN 102290344A
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Abstract
The invention provides a trench type MOS (metal oxide semiconductor) tube manufacturing process, which can improve the surface flatness of a trench gate, avoid V-like depression structures and improve the performance of a trench type MOS tube. The process comprises the following steps that: a semiconductor substrate structure which comprises a trench, and a gate medium layer deposited on the surface of the trench and the surface of the substrate structure is provided; a polysilicon layer is deposited on the surface of the gate medium layer; impurity ions of the first type are injected in the surface of the polysilicon layer; impurity ions of the second type are injected in the polysilicon surface, and the impurity ions of the first type are different from the impurity ions of the second type; the annealing is carried out; the polysilicon layer is ground through a chemical mechanical grinding process; the polysilicon layer out of the trench is removed through a back-etching process; and a source electrode and a drain electrode are manufactured.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the groove MOS pipe and make technology.
Background technology
Groove MOS field effect tube is the Novel MOS tube that grows up on plane formula metal-oxide-semiconductor field effect transistor basis, possess advantages such as conducting resistance is little, saturation voltage is low, switching speed is fast, gully density is high, chip size is little, be the main flow of mesolow metal-oxide-semiconductor field effect transistor development, described mesolow scope is generally between 20V～300V.
Fig. 1 is the cross-sectional view of existing a kind of groove MOS field effect tube.This groove MOS field effect tube 10 is at N
+Growth has one deck N on the silicon substrate 11
- Epitaxial loayer 110, electronics is flowed out from substrate 11 through raceway groove 13 by source end 12, and drain electrode 14 is drawn from the metal level of substrate 11 bottom surfaces.Polysilicon gate 15 is arranged in groove 16, is surrounded by gate oxide 17 in polysilicon gate 15 sides and bottom surface, is used for polysilicon gate 15 is isolated.
With reference to Fig. 2～Fig. 5, the manufacture craft flow process of common groove-type power metal-oxide-semiconductor field effect transistor shown in Figure 1 comprises:
With reference to Fig. 2, substrat structure 20 is provided, this substrat structure 20 comprises silicon substrate 11, N
-Epitaxial loayer epitaxial loayer 110, groove 16, these substrat structure 20 surface coverage have gate oxide 17.
With reference to Fig. 3, at the long-pending conductive polycrystalline silicon floor 18 of gate oxide 17 surface cushion;
With reference to Fig. 4, return etch polysilicon layer 18, by cmp (CMP) technology etching, reduce polysilicon layer 18 thickness; But because CMP technology is when grinding the preflood polysilicon layer of ion, the grinding rate unsteadiness is higher, therefore adopt CMP technology to grind on the one hand herein and make that polysilicon layer 18 surperficial consistency are poor, can cause polysilicon layer 18 surface depressions of groove 16 tops on the other hand, be similar V-arrangement shape.
Then carry out subsequent technique, be included in whole semi-conductor silicon chip surface and carry out for example phosphonium ion injection of p type impurity ion, then carry out for example boron ion injection of N type foreign ion; High annealing then; Pass through (CMP) technology, attenuate polysilicon layer again; By returning etching technics, etching is removed groove outer polysilicon layer and gate oxide, obtains polysilicon gate 15; Carry out subsequent technique then, finish that source electrode and drain electrode are made etc.。
With reference to Fig. 5, because the problem that CMP technology shown in Figure 4 causes, surperficial consistency is poor on the one hand for the trench gate polysilicon 15 of this groove MOS field effect tube, and surface depressions is similar V-arrangement shape on the other hand, greatly reduces trench grate MOS pipe performance.
Summary of the invention
The invention provides the groove MOS field effect tube manufacture craft, improved the trench gate surface flatness of the groove MOS field effect tube of producing, and avoided the trench gate surface the sagging structure of similar V-arrangement shape to occur, thereby improved groove MOS tube device performance.
According to the background technology analysis, the problem that existing scheme exists mainly be CMP technology when being used for the preflood polysilicon layer 15 of ion the grinding rate change cause more greatly, therefore mentality of designing of the present invention is by omitting the preflood trench gate polysilicon layer of ion CMP technology, improves trench gate surface consistency and avoids the problem of V-arrangement defective.
Based on this mentality of designing, a kind of groove MOS pipe provided by the invention is made technology, comprising:
Step 1 provides the Semiconductor substrate structure, and this Semiconductor substrate structure comprises groove, is deposited on the gate dielectric layer on flute surfaces and substrat structure surface; Described gate dielectric layer can be a single layer structure, also can be sandwich construction, and gate dielectric layer is an oxide layer usually.The groove MOS pipe has multiple structure, corresponding its substrat structure has multiple, the invention provides groove MOS pipe making technology and can be suitable for multiple groove MOS pipe, and being not limited to the concrete groove MOS tubular construction that is applicable to that the application secretary is carried, persons skilled in the art can be conspicuous be applied in other the application's book not clearly on the groove MOS tubular construction of record with manufacture craft provided by the invention.
Step 2 is at gate dielectric layer surface deposition polysilicon layer;
Step 3 is carried out first kind foreign ion and is injected on the polysilicon layer surface; Foreign ion is generally and is divided into P type ion and N type ion, and according to power MOS pipe type difference, first kind foreign ion is also different, if P type ion generally includes phosphorus (Ph) ion etc., if N type ion generally includes boron (B) ion etc.
Step 4 is carried out the second type dopant ion and is injected, and the described second type dopant ion is different with first kind foreign ion type, if first kind foreign ion is the P type, then the second type dopant ion is the N type, otherwise is the P type.
Step 5, high annealing.
Step 6, grind polysilicon layer by CMP technology, because this polysilicon layer is through ion injection and high annealing, when CMP technology is ground it, grinding rate stability improves greatly, also can not produce and grind the bigger problem of grinding rate change that takes place in the prior art scheme before ion injects.The CMP technology of this step mainly is with the polysilicon layer attenuate;
Step 7 by returning etching technics, is removed the outer polysilicon layer of groove, obtains polysilicon gate, and the etching precision that returns etching technics is higher, carries out meticulous removal, and the CMP technology of step 6 mainly is preliminary attenuate.
Step 8 is made gate electrode, source electrode and drain electrode.
Above-mentioned groove MOS pipe making scheme need not before ion injects polysilicon layer to be carried out CMP technology, avoided CMP technology when grinding the preflood polysilicon layer of ion, grinding rate unsteadiness problem of higher, improve trench gate surface consistency and avoided the V-arrangement defective, and then improved groove MOS tube device performance.
In above-mentioned process program, the polysilicon layer thickness of step 2 deposition for example injects energy with the injection parameter that step 3 and step 4 intermediate ion inject, implantation dosage is relevant.If step 3 and step 4 intermediate ion injection parameter are less, then the polysilicon of step 2 deposition is thinner; If step 3 and step 4 intermediate ion injection parameter are bigger, then the polysilicon thickness of step 2 deposition can be bigger.
Preferable, the polysilicon layer thickness of deposition is 6k dust～9K dust in the step 2, when step 3 is injected phosphonium ion, injects energy 70KeV～90KeV, implantation dosage is at 1.2E15/cm
-3～1.8E15/cm
-3, when step 4 is injected the boron ion, injecting energy 60KeV～80KeV, implantation dosage is at 1.3E15/cm
-3～2.0E15/cm
-3
Preferable, annealing temperature is higher than 900 degree in the step 5, and annealing time is 1.5 hours-2.5 hours.
Description of drawings
Fig. 1 is the cross-sectional view of existing a kind of groove-type power metal-oxide-semiconductor field effect transistor;
Fig. 2～Fig. 5 is the structural representation of existing groove-type power metal-oxide-semiconductor field effect transistor in making flow process;
Fig. 6～Figure 13 is the structural representation of embodiment of the invention groove-type power metal-oxide-semiconductor field effect transistor in making flow process.
Embodiment
Provide an embodiment of technical solution of the present invention below in conjunction with Figure of description 6～Figure 13.
With reference to Fig. 6, step b1 provides silicon substrate 30;
With reference to Fig. 7, step b2 is at silicon substrate 30 growing epitaxial layers 31; Epitaxial loayer 31 is positioned at silicon substrate 30 surfaces in this step, and the doping content of silicon substrate 30 is higher than epitaxial loayer 31 doping contents;
With reference to Fig. 8, step b3 at epitaxial loayer 31 superficial growth hard mask oxide layers 32, and by photoetching, defines trench etching zone 33, and carries out hard mask oxide layer 32 corrosion; In this step, hard mask oxide layer 32 can have multiple structure, and the double-layer structure of silicon dioxide layer and silicon nitride layer for example, silicon nitride are positioned at the silicon dioxide top.Hard mask oxide layer 32 is thinner.
With reference to Fig. 9, step b4 carries out deep plough groove etchedly based on hard mask oxide layer 32, etch deep trench 34, and removes hard mask oxide layer 32.
Step b5 forms sacrificial oxide layer, sacrificial oxide layer is removed again.
With reference to Figure 10, step b6, by thermal oxidation technology, growth gate oxide 35 in the atmospheric pressure oxidation stove;
B1～b6 has formed substrat structure by step.
With reference to Figure 11, step b7, at the long-pending conductive polycrystalline silicon 37 of gate oxide 35 surface cushion, polysilicon thickness h 1 is 6k dust～9K dust, preferable is 7K dust～8.5K dust.
Step b8 carries out phosphonium ion and injects on polysilicon layer 37 surfaces; Preferable, injecting energy 80KeV～85KeV, implantation dosage is at 1.5E15/cm
-3～1.7E15/cm
-3
Step b9 carries out the boron ion at polysilicon layer 37 and injects.Preferable, injecting energy 70KeV～80KeV, implantation dosage is 1.4E15/cm
-3～1.8E15/cm
-3
Step b10, high annealing, annealing temperature is between 900 degrees centigrade～1100 degrees centigrade, and annealing time is between 2 hours～2.5 hours.
With reference to Figure 12, step b11, CMP technology is ground polysilicon layer 37, with polysilicon layer 37 reduced thickness to 1.5K dust～3K dust;
With reference to Figure 13, step b12 returns etching, removes the outer polysilicon layer of groove;
Finish follow-up common process, comprise and remove the outer gate oxide of groove, making gate electrode, source electrode and drain electrode etc.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. a power groove MOS pipe is made technology, it is characterized in that, comprises step:
The Semiconductor substrate structure is provided, and this Semiconductor substrate structure comprises groove, is deposited on the gate dielectric layer on flute surfaces and substrat structure surface;
At gate dielectric layer surface deposition polysilicon layer;
Carry out first kind foreign ion injects on the polysilicon layer surface;
Carry out the second type dopant ion at polysilicon surface and inject, the described second type dopant ion is different with first kind foreign ion type;
Anneal;
Grind polysilicon layer by chemical mechanical milling tech;
By returning etching technics, remove the outer polysilicon layer of groove;
Make source electrode and drain electrode.
2. manufacture craft as claimed in claim 1 is characterized in that, the thickness of described polysilicon layer deposition is 6k dust～9K dust.
3. manufacture craft as claimed in claim 1 is characterized in that, described first kind foreign ion is a phosphonium ion, and the injection energy is 70KeV～90KeV, and implantation dosage is 1.2E15/cm
-31.8E15 it is individual/cm
-3
4. manufacture craft as claimed in claim 1 is characterized in that, the described second type dopant ion is the boron ion, injects energy 60KeV～80KeV, and implantation dosage is at 1.3E15/cm
-3～2.0E15/cm
-3
5. manufacture craft as claimed in claim 1 is characterized in that, when annealing, annealing temperature is between 900 degrees centigrade～1100 degrees centigrade.
6. manufacture craft as claimed in claim 1 is characterized in that, when annealing, annealing time is 1.5 hours～2.5 hours.
7. manufacture craft as claimed in claim 1 is characterized in that, described gate dielectric layer is a gate oxide.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102574172A CN102290344A (en) | 2011-09-01 | 2011-09-01 | Trench type MOS (metal oxide semiconductor) tube manufacturing process |
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| CN2011102574172A CN102290344A (en) | 2011-09-01 | 2011-09-01 | Trench type MOS (metal oxide semiconductor) tube manufacturing process |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
| CN103021869A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Trench power device manufacturing method |
| CN105931957A (en) * | 2016-05-11 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | Method for eliminating residual polysilicon |
| CN106409836A (en) * | 2016-11-21 | 2017-02-15 | 武汉新芯集成电路制造有限公司 | Manufacturing method of flash memory unit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5998288A (en) * | 1998-04-17 | 1999-12-07 | Advanced Micro Devices, Inc. | Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate |
| CN101305452A (en) * | 2005-07-25 | 2008-11-12 | 飞思卡尔半导体公司 | Programmable structure including nanocrystal storage elements in a trench |
| CN102024848A (en) * | 2010-11-04 | 2011-04-20 | 天津环鑫科技发展有限公司 | Trench structure for power device and manufacturing method thereof |
-
2011
- 2011-09-01 CN CN2011102574172A patent/CN102290344A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5998288A (en) * | 1998-04-17 | 1999-12-07 | Advanced Micro Devices, Inc. | Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate |
| CN101305452A (en) * | 2005-07-25 | 2008-11-12 | 飞思卡尔半导体公司 | Programmable structure including nanocrystal storage elements in a trench |
| CN102024848A (en) * | 2010-11-04 | 2011-04-20 | 天津环鑫科技发展有限公司 | Trench structure for power device and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021869A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Trench power device manufacturing method |
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
| CN105931957A (en) * | 2016-05-11 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | Method for eliminating residual polysilicon |
| CN105931957B (en) * | 2016-05-11 | 2019-04-16 | 上海华虹宏力半导体制造有限公司 | The method for eliminating residual polycrystalline silicon |
| CN106409836A (en) * | 2016-11-21 | 2017-02-15 | 武汉新芯集成电路制造有限公司 | Manufacturing method of flash memory unit |
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| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140430 |
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Effective date of registration: 20140430 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111221 |
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| RJ01 | Rejection of invention patent application after publication |