CN106024635A - Manufacturing method of power semiconductor device active region - Google Patents
Manufacturing method of power semiconductor device active region Download PDFInfo
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- CN106024635A CN106024635A CN201610529258.XA CN201610529258A CN106024635A CN 106024635 A CN106024635 A CN 106024635A CN 201610529258 A CN201610529258 A CN 201610529258A CN 106024635 A CN106024635 A CN 106024635A
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- injection
- polysilicon gate
- power semiconductor
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- block media
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 229920005591 polysilicon Polymers 0.000 claims abstract description 64
- 238000002347 injection Methods 0.000 claims abstract description 50
- 239000007924 injection Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 238000001947 vapour-phase growth Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000000376 reactant Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 19
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 18
- 239000012535 impurity Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 230000008447 perception Effects 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 208000037170 Delayed Emergence from Anesthesia Diseases 0.000 description 1
- 235000014678 Fruitflow® Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention relates to a manufacturing method of a power semiconductor device active region. The method comprises the following steps: forming a gate oxide layer on a substrate; forming a polysilicon grid on the gate oxide layer; forming a P trap in the substrate; performing N+ injection to form N+ source regions in the P trap; forming injection block media on the substrate and the polysilicon grid; photoetchng and etching away the injection block media on the polysilicon grid, and the residual injection block media at the two sides of the polysilicon grid form injection block side walls; performing P+ injection by taking the polysilicon grid and the injection block side walls as a mask, and injecting P-type ions into the P trap; depositing dielectric layers on the substrate and the polysilicon grid; and carrying out contact hole photoetching and etching to form contact holes of the N+ source regions. According to the invention, energy avalanche stress (EAS) of a power device can be greatly improved, no obvious influences are caused to starting voltages VTH and conduction resistance Rdon of the device, and while routine parameters of the device are not affected, the reliability of the device working in a load environment is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the system of a kind of power semiconductor active area
Make method.
Background technology
Modem electronic circuitry is owing to using environment and the particularity of the condition of use, to power semiconductor (merit
Rate VDMOS, power IGBT etc.) reliability requirement more and more higher.Power semiconductor is owing to using
Needs, be usually connected in perceptual load circuit.As a example by VDMOS, when device turns off, perception is negative
Inductance in load produces the voltage about supply voltage twice size added by load circuit, is added in VDMOS device
Between the drain-source pole of part, make to bear the biggest rush of current between the drain-source pole of device.When drain voltage increases
And avalanche region cannot be put into by device during pinch off, leakage-body diode now will produce current carrier.This
Time, all of drain current (avalanche current) will be by leakage-body diode and be controlled by inductive load.As
The electric current that fruit flows to body district is sufficiently large, and it will turn on parasitic transistor, makes device produce avalanche breakdown, device
Because burning and permanent failure.
Therefore, in the urgent need to increasing the avalanche energy of power semiconductor, so that device energy trouble free service exists
In perceptual load circuit.
Summary of the invention
Based on this, it is necessary to provide the power semiconductor of a kind of avalanche energy (EAS) that can improve device
The manufacture method of active area.
A kind of manufacture method of power semiconductor active area, including: on substrate, form gate oxide；
Described gate oxide is formed polysilicon gate；P-well is formed in described substrate；Carry out N+ injection,
N+ source region is formed in described p-well；Described substrate and polysilicon gate are formed and injects block media；Photoetching
And etch away the injection block media on described polysilicon gate, the injection of described polysilicon gate both sides residual
Block media is formed to inject and stops side wall；Stop that side wall carries out P+ for mask with described polysilicon gate and injection
Inject, implanting p-type ion in described p-well；The implantation dosage that described P+ injects injects less than described N+
Implantation dosage；Dielectric layer deposited on described substrate and polysilicon gate；Carry out contact hole photoetching and etching,
Form the contact hole of described N+ source region.
Wherein in an embodiment, described injection block media is double-decker, described at substrate with polycrystalline
Form the step injecting block media on silicon gate, be successively to carry out silicon nitride deposition and tetraethyl orthosilicate
(TEOS) deposit.
Wherein in an embodiment, the described step forming injection block media on substrate and polysilicon gate
Suddenly, it is the silicon nitride of 1000 angstroms～3000 angstroms thickness of low-pressure chemical vapor phase deposition, and with tetraethyl orthosilicate is
Reactant low-pressure chemical vapor phase deposition 5000 angstroms～the silicon dioxide of 10000 angstroms.
Wherein in an embodiment, described in carry out N+ injection step after, described at substrate with polysilicon
Before forming the step of injection block media on grid, also include carrying out P+ with described polysilicon gate extremely mask
Inject, the step of implanting p-type ion in described p-well；Described carry out P+ note with polysilicon gate extremely mask
The step that enters and described stop that side wall carries out the step this twice of P+ injection for mask with polysilicon gate and injecting
The implantation dosage that the implantation dosage sum that P+ injects is injected less than described N+.
Wherein in an embodiment, the described step carrying out P+ injection with polysilicon gate extremely mask, inject
Dosage is 2E15cm-2～5E15cm-2；Described with polysilicon gate and inject stop side wall carry out P+ for mask
The step injected, implantation dosage is 1E15cm-2～4E15cm-2；The implantation dosage that described N+ injects is
5E15cm-2～1.3E16cm-2。
Wherein in an embodiment, the note that the implantation dosage sum that described twice P+ injects is injected than described N+
Enter the little 2E15cm of dosage-2～4E15cm-2。
Wherein in an embodiment, the described step of dielectric layer deposited on substrate and polysilicon gate, be
Deposit forms non-impurity-doped silica glass and the two-layered medium Rotating fields of phosphorosilicate glass.
Wherein in an embodiment, after the step of the contact hole of described formation N+ source region, also include carrying out
The step that contact hole P+ injects.
Wherein in an embodiment, described photoetching also etches away and injects block media on polysilicon gate
Step, is by injecting the etching of gross thickness uniform thickness of block media on described polysilicon gate.
Wherein in an embodiment, described photoetching also etches away and injects block media on polysilicon gate
Step, is to use dry etching.
The manufacture method of above-mentioned power semiconductor active area, is injected by P+ and reduces body district resistance Rb,
Therefore the avalanche energy EAS of power device can be greatly improved.Simultaneously because inject the stop stopping side wall, note
The p-type ion entered, the most again will not be to the cut-in voltage V of device away from device channelTHWith conducting resistance Rdon
Produce significantly impact, while not affecting device conventional parameter, improve device under inductive load environment
The reliability of work.
Accompanying drawing explanation
Fig. 1 is active area and the schematic diagram of termination environment of power semiconductor in an embodiment；
Fig. 2 is the flow chart of the manufacture method of power semiconductor active area in an embodiment；
Fig. 3 a～Fig. 3 c is power semiconductor generalized section in the fabrication process.
Detailed description of the invention
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.
Accompanying drawing gives the first-selected embodiment of the present invention.But, the present invention can come real in many different forms
Existing, however it is not limited to embodiment described herein.On the contrary, providing the purpose of these embodiments is to make this
Disclosure of the invention content is more thorough comprehensively.
Unless otherwise defined, all of technology used herein and scientific terminology and the technology belonging to the present invention
The implication that the technical staff in field is generally understood that is identical.The art used the most in the description of the invention
Language is intended merely to describe the purpose of specific embodiment, it is not intended that in limiting the present invention.Used herein
Term " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
Semiconductor applications vocabulary used herein is the technical words that those skilled in the art commonly use, the most right
In p-type and N-type impurity, for distinguishing doping content, simply P+ type is represented the p-type of heavy dopant concentration,
The p-type of doping content in p-type representative, P-type represents the p-type that concentration is lightly doped, and it is dense that N+ type represents heavy doping
The N-type of degree, the N-type of doping content in N-type representative, N-type represents the N-type that concentration is lightly doped.
Power semiconductor can be vertical DMOS field-effect transistor
(VDMOSFET), insulated gate bipolar transistor (IGBT) constant power device.The present invention increases snowslide
The principle of ENERGY E AS is: power VDMOSFET and IGBT are owing to also existing parasitic transistor NPN (wherein
Liang Ge N district be N-type epitaxial layer and N+ source region respectively, P district refers to p-well).VDMOS in inductive load
With IGBT shutdown moment, leakage-body (reverse PN junction) diode flows through bigger electric current, by managing
Reduce body district resistance Rb, the voltage making the PN junction two ends of parasitic NPN transistor is electric less than the unlatching of PN junction
Press and make parasitic transistor be hardly turned on, thus eliminate avalanche breakdown.If body district resistance RbExcessive, when posting
When the voltage at the PN junction two ends of raw NPN transistor is more than the cut-in voltage of PN junction, parasitic transistor turns on
After, grid will be out of hand to electric current, simultaneously because the Current amplifier effect of parasitic NPN transistor makes electricity
Stream increases rapidly so that device generation avalanche breakdown and lost efficacy.
Seeing Fig. 1, it includes source region 100 and the termination environment 200 of active area 100 periphery.Fig. 2 is a reality
Execute the flow chart of the manufacture method of power semiconductor active area in example, comprise the steps:
S110, forms gate oxide on substrate.
(can be injected by P+ formed at the p-type field limiting ring forming termination environment, this specification is referred to as
P+ injects for the first time) and after carrying out active area field oxide etching, carry out the system of the gate oxide of active area
Standby.Wherein in an embodiment, the mode of thermal oxide is used to grow grid oxygen.The growth of grid oxygen can use
Dry oxygen technique, it would however also be possible to employ the technique of dry and wet dry (dry oxygen-wet oxygen-dry oxygen).
S120, forms polysilicon gate on gate oxide.
In the present embodiment, it is depositing polysilicon, and carries out polysilicon phosphorus diffusion (the most also
Can be that polysilicon is carried out phosphonium ion injection), then polysilicon is carried out photoetching and etching, forms polysilicon
Grid.
S130, forms p-well in substrate.
Implanting p-type foreign ion also spreads, and forms p-well.
S140, carries out N+ injection, forms N+ source region in p-well.
Carry out forming N+ source region in N+ is infused in p-well by this area conventional fashion.Fig. 3 a is step
S140 complete after the generalized section of power semiconductor, including p-well 1, N+ source region 2, gate oxide 3
And polysilicon gate 4.
S150, is formed on substrate and polysilicon gate and injects block media.
In the present embodiment, it is to form one layer by depositing technics at substrate and polysilicon gate surface can hinder
The injection block media of gear ion implanting.Wherein in an embodiment, inject block media and can use double
Rotating fields, obtains more more preferable blocking effect than single layer structure with the actual demand according to technique.Fig. 3 b is step
S150 complete after the generalized section of power semiconductor, in Fig. 3 b illustrated embodiment, inject and stop and be situated between
Matter includes the silicon nitride (Si that low-pressure chemical vapor phase deposition (LPCVD) is formed3N4) layer 5 and with positive silicic acid second
Ester (TEOS) is reactant LPCVD5000 angstrom～the silicon dioxide of 10000 angstroms.
S160, photoetching also etches away the injection block media on polysilicon gate, is formed and injects stop side wall.
See Fig. 3 c, owing to the thickness injecting block media at polysilicon gate 4 step can be more than polysilicon
The thickness injecting block media on grid 4, therefore by the injection block media on polysilicon gate just
When etching clean, polysilicon gate 4 both sides still can remain injection block media, is formed and injects stop side wall 7.
Wherein in an embodiment, step S160 is by and the injection block media on polysilicon gate 4
The etching of gross thickness uniform thickness, inject and stop that side wall 7 thickness everywhere approximates injection block media total thickness at this
The difference of the injection block media gross thickness on degree and polysilicon gate 4.In other embodiments, it is also possible to enter
The over etching that row is a small amount of.
With polysilicon gate and injection, S170, stops that side wall carries out P+ injection for mask, inject P in p-well
Type ion.
The P+ of this step is injected by this specification and is referred to as third time P+ injection.In order to reduce body district resistance Rb,
The dosage that P+ injects can not be the least.But the p-type ion owing to injecting can be in follow-up high-temperature diffusion process
Surrounding spreads, if the P+ ion injected is close to device channel, is easy for being diffused in raceway groove, increases
The cut-in voltage V of deviceTHWith conducting resistance Rdon, make the temperature rise of device increase, so that the reliability of device
Reduce.By injecting, the manufacture method of above-mentioned power semiconductor active area, stops that side wall 7 limits P
The injection zone of type ion, the p type impurity ion therefore injected distant, the follow-up high temperature from raceway groove
Diffusion process is also difficult to be diffused in device channel p-type ion, the cut-in voltage V to deviceTHAnd conducting
Resistance RdonImpact the least.And owing to injecting the physical structural characteristic stopping side wall 7 self so that it is wide
Degree (will not inject in the embodiment using dry etching and stop that the width of side wall 7 is typically about equal to grid oxygen greatly
Change layer 3 and the gross thickness of polysilicon gate 4), therefore can guarantee that a bigger p type impurity ion implanting
Region, can significantly decrease body district resistance Rb。
Note the implantation dosage that the implantation dosage that this step P+ injects should inject less than N+ in step S140, no
Then can cause the cut-in voltage V of deviceTHExcessive.
S180, dielectric layer deposited on substrate and polysilicon gate.
In the present embodiment, non-impurity-doped silica glass (USG) and the double-decker of phosphorosilicate glass (PSG) are used
As dielectric layer.In other embodiments, it would however also be possible to employ other known dielectric layer material and other structures
(the dielectric layer structure of such as monolayer).
S190, carries out contact hole photoetching and etching, forms the contact hole of N+ source region.
Subsequent technique can use the power semiconductor manufacturing process of routine device manufacture to be completed.Such as
Carry out filler metal in contact hole, dielectric layer is formed front metal layer；Front metal layer is formed
Passivation layer；The steps such as the back process carrying out power transistor.
The manufacture method of above-mentioned power semiconductor active area, is injected by third time P+ and reduces body district electricity
Resistance Rb, therefore can be greatly improved the avalanche energy EAS of power device.Side wall 7 is stopped simultaneously because inject
Stopping, the p-type ion of injection, the most again will not be to the cut-in voltage V of device away from device channelTHWith lead
Energising resistance RdonProduce significantly impact, while not affecting device conventional parameter, improve device in perception
The reliability worked under load environment.
Inject and stop that side wall 7 also has good protective effect to gate oxide 3 and polysilicon gate 4.At note
Entering block media is Si3N4In embodiment double-deck with TEOS, Si3N4It is again very with TEOS simultaneously
Good barrier against impurities, the double-decker of two media mixing is more preferable to the blocking effect of impurity.
The injection of polysilicon, gate oxide and chip surface intersection stops that side wall 7 can also improve power
Cut-in voltage V in VDMOS and IGBT conventional parameterTHWith grid source and drain electricity IgssYield, thus improve
The yield that power device manufactures.In the follow-up double-deck embodiment of dielectric layer deposition USG and PSG,
After contact hole etching and metal sputtering complete, (with N+ in gate oxide 3 and polysilicon gate 4 and contact hole
Source region is connected) just there is Si between source metal3N4, TEOS, USG and PSG these four dielectric layer, right
More preferably, what contrast was conventional only has USG and PSG both dielectric layers for the isolation of foreign ion and blocking effect
Technique, grid source and drain electricity Igss can reduce further.Meanwhile, V is being carried outGSAnd VTHDuring test, Bu Huiyin
Dielectric layer PSG and USG is second-rate, and the least grid source breakdown voltage V occursGS(such as several volts), also
Do not have drain current IdValue too big and make VTHTest value show as close to 0 or a below 1V
The least value, i.e. VTHShort circuit or the phenomenon close to short-circuit failure.Therefore multi-dielectric (Si3N4、TEOS、USG、
PSG) structure being isolated is to improving VTHAnd IgssYield better.
Wherein in an embodiment, between step S140 and S150, also include with polysilicon gate 4
P+ injection is carried out, the step of implanting p-type foreign ion in p-well 1 for mask.This specification is by this step
P+ inject be referred to as second time P+ inject.On the basis of second time P+ is injected, increase third time P+ inject,
Body district resistance R can be reduced furtherb.The implantation dosage sum that P+ injects and third time P+ injects for the second time
The dosage injected less than the N+ of step S140.It has been observed that the implantation dosage that second time and third time P+ inject
As relatively big, p-type ion can be caused to enter raceway groove in follow-up diffusing step, increase the cut-in voltage of device
VTHWith conducting resistance Rdon.Wherein in an embodiment, the implantation dosage that P+ injects for the second time is
2E15cm-2～5E15cm-2；The implantation dosage that P+ injects for the third time is 1E15cm-2～4E15cm-2；N+ injects
Implantation dosage be 5E15cm-2～1.3E16cm-2.Further, P+ injects and third time P+ note for the second time
The little 2E15cm of implantation dosage that the implantation dosage sum entered should be injected than N+-2～4E15cm-2。
Wherein in an embodiment, step S150 is 1000 angstroms～3000 angstroms thickness of low-pressure chemical vapor phase deposition
Silicon nitride, and with tetraethyl orthosilicate for reactant low-pressure chemical vapor phase deposition 5000 angstroms～the two of 10000 angstroms
Silicon oxide.
Wherein in an embodiment, step S160 uses dry etching.
Wherein in an embodiment, a contact hole P+ can be carried out after step S190 again and inject the (the 4th
Secondary P+ injects), each cellular of device so can be made good with contacting of source electrode, it is to avoid indivedual cellulars are bad because of contact
This cellular generation avalanche breakdown is made to make device failure.The most this method can suitably reduce device body district resistance
Rb, avalanche energy EAS will be had further raising, and this method will not increase the unlatching electricity of device
Pressure VTHWith conducting resistance Rdon, be conducive to improving concordance and the formedness of the EAS of each tube core on disk.
But this method can increase manufacturing cost, it is adaptable to high-end customer and the power of the client high to EAS requirement
The manufacture of semiconductor device.For normal client, the strict technique controlling contact hole etching, contact hole is made to connect
Touch good.
Wherein in an embodiment, the foreign ion of four P+ injections is boron ion.In other embodiments
In, it is also possible to the p type impurity ion used for other those skilled in the art.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But can not therefore be construed as limiting the scope of the patent.It should be pointed out that, for this area
For those of ordinary skill, without departing from the inventive concept of the premise, it is also possible to make some deformation and change
Entering, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended power
Profit requires to be as the criterion.
Claims (10)
1. a manufacture method for power semiconductor active area, including:
Substrate is formed gate oxide；
Described gate oxide is formed polysilicon gate；
P-well is formed in described substrate；
Carry out N+ injection, in described p-well, form N+ source region；
Described substrate and polysilicon gate are formed and injects block media；
Photoetching also etches away the injection block media on described polysilicon gate, and described polysilicon gate both sides are residual
The injection block media stayed is formed to inject and stops side wall；
Stop that side wall carries out P+ injection for mask with described polysilicon gate and injection, inject in described p-well
P-type ion；The implantation dosage that the implantation dosage that described P+ injects injects less than described N+；
Dielectric layer deposited on described substrate and polysilicon gate；
Carry out contact hole photoetching and etching, form the contact hole of described N+ source region.
The manufacture method of power semiconductor active area the most according to claim 1, it is characterised in that
Described injection block media is double-decker, and described formation on substrate and polysilicon gate injects block media
Step, be successively to carry out silicon nitride deposition and tetraethyl orthosilicate deposit.
The manufacture method of power semiconductor active area the most according to claim 2, it is characterised in that
The described step forming injection block media on substrate and polysilicon gate, is low-pressure chemical vapor phase deposition
The silicon nitride of 1000 angstroms～3000 angstroms thickness, and with tetraethyl orthosilicate for reactant low-pressure chemical vapor phase deposition
5000 angstroms～the silicon dioxide of 10000 angstroms.
The manufacture method of power semiconductor active area the most according to claim 1, it is characterised in that
After the described step carrying out N+ injection, described formation on substrate and polysilicon gate inject block media
Before step, also include carrying out P+ injection with described polysilicon gate extremely mask, in described p-well, inject P
The step of type ion；Described carry out the step of P+ injection and described with polysilicon gate with polysilicon gate extremely mask
Pole and injection stop that the implantation dosage sum that side wall is this twice P+ injection of step that mask carries out P+ injection is little
In the implantation dosage that described N+ injects.
The manufacture method of power semiconductor active area the most according to claim 4, it is characterised in that
The described step carrying out P+ injection with polysilicon gate extremely mask, implantation dosage is 2E15cm-2～5E15cm-2；
Described with polysilicon gate with inject the step stopping that side wall carries out P+ injection for mask, implantation dosage is
1E15cm-2～4E15cm-2；The implantation dosage that described N+ injects is 5E15cm-2～1.3E16cm-2。
The manufacture method of power semiconductor active area the most according to claim 5, it is characterised in that
The implantation dosage sum that described twice P+ injects is less than the implantation dosage that described N+ injects
2E15cm-2～4E15cm-2。
The manufacture method of power semiconductor active area the most according to claim 1, it is characterised in that
The described step of dielectric layer deposited on substrate and polysilicon gate, is that deposit forms non-impurity-doped silica glass and phosphorus
The two-layered medium Rotating fields of silica glass.
The manufacture method of power semiconductor active area the most according to claim 1, it is characterised in that
After the step of the contact hole of described formation N+ source region, also include the step carrying out contact hole P+ injection.
The manufacture method of power semiconductor active area the most according to claim 1, it is characterised in that
Described photoetching also etches away the step injecting block media on polysilicon gate, is by and described polysilicon
The etching of the gross thickness uniform thickness of block media is injected on grid.
The manufacture method of power semiconductor active area the most according to claim 9, its feature exists
In, described photoetching also etches away the step injecting block media on polysilicon gate, is to use dry etching.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107516671A (en) * | 2017-08-17 | 2017-12-26 | 电子科技大学 | A kind of grid-controlled transistor device for improving turn-off characteristic |
| CN109671630A (en) * | 2019-01-30 | 2019-04-23 | 深圳市美浦森半导体有限公司 | A kind of manufacturing method improving DMOS device snowslide performance |
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| US5250449A (en) * | 1990-10-01 | 1993-10-05 | Nippondenso Co., Ltd. | Vertical type semiconductor device and method for producing the same |
| US5930630A (en) * | 1997-07-23 | 1999-07-27 | Megamos Corporation | Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure |
| CN1645624A (en) * | 2003-12-22 | 2005-07-27 | 半导体元件工业有限责任公司 | Semiconductor device having reduced gate charge and reduced on resistance and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250449A (en) * | 1990-10-01 | 1993-10-05 | Nippondenso Co., Ltd. | Vertical type semiconductor device and method for producing the same |
| US5930630A (en) * | 1997-07-23 | 1999-07-27 | Megamos Corporation | Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure |
| CN1645624A (en) * | 2003-12-22 | 2005-07-27 | 半导体元件工业有限责任公司 | Semiconductor device having reduced gate charge and reduced on resistance and method |
Cited By (3)
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| CN107516671A (en) * | 2017-08-17 | 2017-12-26 | 电子科技大学 | A kind of grid-controlled transistor device for improving turn-off characteristic |
| CN107516671B (en) * | 2017-08-17 | 2020-03-31 | 电子科技大学 | Gate-controlled thyristor device with improved turn-off characteristic |
| CN109671630A (en) * | 2019-01-30 | 2019-04-23 | 深圳市美浦森半导体有限公司 | A kind of manufacturing method improving DMOS device snowslide performance |
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