CN103943671A - Power semiconductor device and forming method thereof - Google Patents
Power semiconductor device and forming method thereof Download PDFInfo
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- CN103943671A CN103943671A CN201310025255.9A CN201310025255A CN103943671A CN 103943671 A CN103943671 A CN 103943671A CN 201310025255 A CN201310025255 A CN 201310025255A CN 103943671 A CN103943671 A CN 103943671A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 66
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 109
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 105
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 105
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 95
- 239000011248 coating agent Substances 0.000 claims description 55
- 238000000576 coating method Methods 0.000 claims description 55
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 28
- 238000002513 implantation Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000005036 potential barrier Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 42
- 230000007547 defect Effects 0.000 description 18
- 238000005755 formation reaction Methods 0.000 description 18
- 230000002950 deficient Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- -1 boron ion Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011799 hole material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a power semiconductor device and a forming method thereof, and belongs to the technical field of semiconductor devices. According to the above power semiconductor device provided by the invention, the collector layer is a germanium layer or a silicon germanium layer. Compared with a silicon layer, under the same doping concentration, the germanium layer or the silicon germanium layer has higher carrier mobility, lower contact potential barrier and lower carrier service life, such that conduction voltage reduction and turn-off time of the power semiconductor device disclosed by the invention is reduced, the manufacturing cost of the power semiconductor device is not improved, and the problems of large conduction voltage reduction and long turn-off time of the power semiconductor device in the prior art can be solved on the premise that the manufacturing cost is not improved.
Description
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of power semiconductor and forming method thereof.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviation IGBT) the compound full-control type voltage driven type power semiconductor being formed by double pole triode (BJT) and insulating gate type field effect tube (MOSFET), the high input impedance and the power transistor that have MOSFET device concurrently (are huge transistor, the advantage of low conduction voltage drop two aspects abbreviation GTR), because IGBT has advantages of the little and saturation pressure of driving power, reduce, IGBT is widely applied to every field as a kind of novel power electronic device at present.
Preparation technology at conventional IGBT comprises: provide substrate, the positive technique of described substrate, the back process of described substrate.Wherein, the positive technique of described substrate, comprising: the techniques such as the front to described substrate is oxidized, Implantation, exposure, deposit and etching, form PN junction, gate electrode and emitter pattern in the front of described substrate; The back process of described substrate, comprising: the back side of described substrate is carried out to the techniques such as burn into grinding, Implantation and annealing, at the back side of described substrate, form collector layer.
Yet, in prior art, utilize the conduction voltage drop of the IGBT device that above-mentioned technique forms higher, the turn-off time is longer.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of power semiconductor and forming method thereof, and the conduction voltage drop of this power semiconductor is less, and the turn-off time is shorter.
For addressing the above problem, the embodiment of the present invention provides following technical scheme:
A power semiconductor, in described power semiconductor, collector layer is germanium layer or germanium-silicon layer.
Preferably, the thickness of described germanium layer or germanium-silicon layer is greater than 0.01 μ m.
Preferably, the thickness of described germanium layer or germanium-silicon layer is 0.2 μ m-5 μ m, comprises endpoint value.
Preferably, when described power semiconductor is punch power semiconductor, described power semiconductor also comprises: the resilient coating between described substrate and collector layer.
Preferably, when described collector layer is germanium-silicon layer, described resilient coating is silicon layer or germanium-silicon layer.
Preferably, when described collector layer is germanium layer, described resilient coating is silicon layer, germanium layer or germanium-silicon layer.
Preferably, the thickness of described resilient coating is 1 μ m-20 μ m, comprises endpoint value.
Preferably, in described germanium-silicon layer the atomic percent of germanium for being more than or equal to 10%.
Preferably, when described resilient coating is germanium-silicon layer, and described collector layer is while being germanium-silicon layer, and in described resilient coating, the atomic percent of germanium is less than the atomic percent of germanium in described collector layer.
A formation method for power semiconductor, comprising: substrate is provided; Described substrate back is carried out after attenuate, at the back side of described substrate, form collector layer; Wherein, described collector layer is germanium layer or germanium-silicon layer.
Preferably, also comprise: implanting impurity ion in described germanium layer or germanium-silicon layer; The mode that adopts annealing, activates the foreign ion in described germanium layer or germanium-silicon layer.
Preferably, the foreign ion of described collector layer is boron ion.
Preferably, the Implantation Energy of the foreign ion of described collector layer is 20KeV-100KeV, comprises endpoint value.
Preferably, the implantation dosage of the foreign ion of described collector layer is 10
12/ cm
2-10
16/ cm
2, comprise endpoint value.
Preferably, when described power semiconductor is punch power semiconductor, also comprise:
Between described substrate and collector layer, form resilient coating.
Preferably, when described collector layer is germanium-silicon layer, described resilient coating is silicon layer or germanium-silicon layer.
Preferably, when described collector layer is germanium layer, described resilient coating is silicon layer, germanium layer or germanium-silicon layer.
Preferably, when described resilient coating is silicon layer, between described substrate and collector layer, forms resilient coating and comprise: the substrate back after attenuate is carried out to Implantation; The mode that adopts annealing, activates the foreign ion in described substrate, forms resilient coating.
Preferably, when described resilient coating is germanium layer or germanium-silicon layer, between described substrate and collector layer, forms resilient coating and comprise: the substrate back after attenuate forms germanium layer or germanium-silicon layer.
Preferably, also comprise: implanting impurity ion in described germanium layer or germanium-silicon layer; The mode that adopts annealing, activates the foreign ion in described germanium layer or germanium-silicon layer.
Preferably, the formation technique of described germanium layer or germanium-silicon layer is epitaxy technique or depositing technics.
Preferably, the activationary temperature of described foreign ion is 300 ℃-500 ℃, comprises endpoint value.
Preferably, the activationary temperature of described foreign ion is 400 ℃.
Preferably, the time of described annealing is 10s-120min, comprises endpoint value.
Preferably, the time of described annealing is 10min-30min, comprises endpoint value.
Compared with prior art, technique scheme has the following advantages:
In power semiconductor that the embodiment of the present invention provides and forming method thereof, described collector layer is germanium layer or germanium-silicon layer.Compared to silicon layer, under identical doping content, in described germanium layer or germanium-silicon layer, there is larger carrier mobility, lower contact berrier and lower carrier lifetime, thereby reduced conduction voltage drop and the turn-off time of described power semiconductor, and do not improved the cost of manufacture of described power semiconductor.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of substrate face structure in the power semiconductor that Fig. 1 provides for the embodiment of the present invention one;
The overall structure schematic diagram of the power semiconductor that Fig. 2 provides for the embodiment of the present invention one;
The overall structure schematic diagram that Fig. 3 is the power semiconductor that provides in one embodiment of the invention;
The overall structure schematic diagram of the power semiconductor that Fig. 4 provides for another embodiment of the present invention;
The overall structure schematic diagram of the power semiconductor that Fig. 5 provides for the embodiment of the present invention two.
Embodiment
Just as described in the background section, the conducting voltage of the IGBT device forming in prior art is higher, and the turn-off time is longer.
Inventor studies discovery, and this is mainly because the material of collector layer is monocrystalline silicon, polysilicon or amorphous silicon described in prior art.In the preparation technology of conventional IGBT device, the annealing process that forms backside collector layer mainly adopts common annealing, its annealing temperature is subject to the impact of described IGBT device front metal aluminium electrode, maximum temperature is less than 500 ℃, and be subject to the restriction of annealing temperature, because annealing temperature is lower, cause foreign ion in the collector layer activity ratio in silicon lower, cause in prior art in IGBT device, in described collector layer, the activity ratio of impurity is generally less than 10%, thereby make the conducting voltage of described IGBT device higher, the turn-off time is longer.
In order to address the above problem, a solution of the prior art is to adopt laser annealing to substitute the common annealing in described collector layer forming process, thereby avoid foreign ion in the collector layer activity ratio in silicon to be subject to the restriction of annealing temperature, make the higher impurity activation rate of acquisition in described collector layer, but, because the equipment of laser annealing is very expensive, cause utilizing laser annealing to form the cost of IGBT device of collector layer higher, apply less.
In view of this, the invention provides a kind of semiconductor device and forming method thereof.The formation method of semiconductor device provided by the present invention, comprising: substrate is provided; Described substrate back is carried out after attenuate, at the back side of described substrate, form collector layer; Wherein, described collector layer is germanium layer or germanium-silicon layer.
Accordingly, also provide the semiconductor device forming by said method in the present invention, the collector layer in this semiconductor device is germanium layer or germanium-silicon layer.
Due to compared to silicon layer, under identical doping content, in described germanium layer or germanium-silicon layer, there is larger carrier mobility, lower contact berrier and lower carrier lifetime, thereby reduced conduction voltage drop and the turn-off time of IGBT device provided by the present invention, and do not improved the cost of manufacture of described IGBT device.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Power semiconductor provided by the present invention is preferably IGBT device, and the embodiment of the present invention be take described power semiconductor and described as IGBT device as example.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
Embodiment mono-:
The formation method of power semiconductor provided by the present invention comprises:
As shown in Figure 1, provide substrate 10, described substrate 10 can adopt silicon substrate, and described silicon substrate can be N-type silicon substrate or P type silicon substrate in theory.In the embodiment of the present invention, the described substrate 10 of take is described as N-type silicon substrate as example.
At positive grid structure 20 and the emitter structure of forming of described substrate 10, complete the positive technique of described substrate 10.
Described grid structure 20 comprises: be formed at the gate dielectric layer 201 in described substrate 10 fronts and the gate electrode layer 202 that is formed at described gate dielectric layer 201 surfaces.In embodiments of the present invention, described gate dielectric layer 201 is oxide layer, and described gate electrode layer 202 is polysilicon gate, but in other embodiments of the invention, described gate dielectric layer 201 and gate electrode layer 202 can be also other material, as described in gate dielectric layer 201 can be SrTiO
3, HfO
2or ZrO
2deng, described gate electrode layer 202 can be metal etc., the present invention does not limit this.In addition, described grid structure 20 also comprises grid passivation layer 203, described grid passivation layer 203 is wrapped in the sidewall of described gate dielectric layer 201 and gate electrode layer 202 and the upper surface of described gate electrode layer 202, covers described gate dielectric layer 201 and gate electrode layer 202 completely.
Described emitter structure comprises: be formed at the P type well region 301 in described substrate 10 and be formed at the N-type source/drain region 302 in described P type well region 301, and described P type well region 301 is concordant with the front of described substrate 10 with the surface in described N-type source/drain region 302.In addition, described emitter structure also comprises conduction electrode layer 303, and described conduction electrode layer 303 covers P type well region 301 and described N-type source/drain region 302 completely, and described in be formed at the grid structure 20 in described substrate 10 fronts.In embodiments of the present invention, described conduction electrode layer 303 is metal electrode layer, is preferably aluminium electrode layer.
Because the positive technique that forms grid structure 20 and emitter structure of described substrate 10 is known by those skilled in the art, the present invention no longer describes in detail this.
Complete after the positive technique of described substrate 10, attenuate is carried out in the back side of described substrate 10, in embodiments of the present invention, can adopt the method that the back side of described substrate 10 is ground and corroded, remove the part backing material at described substrate 10 back sides, be about to described substrate 10 thinning back sides.In other embodiments of the invention, can adopt other method, by the thinning back side of described substrate 10, the present invention does not limit this yet.
It should be noted that, according to the structure of power semiconductor provided by the present invention and the difference of applied electric pressure thereof, the thickness of described substrate 10 after thinning back side is not identical yet, is determined on a case-by-case basis.
As shown in Figure 2, described substrate 10 back sides are carried out after attenuate, at described substrate 10 back sides, form collector layer 40, wherein, described collector layer 40 is germanium layer or germanium-silicon layer.In embodiments of the present invention, the formation technique of described germanium layer or germanium-silicon layer can adopt epitaxy technique, also can adopt the techniques such as deposit, in one embodiment of the invention, the thickness of described germanium layer or germanium-silicon layer is greater than 0.01 μ m, is preferably 0.2 μ m-5 μ m, comprises endpoint value, the present invention does not limit this, is determined on a case-by-case basis.
As shown in Figure 3, in one embodiment of the invention, described collector layer 40 is germanium layer, because the lattice mismatch between silicon and germanium is larger, in described substrate 10 and the interface of described germanium layer, form the region that defect concentration is higher, and this defect area is arranged in the energy gap of germanium layer, thereby can be from described germanium layer trapped electron, in described germanium layer, form the doping of P type, and described substrate 10 region higher with the defect concentration of the interface formation of described germanium layer, after trapped electron, also can form P type doped region.
In described substrate 10 and the interface of collector layer 40, there is the region that defect concentration is higher.Wherein, described defect mainly comprises line dislocation.But deviate from the direction of described substrate 10 along described collector layer 40, the density of the line dislocation in described germanium layer reduces gradually, corresponding defect concentration also decreases.Therefore, at described substrate 10 back sides, form after germanium layer, the first higher territory, p type island region 401 of defect concentration that can be positioned at described substrate 10 back sides at described substrate 10 back side self-assembling formations, it is defective p Ge region, the second p type island region territory 402 lower with the defect concentration that is positioned at 401 surfaces, described the first territory, p type island region, it is p Ge region, two regions, be that the collector layer 40 that provides in the embodiment of the present invention is by the first higher territory, p type island region 401 of defect concentration, it is defect ive p Ge region, the second p type island region territory 402 lower with defect concentration, it is p Ge region, two parts form.
As shown in Figure 4, in another embodiment of the present invention, described collector layer 40 is germanium-silicon layer, and the silicon in described germanium-silicon layer and germanium can mix according to arbitrary proportion, and preferred, in described germanium-silicon layer, the atomic percent of germanium is preferably more than or equals 10%.In like manner, because the lattice mismatch between silicon and SiGe is also larger, also can form the region that defect concentration is higher in described substrate 10 and the interface of described germanium-silicon layer, and the region that described defect concentration is higher, meeting trapped electron from described germanium-silicon layer, thus the doping of P type in described germanium-silicon layer, formed, and described substrate 10 region higher with the defect concentration of the interface formation of described germanium-silicon layer, after trapped electron, also can form P type doped region.
Owing to deviating from the direction of described substrate 10 along described collector layer 40, line dislocation density in described germanium-silicon layer reduces gradually, defect in described germanium-silicon layer also decreases, thereby the first higher territory, p type island region 401 of defect concentration that is positioned at described substrate 10 back sides at described substrate 10 back side self-assembling formations, it is defective p SiGe region, the second p type island region territory 402 lower with the defect concentration that is positioned at a described P type silicon Germanium regions surface, it is p SiGe region, two regions, be that the collector layer 40 that provides in the embodiment of the present invention is by the first higher territory, p type island region 401 of defect concentration, it is defective p SiGe region, the second p type island region territory 402 lower with defect concentration, it is p SiGe region, two parts form.
Owing to comparing with silicon layer, in germanium layer or in germanium-silicon layer, there is larger carrier mobility and lower contact berrier, thereby make under identical doping content, in germanium layer or germanium-silicon layer, there is lower tagma resistance and contact resistance, and then make the power semiconductor that described collector layer 40 is germanium layer or germanium-silicon layer there is lower conduction voltage drop.
And, compare with silicon layer, in germanium layer or in germanium-silicon layer, there is lower carrier lifetime, when the PN junction positively biased at described substrate 10 back sides, electron current density from the described collector layer 40 of the interior inflow of described substrate 10 is larger, thereby strengthened the Extracting Ability of charge carrier in 40 pairs of described substrates 10 of described collector layer, in the process that makes to turn-off at described power semiconductor, in described substrate 10, in electronics and described collector layer 40, hole has recombination velocity faster, and then accelerated the turn-off speed of described power semiconductor, shortened the turn-off time of described power semiconductor.
When doping content in described collector layer 40 is higher, method for forming semiconductor devices provided by the present invention also comprises: implanting impurity ion in described germanium layer or germanium-silicon layer, and adopt the mode of annealing, activate the foreign ion in described germanium layer or germanium-silicon layer.
In one embodiment of the invention, this detailed process can be: after described substrate 10 back sides form germanium layers or germanium-silicon layer, described germanium layer or germanium-silicon layer are carried out to Implantation, thereby in described germanium layer or germanium-silicon layer dopant implant ion.When inject the foreign ion satisfying the demands in described germanium layer or germanium-silicon layer after, adopt the mode of annealing, activate the foreign ion in described germanium layer or germanium-silicon layer, form final collector layer 40.
In one embodiment of the invention, described foreign ion is boron ion.In other embodiments of the invention, described foreign ion can be also other P type ion, and the present invention does not limit this.
Because described p type impurity ion has lower activationary temperature in described germanium layer or germanium-silicon layer, general in the temperature range of 300 ℃-500 ℃, can activate completely, thereby make the power semiconductor providing in the embodiment of the present invention, only need to adopt common annealing, just can obtain higher impurity activation rate.And the formation technique of described germanium layer or germanium-silicon layer, form process compatible with power semiconductor of the prior art, can not increase extra cost of manufacture, can not bring the problem such as stain yet.
Therefore, in the power semiconductor formation method providing in the embodiment of the present invention, the temperature of described annealing, the activationary temperature of foreign ion is 300 ℃-500 ℃, comprises endpoint value, is preferably 400 ℃; Described annealing time is 10s-120min, comprises endpoint value, is preferably 10min-30min, comprises endpoint value, but the present invention do not limit this, and concrete selection is determined on a case-by-case basis.
Due to conduction voltage drop and the turn-off time of described power semiconductor, the impact that distributed by plasma that in substrate 10, electronics and hole form, but because the doping content in substrate 10 is lower, the foundation of described plasma, mainly by injection and hole and substrate 10 front injected electrons in described substrate 10 back side PN junctions, form, and in described plasma, the concentration of electronics is approximately equal to the concentration in hole, is electric neutrality.When in described plasma, the concentration in electronics and hole is higher, the conduction voltage drop of described power semiconductor is less, and the turn-off time is shorter.
Therefore, accurately the position of the PN junction of the described substrate 10 of control and 40 formation of collector layer and the doping ion concentration in described collector layer 40, most important to reducing the conduction voltage drop of described power semiconductor and the turn-off time of the described power semiconductor of shortening.And PN junction position in described power semiconductor, Implantation Energy while injected by described germanium layer or germanium-silicon layer intermediate ion affects, concentration impurity ion in described collector layer 40, the implantation dosage while injected by described germanium layer or germanium-silicon layer intermediate ion affects.
So, in order to reduce the conduction voltage drop of power semiconductor provided by the present invention, shorten the turn-off time of power semiconductor provided by the present invention, in one embodiment of the invention, the Implantation Energy of described foreign ion is preferably 20KeV-100KeV, comprises endpoint value; In another embodiment of the present invention, the implantation dosage of described foreign ion is preferably 10
12/ cm
2-10
16/ cm
2, comprise endpoint value.
It should be noted that, at 300 ℃-500 ℃, comprise under the condition of endpoint value, the diffusion coefficient of described p type impurity ion in described germanium layer or germanium-silicon layer is very low, therefore, by selecting Implantation Energy and the implantation dosage of described foreign ion can accurately control the PN junction position in power semiconductor provided by the present invention, and near the doping ion distribution described PN junction, thereby conduction voltage drop and the turn-off time of described power semiconductor controlled.
Also it should be noted that, in power semiconductor formation method provided by the present invention, can also be by selecting suitable germanium layer or the Implantation Energy of germanium-silicon layer thickness and magazine ion, described PN junction is formed in described substrate 10, thereby reduces the leakage current of power semiconductor provided by the present invention under blocking-up condition.
In sum, in semiconductor device provided by the present invention and forming method thereof, described collector layer 40 is germanium layer or germanium-silicon layer, compared to silicon layer, under identical doping content, in described germanium layer or germanium-silicon layer, there is larger carrier mobility, lower contact berrier and lower carrier lifetime, thus conduction voltage drop and the turn-off time of having reduced described power semiconductor, and do not improve the cost of manufacture of described power semiconductor.
Embodiment bis-:
Power semiconductor provided by the present invention comprises punch power semiconductor and non-punch power semiconductor.As shown in Figure 5, when described power semiconductor is punch power semiconductor, power semiconductor provided by the present invention also comprises: the resilient coating 50 between described substrate 10 and collector layer 40.The doping type of described resilient coating 50 is contrary with the doping type of described collector layer 40, thereby makes described resilient coating 50 and collector layer 40 form PN junction.Concrete, when described collector layer 40 adulterates for P type, described resilient coating 50 is N-type doping; When described collector layer 40 adulterates for N-type, described resilient coating 50 is the doping of P type.The embodiment of the present invention be take described power semiconductor as punch power semiconductor, and the collector layer in described punch power semiconductor is that P type is doped to example, and power semiconductor provided by the present invention and forming method thereof is elaborated.
When described power semiconductor is punch power semiconductor, the formation method of power semiconductor provided by the present invention, also comprises: between described substrate 10 and collector layer 40, form resilient coating 50.When described collector layer 40 is germanium-silicon layer, described resilient coating 50 can be silicon layer, can be also germanium-silicon layer; When described collector layer 40 is germanium layer, described resilient coating 50 can silicon layer, can be also germanium-silicon layer, can also be germanium layer.Wherein, the silicon in described germanium-silicon layer and germanium can mix according to arbitrary proportion, and preferred, in described germanium-silicon layer, the atomic percent of germanium is for being more than or equal to 10%.It should be noted that, when described resilient coating 50 is germanium-silicon layer, and described collector layer 40 is while being also germanium-silicon layer, and in described resilient coating 50, the atomic percent of germanium is less than the atomic percent of germanium in described collector layer 40.
In one embodiment of the invention, described resilient coating 50 is silicon layer, forms resilient coating 50 and comprise between described substrate 10 and described collector layer 40: Implantation is carried out in substrate 10 back sides after attenuate, thereby at the interior formation doped region of described substrate 10.After the foreign ion that the interior injection of described substrate 10 satisfies the demands, adopt the mode of annealing, activate the foreign ion in described substrate 10, form resilient coating 50.
In another embodiment of the present invention, described resilient coating 50 is germanium layer or germanium-silicon layer, forms resilient coating 50 and comprise between described substrate 10 and described collector layer 40: substrate 10 back sides after attenuate form germanium layer or germanium-silicon layer.In embodiments of the present invention, the formation technique of described germanium layer or germanium-silicon layer can adopt epitaxy technique, also can adopt the techniques such as deposit, and the present invention does not limit this, is determined on a case-by-case basis.
When described resilient coating 50 is germanium layer or germanium-silicon layer, the formation method that the embodiment of the present invention provides, also comprises: implanting impurity ion in described germanium layer or germanium-silicon layer, and adopt the mode of annealing, activate the foreign ion in described germanium layer or germanium-silicon layer.In of the present invention one concrete enforcement, this detailed process can comprise: after described substrate 10 back sides form germanium layers or germanium-silicon layer, described germanium layer or described germanium-silicon layer are carried out to Implantation, thereby in described germanium layer or germanium-silicon layer dopant implant ion; When inject the foreign ion satisfying the demands in described germanium layer or germanium-silicon layer after, adopt the mode of annealing, activate the foreign ion in described germanium layer or germanium-silicon layer, form resilient coating 50.
The temperature of described annealing in one embodiment of the invention, the activationary temperature of foreign ion, preferably, at 300 ℃-500 ℃, comprises in the temperature range of endpoint value, is more preferably 400 ℃; Described annealing time, preferably at 10s-120min, comprises in the scope of endpoint value, more preferably at 10min-30min, comprise in the scope of endpoint value, but the present invention does not limit this, and concrete selection is determined on a case-by-case basis.
It should be noted that, in an embodiment of the present invention, the thickness of described resilient coating 50 is preferably 1 μ m-20 μ m, comprise endpoint value, and the foreign ion in described resilient coating 50 can be phosphonium ion, also can other N-type ion, as long as described substrate 10 in or the N-type resilient coating 50 that meets the demands of substrate 10 back sides formation, the present invention does not limit this.Also it should be noted that, in embodiments of the present invention, the doping content in described resilient coating 50 is higher than the doping content of described collector layer 40.
Due to compared to silicon layer, in germanium layer or in germanium-silicon layer, there is larger carrier mobility and lower contact berrier, thereby make under identical doping content, in germanium layer or germanium-silicon layer, there is lower tagma resistance and contact resistance, therefore, when described resilient coating 50 is germanium layer or germanium-silicon layer, the power semiconductor that the embodiment of the present invention provides has lower conduction voltage drop.
And, compared to silicon layer, in germanium layer or in germanium-silicon layer, there is lower carrier lifetime, when the PN junction positively biased at described substrate 10 back sides, electron current density from the described collector layer 40 of the interior inflow of described substrate 10 is larger, thereby strengthened in the Extracting Ability of charge carrier in 40 pairs of described substrates 10 of described collector layer, the process that makes to turn-off at described power semiconductor, electronics and hole in described resilient coating 50 have recombination velocity faster, and then have accelerated the turn-off speed of described power semiconductor.Therefore,, when described resilient coating 50 is germanium layer or germanium-silicon layer, the power semiconductor that the embodiment of the present invention provides has the shorter turn-off time.
It should be noted that, because the energy gap (being bandwidth) of germanium-silicon layer is directly proportional to the atomic percent of germanium in described germanium-silicon layer, therefore, when described resilient coating 50 is germanium layer or germanium-silicon layer, and when collector layer 40 is also germanium layer or germanium-silicon layer, by described resilient coating 50 and relative germanium atom percentage in collector layer 40 are rationally set, can in described power semiconductor, form and level and smooth continuous can be with distribution, thereby be conducive to the injection in hole, accelerate the turn-off speed of described power semiconductor.
Also it should be noted that, the power semiconductor that the described power semiconductor of all take in the embodiment of the present invention is planar gate structure is example, power semiconductor provided by the present invention is described, but power semiconductor provided by the present invention is not limited in the power semiconductor into planar gate structure, be equally applicable to trench gate type power semiconductor, the present invention does not limit this.
In sum, in power semiconductor that the embodiment of the present invention provides and forming method thereof, described collector layer 40 is germanium layer or germanium-silicon layer.Compared to silicon layer, under identical doping content, in described germanium layer or germanium-silicon layer, there is larger carrier mobility, lower contact berrier and lower carrier lifetime, thereby reduced conduction voltage drop and the turn-off time of described power semiconductor, and do not improved the cost of manufacture of described power semiconductor.
And, when described power semiconductor is punch power semiconductor, the material of described resilient coating 50 can be also germanium layer or germanium-silicon layer, thereby further reduce conduction voltage drop and the turn-off time of punch power semiconductor, and do not improve the cost of manufacture of described punch power semiconductor.
In this specification, various piece adopts the mode go forward one by one to describe, and each part stresses is the difference with other parts, between various piece identical similar part mutually referring to.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the present invention.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (25)
1. a power semiconductor, is characterized in that, in described power semiconductor, collector layer is germanium layer or germanium-silicon layer.
2. power semiconductor according to claim 1, is characterized in that, the thickness of described germanium layer or germanium-silicon layer is greater than 0.01 μ m.
3. power semiconductor according to claim 2, is characterized in that, the thickness of described germanium layer or germanium-silicon layer is 0.2 μ m-5 μ m, comprises endpoint value.
4. power semiconductor according to claim 1, is characterized in that, when described power semiconductor is punch power semiconductor, described power semiconductor also comprises: the resilient coating between described substrate and collector layer.
5. power semiconductor according to claim 4, is characterized in that, when described collector layer is germanium-silicon layer, described resilient coating is silicon layer or germanium-silicon layer.
6. power semiconductor according to claim 4, is characterized in that, when described collector layer is germanium layer, described resilient coating is silicon layer, germanium layer or germanium-silicon layer.
7. power semiconductor according to claim 4, is characterized in that, the thickness of described resilient coating is 1 μ m-20 μ m, comprises endpoint value.
8. according to the power semiconductor described in claim 1-7 any one, it is characterized in that, in described germanium-silicon layer, the atomic percent of germanium is for being more than or equal to 10%.
9. power semiconductor according to claim 8, is characterized in that, when described resilient coating is germanium-silicon layer, and described collector layer is while being germanium-silicon layer, and in described resilient coating, the atomic percent of germanium is less than the atomic percent of germanium in described collector layer.
10. a formation method for power semiconductor, is characterized in that, comprising:
Substrate is provided;
Described substrate back is carried out after attenuate, at the back side of described substrate, form collector layer;
Wherein, described collector layer is germanium layer or germanium-silicon layer.
11. formation methods according to claim 10, is characterized in that, also comprise:
Implanting impurity ion in described germanium layer or germanium-silicon layer;
The mode that adopts annealing, activates the foreign ion in described germanium layer or germanium-silicon layer.
12. according to the formation method described in claim 10 or 11, it is characterized in that, the foreign ion of described collector layer is boron ion.
13. according to the formation method described in claim 10 or 11, it is characterized in that, the Implantation Energy of the foreign ion of described collector layer is 20KeV-100KeV, comprises endpoint value.
14. according to the formation method described in claim 10 or 11, it is characterized in that, the implantation dosage of described collector layer foreign ion is 10
12/ cm
2-10
16/ cm
2, comprise endpoint value.
15. according to the formation method described in claim 10-14 any one, it is characterized in that, when described power semiconductor is punch power semiconductor, also comprises: between described substrate and collector layer, form resilient coating.
16. formation methods according to claim 15, is characterized in that, when described collector layer is germanium-silicon layer, described resilient coating is silicon layer or germanium-silicon layer.
17. formation methods according to claim 15, is characterized in that, when described collector layer is germanium layer, described resilient coating is silicon layer, germanium layer or germanium-silicon layer.
18. according to the formation method described in claim 16 or 17, it is characterized in that, when described resilient coating is silicon layer, forms resilient coating and comprise between described substrate and collector layer:
Substrate back after attenuate is carried out to Implantation;
The mode that adopts annealing, activates the foreign ion in described substrate, forms resilient coating.
19. according to the formation method described in claim 16 or 17, it is characterized in that, when described resilient coating is germanium layer or germanium-silicon layer, forms resilient coating and comprise between described substrate and collector layer:
Substrate back after attenuate forms germanium layer or germanium-silicon layer.
20. formation methods according to claim 19, is characterized in that, also comprise:
Implanting impurity ion in described germanium layer or germanium-silicon layer;
The mode that adopts annealing, activates the foreign ion in described germanium layer or germanium-silicon layer.
21. according to the formation method described in any one in claim 10-14,16-17 or 20, it is characterized in that, the formation technique of described germanium layer or germanium-silicon layer is epitaxy technique or depositing technics.
22. according to the formation method described in any one in claim 11-14,16-17 or 20, it is characterized in that, the activationary temperature of described foreign ion is 300 ℃-500 ℃, comprises endpoint value.
23. formation methods according to claim 22, is characterized in that, the activationary temperature of described foreign ion is 400 ℃.
24. according to the formation method described in any one in claim 11-14,16-17 or 20, it is characterized in that, the time of described annealing is 10s-120min, comprises endpoint value.
25. formation methods according to claim 24, is characterized in that, the time of described annealing is 10min-30min, comprises endpoint value.
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