CN113241377A - IGBT structure capable of improving high temperature resistance and radiation resistance and preparation method thereof - Google Patents
IGBT structure capable of improving high temperature resistance and radiation resistance and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention discloses an IGBT structure for improving high temperature resistance and radiation resistance, which comprises an active area cellular structure and a non-active area terminal structure, wherein the active area cellular structure comprises: an N-type semiconductor substrate; a plurality of column-shaped N-type doped regions formed on the back surface of the semiconductor substrate; the P-type collector region is formed on the back surface of the columnar N-type doped region; a collector metal layer formed on the back of the P-type collector region; the N-type CS layer is formed on the front surface of the semiconductor substrate; a P well layer formed on the front surface of the N-type CS layer; the highly doped P + region is formed on the front surface of the P well layer; the trench gates are formed in the highly doped P + regions, and N + emitting regions are arranged on the outer sides of the front surfaces of the trench gates; a grid metal layer is arranged on the surface of the trench gate; and emitter metal layers are arranged on the surfaces of the highly doped P + region and the N + emitting region. The invention can not only reduce the leakage current of the device, but also improve the high temperature resistance and radiation resistance of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to an IGBT structure capable of improving high temperature resistance and radiation resistance and a preparation method thereof.
Background
Insulated Gate Bipolar transistor (igbt) as a new power semiconductor device has become a new generation of mainstream products in the field of power electronics, and is widely applied to the fields of new energy automobiles, energy generation, consumer electronics, rail transit, aerospace, intelligent home appliances and the like. The insulated gate bipolar transistor integrates a MOSFET structure and a BJT structure and has the characteristics of the two devices. Compared with current control devices such as thyristors, the device has the advantages of controllability, safe working area, turn-off loss, auxiliary drive circuits and the like; compared with voltage control devices such as field effect transistors, the power control device has the advantages of power capacity, voltage level, current level and the like.
Compared with a planar IGBT device, the trench gate IGBT has lower on-resistance, optimizes the contradiction between the on-resistance and the turn-off speed of the IGBT, and generally adds an N-type CS layer under a P-type body region to obtain better conductance modulation effect. With the continuous maturity and the continuous improvement of performance of the IGBT product technology, the performance of high temperature resistance and radiation resistance of the IGBT device is put forward higher requirements.
According to the single-particle burnout mechanism of the Si-based IGBT, the radiation-resistant measures are generally developed around three directions: firstly, the starting of a parasitic transistor is restrained, the base resistance of the transistor can be reduced by increasing the concentration of a P well region, in addition, the injection efficiency of an emitter of the transistor can be reduced by reducing the doping concentration and the junction depth of an N + source region, so that the quantity of electrons injected into an IGBT drift region (a collector of the transistor) is also reduced when the transistor is latched, and the transistor cannot be burnt out due to secondary breakdown; secondly, the area surrounded by the electric field is increased by adding the buffer layer, so that the secondary breakdown voltage of the device is improved; and thirdly, the service life of carriers in the drift layer is reduced, so that the recombination of electron-hole pairs excited by heavy ions is promoted. In conclusion, although the solutions can improve the single-particle burnout resistance of the device, the electrical characteristics of the IGBT device itself can be affected while changing the structural parameters, for example, the on-resistance and the threshold value can be degraded, and more research is needed in the aspect of the radiation resistance of the IGBT.
Disclosure of Invention
The invention aims to solve the problems, provides an IGBT structure capable of improving high temperature resistance and radiation resistance, can reduce leakage current of a device, and has a small current concentration area when a single event effect occurs, so that the high temperature resistance and radiation resistance of the device are improved.
An IGBT structure for improving high temperature resistance and radiation resistance comprises an active area cellular structure and a non-active area terminal structure, wherein the active area cellular structure comprises: an N-type semiconductor substrate; a plurality of column-shaped N-type doped regions formed on the back surface of the semiconductor substrate; the P-type collector region is formed on the back surface of the columnar N-type doped region; a collector metal layer formed on the back of the P-type collector region; the N-type CS layer is formed on the front surface of the semiconductor substrate; a P well layer formed on the front surface of the N-type CS layer; the highly doped P + region is formed on the front surface of the P well layer; a plurality of trench gates formed in the highly doped P + region, wherein the bottoms of the trench gates are located in the semiconductor substrate; an N + emitting region is arranged on the outer side of the front surface of the trench gate; a grid metal layer is arranged on the surface of the trench gate; and emitter metal layers are arranged on the surfaces of the highly doped P + region and the N + emitting region.
Preferably, the doping concentration of the columnar N-type doping region is greater than that of the N-type semiconductor substrate.
Preferably, adjacent columnar N-type doped regions are connected with each other or arranged at intervals.
Preferably, the trench gate includes polysilicon filled in the trench and an oxide layer for isolating the polysilicon from the inner wall of the trench.
Preferably, the non-active region termination structure includes: the semiconductor device comprises an N-type semiconductor substrate, a plurality of P-type field limiting rings formed on the front surface of the N-type semiconductor substrate, and a plurality of columnar N-type doped regions formed on the back surface of the N-type semiconductor substrate; the P-type collector region is formed on the back surface of the columnar N-type doped region; and the collector metal layer is formed on the back surface of the P-type collector region.
Preferably, adjacent columnar N-type doped regions are connected with each other.
Preferably, the adjacent P-type field limiting rings are arranged at intervals.
A preparation method of an IGBT structure for improving high temperature resistance and radiation resistance comprises the following steps:
providing an N-type semiconductor substrate; forming a plurality of column-shaped N-type doped regions on the back surface of the N-type semiconductor substrate; forming a P-type collector region on the back of the columnar N-type doped region; forming a collector metal layer on the back of the P-type collector region;
manufacturing an active area cellular structure: forming an N-type CS layer on the front surface of the N-type semiconductor substrate part; forming a P well layer on the front surface of the N-type CS layer; forming a highly doped P + region on the front surface of the P well layer; forming a plurality of trench gates in the highly doped P + region, wherein the bottoms of the trench gates are positioned in the semiconductor substrate; forming an N + emitting region on the outer side of the front surface of the trench gate; forming a grid metal layer on the surface of the trench gate; forming an emitter metal layer on the surfaces of the highly doped P + region and the N + emitter region;
manufacturing a non-active area terminal structure: and forming a plurality of P-type field limiting rings on the front surface of the N-type semiconductor substrate part.
Preferably, a plurality of column-shaped N-type doped regions in the cell region of the active region are connected with each other or arranged at intervals; and the plurality of columnar N-type doped regions positioned in the non-active region terminal region are mutually connected.
Preferably, the columnar N-type doped region is formed by means of ion implantation.
In order to realize the purpose, the invention adopts the technical scheme that:
the invention has the beneficial effects that:
1. the invention is provided with the column type N doped region, so that the leakage current of the device is reduced due to the reduction of the gain of the original PNP transistor on the back surface, and the high temperature resistance of the IGBT device is improved.
2. The distance between the column type N doped regions can be adjusted, so that a through type and non-through type alternating structure is obtained.
3. The preparation method provided by the invention has simple steps, can finish the preparation of the IGBT on the basis of the traditional IGBT preparation method by only adding a small number of steps, and is beneficial to large-scale popularization and application.
Drawings
FIG. 1 is a schematic structural view of example 1 of the present invention;
FIG. 2 is a schematic structural diagram of example 2 of the present invention;
fig. 3-12 are diagrams illustrating steps of an embodiment.
Detailed Description
The following detailed description of the present invention is given for the purpose of better understanding technical solutions of the present invention by those skilled in the art, and the present description is only exemplary and explanatory and should not be construed as limiting the scope of the present invention in any way.
Example 1
Referring to fig. 1, an IGBT structure for improving high temperature resistance and radiation resistance includes an active area cell structure and a non-active area terminal structure, where the active area cell structure includes: an N-type semiconductor substrate 4; a plurality of column-shaped N-type doped regions 3 formed on the back surface of the semiconductor substrate 4; the P-type collector region 2 is formed on the back of the columnar N-type doped region 3; a collector metal layer 1 formed on the back of the P-type collector region 2; an N-type CS layer 9 formed on the front surface of the semiconductor substrate 4; a P-well layer 7 formed on the front surface of the N-type CS layer 9; a highly doped P + region 6 formed on the front surface of the P well layer 7; a plurality of trench gates formed in the highly doped P + region 6, the bottom of the trench gates being located in the semiconductor substrate 4; an N + emitting region 8 is arranged on the outer side of the front surface of the trench gate; a grid metal layer 13 is arranged on the surface of the trench gate; the surfaces of the highly doped P + region 6 and the N + emitter region 8 are provided with an emitter metal layer 12.
In this embodiment, the doping concentration of the column-shaped N-type doped regions 3 is greater than that of the N-type semiconductor substrate 4, and the adjacent column-shaped N-type doped regions 3 are connected to form a whole region, so that the IGBT device is in a non-punch-through type alternately arranged structure.
In the present embodiment, the trench gate includes polysilicon 10 filled in the trench and an oxide layer 11 for isolating the polysilicon 10 from the inner wall of the trench.
In this embodiment, the non-active area termination structure includes: the semiconductor device comprises an N-type semiconductor substrate 4, a plurality of P-type field limiting rings 5 formed on the front surface of the N-type semiconductor substrate 4, and a plurality of column-shaped N-type doped regions 3 formed on the back surface of the N-type semiconductor substrate 4; the P-type collector region 2 is formed on the back of the columnar N-type doped region 3; and the collector metal layer 1 is formed on the back surface of the P-type collector region 2, the adjacent columnar N-type doped regions 3 are mutually connected to form a whole region, and the adjacent P-type field limiting rings 5 are arranged at intervals to form a P-type field limiting ring region.
Example 2
Referring to fig. 2, an IGBT structure for improving high temperature resistance and radiation resistance includes an active area cell structure and a non-active area terminal structure, where the active area cell structure includes: an N-type semiconductor substrate 4; a plurality of column-shaped N-type doped regions 3 formed on the back surface of the semiconductor substrate 4; the P-type collector region 2 is formed on the back of the columnar N-type doped region 3; a collector metal layer 1 formed on the back of the P-type collector region 2; an N-type CS layer 9 formed on the front surface of the semiconductor substrate 4; a P-well layer 7 formed on the front surface of the N-type CS layer 9; a highly doped P + region 6 formed on the front surface of the P well layer 7; a plurality of trench gates formed in the highly doped P + region 6, the bottom of the trench gates being located in the semiconductor substrate 4; an N + emitting region 8 is arranged on the outer side of the front surface of the trench gate; a grid metal layer 13 is arranged on the surface of the trench gate; the surfaces of the highly doped P + region 6 and the N + emitter region 8 are provided with an emitter metal layer 12.
In this embodiment, the doping concentration of the column-shaped N-type doped regions 3 is greater than that of the N-type semiconductor substrate 4, and a certain distance is formed between adjacent column-shaped N-type doped regions 3, so that the IGBT device has a structure in which the penetrating N-type doped regions are alternately arranged.
In the present embodiment, the trench gate includes polysilicon 10 filled in the trench and an oxide layer 11 for isolating the polysilicon 10 from the inner wall of the trench.
In this embodiment, the non-active area termination structure includes: the semiconductor device comprises an N-type semiconductor substrate 4, a plurality of P-type field limiting rings 5 formed on the front surface of the N-type semiconductor substrate 4, and a plurality of column-shaped N-type doped regions 3 formed on the back surface of the N-type semiconductor substrate 4; the P-type collector region 2 is formed on the back of the columnar N-type doped region 3; and the collector metal layer 1 is formed on the back surface of the P-type collector region 2, the adjacent columnar N-type doped regions 3 are mutually connected to form a whole region, and the adjacent P-type field limiting rings 5 are arranged at intervals to form a P-type field limiting ring region.
Example 3
A preparation method of an IGBT structure for improving high temperature resistance and radiation resistance comprises the following steps:
1) an N-type semiconductor substrate 4, specifically, a silicon wafer is provided, and the original zone-melting silicon single crystal is inspected, cleaned and dried.
2) As shown in fig. 3, the field oxidation forms an L0 layer alignment mark.
3) Manufacturing a non-active area terminal structure: forming a plurality of N-type semiconductor substrates 4 on partial front surfacePA field limiting ring 5. Specifically, the non-active region terminal structure is a P-field limiting ring region, as shown in fig. 4, a doping window of the field limiting ring region is photoetched, a sacrificial oxide layer is grown by sputtering, boron ions are implanted, then the sacrificial oxide layer is etched, and then the P-field limiting ring region is formed by advancing, annealing and oxidizing.
4) Manufacturing an active area cellular structure: forming an N-type CS layer 9 on the partial front surface of the N-type semiconductor substrate 4; forming a P well layer 7 on the front surface of the N-type CS layer 9; a highly doped P + region 6 is formed on the front surface of the P-well layer 7. Specifically, as shown in fig. 5, an active region doping window is etched, a sacrificial oxide layer is grown by sputtering, boron ions are implanted, then the sacrificial oxide layer is etched, then a P-well layer 7 is formed by performing annealing and oxidation, and similarly, a highly doped P + region 6 is formed by implanting boron ions and performing annealing, and an N-type CS layer 9 is formed by ion implantation.
5) Manufacturing an active area cellular structure: forming a plurality of trench gates in the highly doped P + region 6, wherein the bottoms of the trench gates are positioned in the semiconductor substrate 4; an N + emitter region 8 is formed outside the front surface of the trench gate.
The preparation method comprises the following steps:
as shown in fig. 6, the emitter doping window is first photoetched, a sacrificial oxide layer is grown by sputtering, phosphorus ions are implanted, then the sacrificial oxide layer is etched, then the N + emitter 8 is formed by advancing and annealing, and then silicon nitride and silicon dioxide layers are deposited on the surface.
As shown in fig. 7, a trench area window is etched, and the trench etching and damage layer removing process is performed to form a gate trench.
As shown in fig. 8, an oxide layer 11 is grown, polysilicon 10 is deposited and doped to fill the trench, the polysilicon 10 is etched and the oxide layer 11 is etched, the polysilicon 10 is selectively oxidized and silicon nitride and the pad oxide layer are etched, and phosphosilicate glass is deposited to form a polysilicon gate.
6) Forming a gate metal layer 13 on the surface of the trench gate; and forming an emitter metal layer 12 on the surfaces of the high-doped P + region 6 and the high-doped N + region 8.
As shown in fig. 9, windows of the emitter and polysilicon gate contact regions are etched, a metal aluminum film is sputtered on the surface, an aluminum metallization pattern is etched back to form a top gate metal layer 13 and an emitter metal layer 12, and then passivation, specifically, a silicon nitride passivation film is deposited and a passivation film is etched back.
7) A plurality of column-shaped N-type doped regions 3 are formed on the back surface of the N-type semiconductor substrate 4.
As shown in fig. 10, the back substrate is thinned, the N-type column region doping window is photoetched, a sacrificial oxide layer is sputtered and grown on the back, phosphorus ions are implanted, then the sacrificial oxide layer on the back is etched, and then the laser annealing and propelling are carried out on the back to form the column-shaped N doping region 3.
8) Forming a P-type collector region 2 on the back of the cylindrical N-type doped region 3, as shown in fig. 11, performing back sputtering to grow a sacrificial oxide layer, implanting boron ions, then etching the back sacrificial oxide layer, and then performing back laser annealing to form the P-type collector region 2.
9) And forming a collector metal layer 1 on the back of the P-type collector region 2, sputtering a plurality of metal films on the back and alloying as shown in fig. 12, and finally performing testing, scribing, die cutting, lead bonding and packaging to finish the process.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.
Claims (10)
1. The utility model provides a promote IGBT structure of high temperature resistant and anti irradiation ability, includes active area cellular structure and non-active area terminal structure, its characterized in that, active area cellular structure includes: an N-type semiconductor substrate (4); a plurality of column-shaped N-type doped regions (3) formed on the back surface of the semiconductor substrate (4); the P-type collector region (2) is formed on the back surface of the columnar N-type doped region (3); a collector metal layer (1) formed on the back of the P-type collector region (2); an N-type CS layer (9) formed on the front surface of the semiconductor substrate (4); a P well layer (7) formed on the front surface of the N-type CS layer (9); a highly doped P + region (6) formed on the front surface of the P well layer (7); a plurality of trench gates formed in the highly doped P + region (6), wherein the bottoms of the trench gates are positioned in the semiconductor substrate (4); an N + emitting region (8) is arranged on the outer side of the front surface of the trench gate; a grid metal layer (13) is arranged on the surface of the trench gate; and an emitter metal layer (12) is arranged on the surfaces of the highly doped P + region (6) and the N + emitting region (8).
2. The IGBT structure for improving high temperature resistance and radiation resistance according to claim 1, characterized in that the doping concentration of the columnar N-type doped region (3) is greater than that of the N-type semiconductor substrate (4).
3. The IGBT structure capable of improving the high temperature resistance and the radiation resistance according to claim 2, characterized in that adjacent columnar N-type doped regions (3) are connected with each other or arranged at intervals.
4. The IGBT structure capable of improving high temperature resistance and radiation resistance according to claim 3, wherein the trench gate comprises polysilicon (10) filled in the trench and an oxide layer (11) for isolating the polysilicon (10) from the inner wall of the trench.
5. The IGBT structure for improving high temperature resistance and radiation resistance according to claim 4, wherein the non-active region termination structure comprises: the semiconductor device comprises an N-type semiconductor substrate (4), a plurality of P-type field limiting rings (5) formed on the front surface of the N-type semiconductor substrate (4), and a plurality of column-shaped N-type doped regions (3) formed on the back surface of the N-type semiconductor substrate (4); the P-type collector region (2) is formed on the back surface of the columnar N-type doped region (3); and the collector metal layer (1) is formed on the back surface of the P-type collector region (2).
6. The IGBT structure capable of improving high temperature resistance and radiation resistance according to claim 5, characterized in that adjacent columnar N-type doped regions (3) are connected with each other.
7. The IGBT structure capable of improving high temperature resistance and radiation resistance according to claim 5, is characterized in that adjacent P-type field limiting rings (5) are arranged at intervals.
8. A preparation method of an IGBT structure capable of improving high temperature resistance and radiation resistance is characterized by comprising the following steps:
providing an N-type semiconductor substrate (4); forming a plurality of column-shaped N-type doped regions (3) on the back surface of the N-type semiconductor substrate (4); forming a P-type collector region (2) on the back of the columnar N-type doped region (3); forming a collector metal layer (1) on the back of the P-type collector region (2);
manufacturing an active area cellular structure: forming an N-type CS layer (9) on the partial front surface of the N-type semiconductor substrate (4); forming a P well layer (7) on the front surface of the N-type CS layer (9); forming a highly doped P + region (6) on the front surface of the P well layer (7); forming a plurality of trench gates in the highly doped P + region (6), wherein the bottoms of the trench gates are positioned in the semiconductor substrate (4); forming an N + emitting region (8) at the outer side of the front surface of the trench gate; forming a gate metal layer (13) on the surface of the trench gate; forming an emitter metal layer (12) on the surfaces of the high-doped P + region (6) and the N + emitter region (8);
manufacturing a non-active area terminal structure: and forming a plurality of P-type field limiting rings (5) on the partial front surface of the N-type semiconductor substrate (4).
9. The preparation method of the IGBT structure for improving the high temperature resistance and the radiation resistance according to claim 8, characterized in that a plurality of column-shaped N-type doped regions (3) in the cell region of the active region are connected with each other or arranged at intervals; the plurality of columnar N-type doped regions (3) located in the non-active region termination region are connected with each other.
10. The method for preparing the IGBT structure capable of improving the high temperature resistance and the radiation resistance according to claim 8, wherein the columnar N-type doped region (3) is formed by means of ion implantation.
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| CN117038451A (en) * | 2023-10-09 | 2023-11-10 | 深圳市锐骏半导体股份有限公司 | Trench gate IGBT device, manufacturing method and simulation method |
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