CN117038451A - Trench gate IGBT device, manufacturing method and simulation method - Google Patents

Trench gate IGBT device, manufacturing method and simulation method Download PDF

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Publication number
CN117038451A
CN117038451A CN202311297249.9A CN202311297249A CN117038451A CN 117038451 A CN117038451 A CN 117038451A CN 202311297249 A CN202311297249 A CN 202311297249A CN 117038451 A CN117038451 A CN 117038451A
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ring
layer
terminal
simulation
region
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CN117038451B (en
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蔡远飞
黄泽军
江洪湖
匡迪
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SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
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SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
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    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

The embodiment of the invention discloses a trench gate IGBT device, a manufacturing method and a simulation method, wherein the manufacturing method comprises the steps of sequentially generating an N-RING cutoff RING and a G-RING compression RING in a terminal area; forming a CS layer in the active region; annealing and knot pushing are carried out; processing the terminal area to generate a LOCOS thick oxide layer, and continuously annealing and pushing the LOCOS thick oxide layer; generating a BODY well region for the terminal region; generating a gate oxide layer, and continuously annealing and pushing a junction; depositing and etching polysilicon; forming an N+ emitter on the active region, and activating by annealing; etching the contact hole on the deposited dielectric layer, and injecting P-type ions; depositing a metal layer and etching metal; depositing a passivation layer and etching the passivation layer; and forming a back FS layer and a back P-type collector on the back surface of the silicon substrate. By implementing the manufacturing method of the embodiment of the invention, the injection efficiency of the CS layer can be improved, the CSBT conduction voltage drop and saturation current are reduced, and the trade-off relation between the conduction voltage drop and the turn-off loss is optimized.

Description

Trench gate IGBT device, manufacturing method and simulation method
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a trench gate IGBT device, a manufacturing method and a simulation method.
Background
The IGBT (Insulated Gate Bipolar Transistor ) is a composite driving power semiconductor device composed of a BJT (bipolar junction transistor ) and a MOSFET (metal oxide semiconductor field effect transistor, metal Oxide Semiconductor Field Effect Transistor), has the characteristics of a MOSFET and a bipolar junction transistor, and has a good trade-off relationship between on-state current and switching loss. The IGBT has the advantages of high forward current density, low conduction voltage drop, simple driving circuit, good controllability, large safe working area and the like. When the IGBT is turned on in the forward direction, a large amount of unbalanced carriers are injected into the collector to form a conduction modulation effect, so that the conduction voltage drop is greatly reduced, and when the device is turned off, the excessive minority carriers in the voltage-resistant area can be extracted and disappeared only after a period of time is needed, so that the turn-off speed of the IGBT is slower, and the turn-off loss is higher. In order to further improve the compromise performance of the forward conduction voltage drop and the turn-off loss of the IGBT, an emitter carrier enhancement technology may be used, and an IGBT device with a CSL (with carrier storage layer, carrier Stored Layer) structure is used in the conventional carrier enhancement technology. There is also a method that a hole barrier is built on the upper part of the N-type epitaxial layer and is combined with a trench gate structure, and a structure is proposed that an N-type doped carrier storage layer is introduced between a P-type body region of the trench gate IGBT and the N-type epitaxial layer, wherein the doping concentration of the carrier storage layer is higher than that of the epitaxial layer, and the structure is named CSTBT (carrier storage layer trench bipolar transistor, carrier Stored Trench Gate Bipolar Transistor), which is a common structure applying carrier enhancement technology in the IGBT, and when the device is turned on in the forward direction, a N N + junction between the epitaxial layer and the carrier storage layer builds a diffusion potential to block the outflow of holes, so that holes are accumulated below the carrier storage layer. When the number of holes is larger than the number of electrons, the N-type epitaxial layer in the region cannot maintain a charge balance condition, in order to maintain charge balance, the emitter can inject more electrons to flow through an inversion layer channel in the P-type body region, so that the carrier injection rate of the emitter is improved, which is equivalent to locally increasing the carrier concentration at one side of the epitaxial layer close to the emitter, and reducing the conduction voltage drop of the device. The IGBT device adopting the carrier storage layer structure improves the injection efficiency of the emitter, and is equivalent to the reduction of the injection efficiency of the collector to obtain the same on-voltage drop, so that when the IGBT is turned off, the turn-off time can be greatly reduced and the turn-off loss can be reduced because the carrier efficiency of the injection of the collector is reduced.
The conduction voltage drop of the CSBT is reduced along with the increase of the doping concentration of the CS layer, and the CS layer in the prior art is usually implanted without a photomask after the etching step of thick oxygen is finished, so that the high-temperature long-time thermal process of the thick oxygen step cannot be effectively utilized, the advancing depth of the CS layer is often limited, and the conduction loss of a device, the performance of a safe working area and the like are greatly reduced.
Therefore, a new method is necessary to be designed, so that the injection efficiency of the CS layer is improved, the aims of reducing the conduction voltage drop and the saturation current of the CSBT are fulfilled, and the trade-off relation between the conduction voltage drop and the turn-off loss is optimized.
Disclosure of Invention
The invention aims to provide a trench gate IGBT device, a manufacturing method and a simulation method.
In order to solve the technical problems, the aim of the invention is realized by the following technical scheme: the manufacturing method of the trench gate IGBT device comprises the following steps:
sequentially generating an N-RING cutoff RING and a G-RING compression RING on the N-doped silicon substrate of the terminal area;
forming a CS layer in the active region by adopting a third photomask through N-type ion implantation;
carrying out main annealing pushing junction on the N-RING cut-off RING, the G-RING compression RING and the CS layer;
processing the terminal area to generate a LOCOS thick oxide layer, and continuously annealing and pushing the N-RING cutoff RING, the G-RING compression RING and the CS layer;
generating a BODY well region for the terminal region and the active region;
generating a gate oxide layer for the terminal area and the active area, and continuously annealing and pushing the N-RING cut-off RING, the G-RING compression RING and the CS layer;
depositing polysilicon on the terminal area and the active area, and etching the polysilicon;
forming an N+ emitter through N-type ion implantation on the active region, and activating by annealing;
depositing dielectric layers on the terminal area and the active area, etching the contact hole, injecting P-type ions into the contact hole, and activating by thermal annealing;
depositing a metal layer on the terminal and the active region, and etching metal to form an emitter metal and a gate metal;
depositing a passivation layer on the terminal and the active region, and etching the passivation layer to form a protection layer;
and grinding the back of the silicon substrate of the terminal and the active region, forming a back FS layer through N-type ion implantation, and forming a back P-type collector through P-type ion implantation.
The further technical scheme is as follows: the N-doped silicon substrate in the terminal area sequentially generates an N-RING cutoff RING and a G-RING compression RING, and the N-RING cutoff RING comprises the following components:
forming an N-RING cutoff RING on the N-doped silicon substrate of the terminal region by N-type ion implantation by using a first photomask;
and forming a G-RING voltage-resistant RING in the terminal area by P-type ion implantation by adopting a second photomask.
The further technical scheme is as follows: the main annealing and knot pushing of the N-RING cut-off RING, the G-RING compression RING and the CS layer comprises the following steps:
annealing and knot pushing are adopted for the N-RING cut-off RING, the G-RING compression RING and the CS layer at 1150-1200 ℃ for 180-400 min.
The further technical scheme is as follows: the pair of terminal areas generates a BODY well area, which comprises the following steps:
and removing the silicon nitride from the terminal region, and forming a BODY well region through P-type ion implantation.
The further technical scheme is as follows: the annealing and pushing junction of the N-RING cutoff RING, the G-RING compression RING and the CS layer continuously comprises the following steps:
and forming grooves on the surfaces of the terminal area and the active area by etching through a fifth photomask, and sequentially forming a sacrificial oxide layer and a gate oxide layer through thermal oxidation, wherein the grooves are used for continuously annealing and pushing the N-RING stop RING, the G-RING compression RING and the CS layer.
The further technical scheme is as follows: the pair of active regions form an N+ emitter through N-type ion implantation and are annealed and activated, and the method comprises the following steps:
and forming an N+ emitter by adopting a third photomask for the active region through N-type ion implantation, and annealing and activating.
In addition, the technical problem to be solved by the invention is to provide a trench gate IGBT device, which is characterized in that the trench gate IGBT device is manufactured by adopting the manufacturing method of the trench gate IGBT device, wherein the trench gate IGBT device comprises an active region and a terminal region, the terminal region surrounds the active region, the terminal region is provided with a terminal structure, the terminal structure comprises a terminal front structure, and the terminal front structure comprises a silicon substrate, an N-RING cut-off RING, a G-RING compression RING, a LOCOS thick oxide layer, a BODY well region, a gate oxide layer, a dielectric layer, a metal layer and a protective layer; the N-RING cutoff RING and the G-RING pressure-resistant RING are positioned on the same layer, and the silicon substrate is positioned on the lower layers of the N-RING cutoff RING and the G-RING pressure-resistant RING; a BODY well region is connected between two adjacent LOCOS thick oxide layers; the gate oxide layer, the dielectric layer, the metal layer and the protective layer are arranged above the LOCOS thick oxide layer from bottom to top; a contact hole is formed in the dielectric layer of the front structure of the terminal, and P-type impurities are filled in the contact hole; the active area is provided with an active structure, and the active structure comprises an active front structure; the active front structure comprises a silicon substrate, a CS layer, a BODY well region, a gate oxide layer, an N+ emitter, a dielectric layer, a metal layer and a protective layer which are sequentially arranged from bottom to top; a plurality of grooves are formed in the CS layer, the grooves penetrate through the CS layer, and the gate oxide layer of the BODY well region is arranged on the inner wall of the grooves and above the BODY well region; the BODY well region is arranged on the CS layer; polysilicon is filled in the groove; an N+ emitter is arranged on the BODY well region; the dielectric layer of the active front structure is provided with a contact hole, and the contact hole is filled with P-type impurities.
The further technical scheme is as follows: the terminal structure further comprises a terminal back structure, the terminal back structure comprises a back FS layer and a back P-type collector, and the active structure comprises an active back structure; the active backside structure includes a backside FS layer and a backside P-type collector.
In addition, the technical problem to be solved by the invention is to provide a simulation method of the trench gate IGBT device, which is characterized by comprising the following steps:
acquiring the terminal structure of the trench gate IGBT device and the manufacturing method of the trench gate IGBT device;
dividing the front structure of the terminal according to a preset dividing rule to obtain a plurality of dividing areas;
determining simulation codes corresponding to the manufacturing method of the trench gate IGBT device, and performing structural simulation on each divided area by utilizing the simulation codes and the area parameters of each divided area to generate a corresponding simulation module;
combining simulation modules corresponding to the divided areas according to the area positions of the divided areas to obtain a primary combined structure;
performing planar structure simulation according to the terminal back structure to obtain a back simulation module;
integrating the primary combined structure with the back simulation module to obtain an integrated simulation terminal structure;
optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure by adopting a historical experience method to obtain an adjusted integrated simulation terminal structure;
and performing simulation operation on the adjusted integrated simulation terminal structure according to a preset operation rule to obtain simulation electrical performance parameters of the integrated simulation terminal structure.
The further technical scheme is as follows: the method for optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure by adopting the historical experience method to obtain an adjusted integrated simulation terminal structure comprises the following steps:
and searching out the historical virtual grid density which is the closest to the structure of each simulation module according to the stored historical data, and optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure according to the historical virtual grid density to obtain an adjusted integrated simulation terminal structure.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, one NP photoetching is added before thick oxygen growth, the injection of a CS layer is predefined, the high-temperature thermal process in the whole flow is efficiently utilized, and the CS layer is comprehensively propelled, so that a more ideal depth and concentration distribution is obtained, the injection efficiency of the CS layer is remarkably improved, the aims of reducing the CSBT conduction voltage drop and saturation current are fulfilled, and the trade-off relation between the conduction voltage drop and the turn-off loss is optimized; the CS layer is selectively injected, so that N-type impurities cannot be doped into the P-type compression ring, and the voltage is more favorable for stabilizing the breakdown voltage; the number of layers of the photomask is not increased, and the production cost is reduced to the maximum extent.
The invention is further described below with reference to the drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a trench gate IGBT device according to an embodiment of the invention;
FIG. 2 is a schematic illustration of a termination region formed by N-type ion implantation to form an N-RING cutoff RING according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of an active region of an N-RING cutoff RING formed by N-type ion implantation in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a termination region for forming a G-RING voltage-resistant RING by P-type ion implantation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an active region of a G-RING voltage-resistant RING formed by P-type ion implantation according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a terminal area for forming a CS layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an active region for forming a CS layer according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a CS layer implant provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of a CS layer implant corresponding NP mask provided by an embodiment of the present invention;
fig. 10 is a schematic diagram of a termination region of an annealing push junction according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of an active region of an annealing push junction according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a termination region of etched silicon nitride according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of an etched silicon nitride active region according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a termination region of a thermally oxidized grown LOCOS thick oxygen layer according to an embodiment of the present invention;
FIG. 15 is a schematic view of an active region of a LOCOS thick oxygen layer grown by thermal oxidation according to an embodiment of the present invention;
FIG. 16 is a schematic diagram of a termination region for forming a BODY well region according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of an active region for forming a BODY well region according to an embodiment of the present invention;
fig. 18 is a schematic view of a termination region for forming a trench according to an embodiment of the present invention;
fig. 19 is a schematic view of an active area for forming a trench according to an embodiment of the present invention;
FIG. 20 is a schematic diagram of a termination region for forming a gate oxide layer by thermal oxidation according to an embodiment of the present invention;
FIG. 21 is a schematic diagram of an active region of a gate oxide formed by thermal oxidation according to an embodiment of the present invention;
FIG. 22 is a schematic illustration of a termination region for deposited polysilicon according to an embodiment of the present invention;
FIG. 23 is a schematic illustration of an active region of deposited polysilicon according to an embodiment of the present invention;
fig. 24 is a schematic diagram of a termination region of N-type ion implantation according to an embodiment of the present invention;
fig. 25 is a schematic diagram of an N-type ion implanted active region according to an embodiment of the present invention;
FIG. 26 is a schematic diagram of a termination region of a deposited dielectric layer according to an embodiment of the present invention;
FIG. 27 is a schematic illustration of an active region of a deposited dielectric layer according to an embodiment of the present invention;
FIG. 28 is a schematic view of a termination region of a deposited metal layer according to an embodiment of the present invention;
FIG. 29 is a schematic view of an active region of a deposited metal layer according to an embodiment of the present invention;
fig. 30 is a schematic diagram of a termination region formed after thinning to form a back FS layer and a back P-type collector according to an embodiment of the present invention;
fig. 31 is a schematic diagram of an active region of a back FS layer and a back P-type collector formed after thinning according to an embodiment of the present invention;
fig. 32 is a schematic diagram of a termination structure of a trench gate IGBT device according to an embodiment of the invention;
fig. 33 is a schematic diagram of an active structure of a trench gate IGBT device according to an embodiment of the invention;
fig. 34 is a flow chart of a simulation method of a trench gate IGBT device according to an embodiment of the invention;
the figure identifies the description:
1. a terminal structure; 2. an active structure; 10. a silicon substrate; 20. an N-RING cutoff RING; 30. G-RING pressure RING; 40. LOCOS thick oxide layer; 50. a BODY well region; 60. a contact hole; 70. a back FS layer; 80. a back P-type collector; 90. a dielectric layer; 100. a metal layer; 110. a CS layer; 120. polycrystalline silicon; 130. an n+ emitter; 140. and a gate oxide layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a trench gate IGBT device according to an embodiment of the present invention, in which, by adding NP lithography before thick oxygen growth, injection of a CS layer is predefined, high-temperature thermal process in the whole flow is efficiently utilized, and the CS layer is comprehensively propelled, so that a more ideal depth and concentration distribution is obtained, injection efficiency of the CS layer is significantly improved, and the purpose of reducing csbt conduction voltage drop and saturation current is achieved, and meanwhile, a trade-off relationship between conduction voltage drop and turn-off loss is also significantly optimized.
Referring to fig. 1, the method for fabricating a trench gate IGBT device includes steps S110 to S220.
S110, sequentially generating an N-RING cutoff RING and a G-RING compression RING on the N-doped silicon substrate of the terminal area.
In this embodiment, referring to fig. 2 and 3, a first mask is used to form an N-RING stop RING on an N-doped silicon substrate in the termination region by N-type ion implantation.
Referring to fig. 4 and 5, a second mask is used to form a G-RING halo by P-ion implantation on the N-doped silicon substrate in the termination region.
S120, forming a CS layer in the active region by adopting a third photomask through N-type ion implantation.
In this embodiment, please refer to fig. 6-9, wherein fig. 8 is a sectional view AA of fig. 9; the selective injection CS layer is a carrier storage layer, only the active region is injected, the terminal region is not injected, the P-type voltage-resistant ring is not doped with N-type impurities, and the method is more beneficial to stabilizing breakdown voltage.
S130, carrying out main annealing push junction on the N-RING cut-off RING, the G-RING compression RING and the CS layer.
In this embodiment, the step S130 may include: annealing and knot pushing are adopted for the N-RING cut-off RING, the G-RING compression RING and the CS layer at 1150-1200 ℃ for 180-400 min.
Referring to fig. 10 to 11, one NP lithography is added before the thick oxygen growth, the injection of the CS layer is predefined, the high-temperature thermal process in the whole process is efficiently utilized, and the CS layer is comprehensively propelled, so that a more ideal depth and concentration distribution is obtained, the injection efficiency of the CS layer is significantly improved, the purpose of reducing the csbt conduction voltage drop and the saturation current is achieved, and meanwhile, the trade-off relationship between the conduction voltage drop and the turn-off loss is significantly optimized.
S140, processing the terminal area to generate a LOCOS thick oxide layer, and continuing annealing and pushing the N-RING cut-off RING, the G-RING compression RING and the CS layer.
In this embodiment, referring to fig. 12 to 15, silicon nitride is deposited on the termination region and the active region, and the fourth mask is used to etch the silicon nitride on the termination region to expose the LOCOS window, and the LOCOS thick oxide layer (12K a to 20K a) is grown by thermal oxidation in the LOCOS window, so that the step S130 is still to continue to push the junction when this step is performed.
S150, generating a BODY well region for the terminal region and the active region;
in this embodiment, referring to fig. 16 to 17, silicon nitride is removed from the termination region, and a BODY well region is formed by P-type ion implantation.
And S160, generating a gate oxide layer for the terminal area and the active area, and continuously annealing and pushing the N-RING cut-off RING, the G-RING compression RING and the CS layer.
In this embodiment, referring to fig. 20 to 21, trenches are formed in the terminal region and the active region by etching the surface of the silicon substrate using a fifth photomask, and a sacrificial oxide layer and a gate oxide layer are sequentially formed by thermal oxidation, so that the N-RING stop RING, the G-RING compression RING and the CS layer are continuously annealed and pushed, and the step S130 is still performed continuously when the step is performed.
S170, depositing polycrystalline silicon on the terminal area and the active area, and etching the polycrystalline silicon.
In this embodiment, referring to fig. 22 to 23, polysilicon is deposited for the termination region and the active region, and a sixth mask is provided to etch the polysilicon.
S180, forming an N+ emitter on the active region through N-type ion implantation, and activating by annealing.
In this embodiment, referring to fig. 24 to 25, an n+ emitter is formed by N-type ion implantation using a third mask for the active region, and is activated by annealing.
The number of layers of the mask is not increased, which is equivalent to using one NP mask, namely the third mask, twice (CS layer injection and NP injection), thereby reducing the production cost to the greatest extent.
And S190, depositing dielectric layers on the terminal area and the active area, etching the contact hole, injecting P-type ions into the contact hole, and activating by thermal annealing.
In this embodiment, referring to fig. 26 to 27, dielectric layers are deposited on the termination region and the active region, eighth mask etching contact holes are provided, P-type ions are implanted into the contact holes, and activation is performed by rapid thermal annealing.
And S200, depositing a metal layer on the terminal and the active region, and etching metal to form an emitter metal and a gate metal.
In this embodiment, referring to fig. 28 to 29, a metal layer is deposited on the terminal and the active region, and a ninth mask etching metal is provided to form an emitter metal and a gate metal.
And S210, depositing a passivation layer on the terminal and the active region, and etching the passivation layer to form a protection layer.
In this embodiment, a passivation layer is deposited on the terminal and the active region, and a tenth mask is provided to etch the passivation layer to form a protective layer.
And S220, grinding the back of the silicon substrate of the terminal and the active region, forming a back FS layer through N-type ion implantation, and forming a back P-type collector through P-type ion implantation.
In this embodiment, referring to fig. 30 to 31, the back surface of the silicon substrate of the terminal and the active region is ground and thinned, a back FS layer is formed by N-type ion implantation, and a back P-type collector is formed by P-type ion implantation.
According to the manufacturing method of the trench gate IGBT device, the injection of the CS layer is predefined by adding one NP photoetching before thick oxygen growth, the high-temperature thermal process in the whole flow is efficiently utilized, and the CS layer is comprehensively propelled, so that a relatively ideal depth and concentration distribution is obtained, and the junction depth of CS is at least 2-5 um larger than the junction depth of the BODY well region of the active region by taking 1200V trench FS IGBT as an example, and the concentration is between e15 and e 17. The injection efficiency of the CS layer is obviously improved, the aim of reducing the CSBT conduction voltage drop and the saturation current is fulfilled, and the trade-off relation between the conduction voltage drop and the turn-off loss is optimized; the CS layer is selectively injected, so that N-type impurities cannot be doped into the P-type compression ring, and the voltage is more favorable for stabilizing the breakdown voltage; the number of layers of the photomask is not increased, and the production cost is reduced to the maximum extent.
In an embodiment, referring to fig. 32 to 33, a trench gate IGBT device is further provided, and the trench gate IGBT device is manufactured by the method for manufacturing a trench gate IGBT device described above, where the trench gate IGBT device includes an active region and a termination region, the termination region surrounds the active region, the termination region is provided with a termination structure 1, the termination structure 1 includes a termination front structure, and the termination front structure includes a silicon substrate 10, an N-RING stop RING 20, a G-RING voltage-resistant RING 30, a LOCOS thick oxide layer 40, a BODY well region 50, a gate oxide layer 140, a dielectric layer 90, a metal layer 100, and a protection layer; wherein the N-RING cutoff RING 20 and the G-RING pressure RING 30 are positioned on the same layer, and the silicon substrate 10 is positioned on the lower layer of the N-RING cutoff RING 20 and the G-RING pressure RING 30; a BODY well region 50 is connected between two adjacent LOCOS thick oxide layers 40; the gate oxide layer 140, the dielectric layer 90, the metal layer 100 and the protective layer are arranged above the LOCOS thick oxide layer 40 from bottom to top; a contact hole 60 is arranged on the dielectric layer 90 of the front structure of the terminal, and P-type impurities are filled in the contact hole 60; the active area is provided with an active structure 2, and the active structure 2 comprises an active front structure; the active front structure comprises a silicon substrate 10, a CS layer 110, a BODY well region 50, a gate oxide layer 140, an N+ emitter, a dielectric layer 90, a metal layer 100 and a protective layer which are sequentially arranged from bottom to top; a plurality of grooves are formed in the CS layer 110, the grooves penetrate through the CS layer 110, and the gate oxide layer 140 of the BODY well region 50 is arranged on the inner wall of the grooves and above the BODY well region 50; the BODY well region 50 is disposed on the CS layer 110; the trench is filled with polysilicon 120; an N+ emitter 130 is arranged on the BODY well region 50; the dielectric layer 90 of the active front structure is provided with a contact hole 60, and the contact hole 60 is filled with P-type impurities.
In this embodiment, the reference junction depth of the N-RING cutoff RING 20 is 9-15 um; the reference junction depth of the G-RING pressure-resistant RING 30 is 7-10 um; the LOCOS thick oxide layer 40 has a reference thickness of 1.3-2.0 um; the reference junction depth of the BODY well region 50 is 2.3-3.8 um; the reference thickness of the gate oxide layer 140 is 1000-2500 Å; the reference thickness of the dielectric layer 90 is 0.8-1.2 um; the reference thickness of the metal layer 100 is 4.0-6.0 um; the reference thickness of the protective layer is 1.0-1.5 um; the reference junction depth of the CS layer 110 is 6-10 um; the reference junction depth of the N+ emitter is 0.23-0.35 um; the reference depth of the groove is 5-7 um.
In one embodiment, referring to fig. 32 and 33, the terminal structure 1 further includes a terminal back structure, the terminal back structure includes a back FS layer 70 and a back P-type collector 80, and the active structure 2 includes an active back structure; the active backside structure includes a backside FS layer 70 and a backside P-type collector 80.
The reference junction depth of the back P-type collector 80 is 0.18-0.3 um; the reference junction depth of the back FS layer 70 is 2-5 um, a phosphorus implantation process.
In the trench gate IGBT device of the embodiment, the CS layer 110 is not arranged in the terminal area, and the CS layer 110 is arranged in the active area, so that N-type impurities are not doped into the P-type voltage-resistant ring, and the breakdown voltage is more favorably stabilized; the number of layers of the photomask is not increased, and the production cost is reduced to the maximum extent; and the CSBT conduction voltage drop and saturation current of the trench gate IGBT device can be reduced, and the trade-off relation between the conduction voltage drop and the turn-off loss is optimized.
In an embodiment, referring to fig. 34, a simulation method of a trench gate IGBT device is further provided, specifically, a terminal structure of the trench gate IGBT device is simulated to verify whether an electrical performance parameter of the trench gate IGBT device meets a design requirement, where the electrical performance parameter includes electrical parameter information such as breakdown voltage, breakdown electric field distribution, and the like, and a tester can determine whether a power device terminal meets the design requirement by simulating the electrical performance parameter; the simulation method of the trench gate IGBT device comprises steps S310-S380.
S310, acquiring information corresponding to the terminal structure of the trench gate IGBT device and information corresponding to the manufacturing method of the trench gate IGBT device.
In this embodiment, the acquiring terminal structure entity includes information such as a size parameter, a unit structure type, a unit structure shape, and a unit structure coordinate; the manufacturing method of the trench gate IGBT device comprises the technological process and production technological parameters.
S320, dividing the front structure of the terminal according to a preset dividing rule to obtain a plurality of dividing areas.
In this embodiment, the front structure of the terminal includes an N-RING cutoff RING, a G-RING pressure RING; the unit structure corresponding to the type of the N-RING cut-off RING does not contain a subunit structure, and the N-RING cut-off RING is determined to be a basic unit; the G-RING pressure RINGs all comprise subunit structures, and the subunit results are determined to be basic units, for example, the unit structures corresponding to the G-RING pressure RINGs respectively comprise four G-RING subunit structures, and each G-RING subunit structure can be correspondingly determined to be a basic unit respectively;
in the dividing rule, the unit structure is further divided according to the sub-unit structures included in the unit structures corresponding to the respective types, for example, the contact points of the adjacent unit structures are determined as dividing points, and the dividing planes corresponding to the dividing points are generated along the first cutting direction, so that the dividing regions corresponding to the respective basic units are obtained by dividing, that is, each basic unit corresponds to one dividing region. That is, the front structure of the current terminal can be divided into a dividing region formed by an N-RING cutoff RING and four dividing regions respectively formed by G-RING subunit structures; determining the virtual grid point number of each basic unit according to the three-dimensional basic grid and the unit coordinate position of each basic unit in the terminal information to be simulated; when the number of the virtual grid points of each basic unit is larger than a point threshold value in the segmentation rule; and re-dividing the dividing region corresponding to the basic unit according to the mode of symmetrical dividing of the middle axis in the dividing rule, and finally determining the dividing region.
Specifically, the virtual grid point number of each basic unit in the three-dimensional basic network can be determined according to the unit coordinate position of each basic unit, and the virtual grid point number is the number of grid points occupied by the basic unit in the three-dimensional basic network. For example, if the basic grid size is 2 micrometers, each grid point is a cube of 2 micrometers×2 micrometers, whether the basic unit fills a certain grid point can be determined according to the unit coordinate position of the basic unit (or whether the filling ratio of the basic unit to the grid point is greater than a preset ratio, for example, the preset ratio is set to be 60%), and if the basic unit fills a certain grid point, the grid point can be counted; and obtaining the counting result of each basic unit to obtain the virtual grid point number of each basic unit.
S330, determining simulation codes corresponding to the manufacturing method of the trench gate IGBT device, and performing structural simulation on each divided area by using the simulation codes and the area parameters of each divided area to generate a corresponding simulation module.
In this embodiment, corresponding parameters are set according to a trench gate IGBT device manufacturing method in a process flow editing module (dimension) of sentaurrus, and region parameters of a divided region are set, where the region parameters of the divided region include size parameters, unit structure shapes, and parameter information corresponding to the divided region in unit structure coordinates; and generating simulation codes, and running the simulation codes of all the divided areas in Sprocess, so that structural simulation is realized and a simulation module is generated. For basic units divided by the G-RING withstand voltage RING in the trench gate IGBT device, only one basic unit can be selected for structural simulation, so that system resources occupied in the structural simulation process are greatly reduced, namely the system operation pressure is reduced, and the efficiency of generating a simulation module is greatly improved; the system resources comprise CPU occupation, processing thread occupation, memory occupation, GPU occupation, video memory occupation and the like of the computer terminal or the server.
S340, combining simulation modules corresponding to the division areas according to the area positions of the division areas to obtain a primary combined structure.
And combining the positions of the segmented areas by adopting corresponding positions in the trench gate IGBT device to form a primary combined structure.
S350, carrying out planar structure simulation according to the terminal back structure to obtain a back simulation module.
Planar structure simulation was performed for the back side structure. And establishing a one-dimensional model with the thickness corresponding to the primary combined structure, carrying out planar structure simulation based on the back structure, and carrying out process simulation such as back FS layer injection, P collector injection and the like according to a trench gate IGBT device manufacturing method, thereby obtaining a back simulation module.
And S360, integrating the primary combined structure with the back simulation module to obtain an integrated simulation terminal structure.
Horizontally segmenting the primary combined structure, and taking the segmented upper structure to obtain a front segmentation structure; meanwhile, horizontally segmenting the back simulation module, and taking the segmented lower layer structure to obtain a back segmentation structure; and integrating the front segmentation structure and the back segmentation structure in the vertical direction to form an integrated simulation terminal structure. The splitting height for horizontally splitting the primary combined structure can be half of the thickness of the primary combined structure, and the splitting height for horizontally splitting the back simulation module can also be half of the thickness of the primary combined structure. Because the back simulation module is a one-dimensional model, specific details of the front segmentation structure can be emphasized through segmentation and integration operation, and meanwhile, system resources can be saved through the back segmentation structure, so that the consumption of the system resources is further reduced.
The segmentation height H for horizontally segmenting the primary combined structure is calculated through a segmentation calculation formula 1 And a dicing height H for horizontally dicing the back surface simulation module 2 . The height ratio of the initial combined structure and the back simulation module for horizontal segmentation is automatically adjusted through the total number of virtual grid points of the initial combined structure, so that the integrated simulation terminal structure obtained by integration can further embody the reduction of the terminal operation pressure.
Wherein the segmentation height H is calculated by a segmentation calculation formula 2 The expression can be expressed by the formula (1): （1）；
wherein Dz is the total point number of the virtual grid contained in the primary combined structure, D 0 For the point threshold in the segmentation rule, e is the natural logarithmic base, H 0 To the thickness of the preliminary combined structure, cut the height H 1 = H 0 -H 2 。
For example, dz=45 ten thousand, D 0 =10ten thousand, H 0 =50 μm, then the calculated slice height H corresponds to 2 At 27.67 microns (height from the bottom of the back simulation module to the horizontal split point), split height H 1 22.33 microns (height from top of the preliminary combined structure to the horizontal split point).
And S370, optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure by adopting a historical experience method to obtain an adjusted integrated simulation terminal structure.
In this embodiment, the historical virtual grid density which is the closest to the structure of each simulation module is found according to the stored historical data, and the virtual grid density of each simulation module in the integrated simulation terminal structure is optimized and adjusted according to the historical virtual grid density, so as to obtain the adjusted integrated simulation terminal structure.
The historical data comprises different integrated simulation terminal structures, structures of corresponding simulation modules and virtual network densities, the historical data is formed by extracting corresponding data through a previous simulation process and storing the corresponding data into a database, in the embodiment, the historical data is utilized to adjust the virtual grid density of each simulation module in the integrated simulation terminal structure to be the most similar historical virtual grid density with the structure of each simulation module, and then fine adjustment is carried out through an expert experience method, for example, fine adjustment is carried out on some important simulation modules, so that the purpose of the important simulation modules in the integrated simulation terminal structure is highlighted.
And S380, performing simulation operation on the adjusted integrated simulation terminal structure according to a preset operation rule to obtain simulation electrical performance parameters of the integrated simulation terminal structure.
In this embodiment, the electrode types and the simulation running codes matched in the running rule can be obtained according to the integrated simulation terminal structure; the operation rule includes a plurality of sets of electrode mapping information, and each set of electrode mapping information includes electrode types corresponding to one or more boundary conditions. Specifically, a group of mapping relations matched with the boundary conditions in the operation rule are respectively determined according to the initial boundary conditions of each simulation module in the integrated simulation terminal structure, and the electrode types in the matched mapping relations are obtained and determined as the electrode types matched with the simulation modules. For example, the boundary condition is gate (gate) or emitter (emitter), and the electrode type in the corresponding set of mapping relations is ohmic contact electrode (voltage=0); the boundary condition is collector (collector), and the electrode type corresponding to one group of mapping relation is electrode (resistance=1e5 to 1e13) with large external resistance; the boundary condition is a metal field plate, and the electrode type in the corresponding group of mapping relations is a common floating electrode (charge=0); the boundary condition is a cut-off ring metal field plate (the electrode is usually shorted to the silicon surface), and the electrode type in the corresponding set of mapping relations is a special floating electrode, i.e. a zero current boundary condition (voltage=0, current=0). Of course, the design of the terminal structure is various, and the above initial boundary conditions are only one, and eventually, appropriate adjustment may be given according to the actual structure.
And acquiring a simulation operation code corresponding to the substrate parameter in the terminal information to be simulated in the operation rule, and executing the simulation operation code to perform simulation operation on the adjusted integrated simulation terminal structure, so as to acquire the simulation electrical performance parameter of the integrated simulation terminal structure. The simulation electrical performance parameters comprise electrical parameter information such as breakdown voltage, breakdown electric field distribution and the like, and a tester can judge whether the power device terminal meets the design requirement through simulating the electrical performance parameters. Because the simulation verification does not need to carry out actual production on the power device terminal, the cost for testing the power device terminal can be greatly saved, and the testing efficiency is improved.
After determining the manufacturing method of the trench gate IGBT device and determining the structure of the trench gate IGBT device, simulation is performed, the simulation method of the embodiment can improve the high reliability of the simulation result, and a designer can verify the manufacturing method of the trench gate IGBT device of the embodiment through the method to achieve the corresponding purpose.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (10)

1. The manufacturing method of the trench gate IGBT device is characterized by comprising the following steps of:
sequentially generating an N-RING cutoff RING and a G-RING compression RING on the N-doped silicon substrate of the terminal area;
forming a CS layer in the active region by adopting a third photomask through N-type ion implantation;
carrying out main annealing pushing junction on the N-RING cut-off RING, the G-RING compression RING and the CS layer;
processing the terminal area to generate a LOCOS thick oxide layer, and continuously annealing and pushing the N-RING cutoff RING, the G-RING compression RING and the CS layer;
generating a BODY well region for the terminal region and the active region;
generating a gate oxide layer for the terminal area and the active area, and continuously annealing and pushing the N-RING cut-off RING, the G-RING compression RING and the CS layer;
depositing polysilicon on the terminal area and the active area, and etching the polysilicon;
forming an N+ emitter through N-type ion implantation on the active region, and activating by annealing;
depositing dielectric layers on the terminal area and the active area, etching the contact hole, injecting P-type ions into the contact hole, and activating by thermal annealing;
depositing a metal layer on the terminal and the active region, and etching metal to form an emitter metal and a gate metal;
depositing a passivation layer on the terminal and the active region, and etching the passivation layer to form a protection layer;
and grinding the back of the silicon substrate of the terminal and the active region, forming a back FS layer through N-type ion implantation, and forming a back P-type collector through P-type ion implantation.
2. The method for fabricating the trench gate IGBT device of claim 1 wherein the sequentially generating an N-RING stop RING and a G-RING withstand RING on the N-doped silicon substrate in the termination region comprises:
forming an N-RING cutoff RING on the N-doped silicon substrate of the terminal region by N-type ion implantation by using a first photomask;
and forming a G-RING voltage-resistant RING in the terminal area by P-type ion implantation by adopting a second photomask.
3. The method for manufacturing the trench gate IGBT device of claim 1, wherein the main annealing and junction pushing the N-RING cutoff RING, the G-RING withstand voltage RING, and the CS layer comprises:
annealing and knot pushing are adopted for the N-RING cut-off RING, the G-RING compression RING and the CS layer at 1150-1200 ℃ for 180-400 min.
4. The method for fabricating a trench gate IGBT device of claim 1 wherein the pair of termination regions generate a BODY well region comprising:
and removing the silicon nitride from the terminal region, and forming a BODY well region through P-type ion implantation.
5. The method for fabricating a trench gate IGBT device of claim 1 wherein the forming a gate oxide layer for the termination region and the active region and continuing the annealing push junction of the N-RING stop RING, the G-RING withstand voltage RING, and the CS layer comprises:
and forming grooves on the surfaces of the terminal area and the active area by etching through a fifth photomask, and sequentially forming a sacrificial oxide layer and a gate oxide layer through thermal oxidation, wherein the grooves are used for continuously annealing and pushing the N-RING stop RING, the G-RING compression RING and the CS layer.
6. The method for fabricating the trench gate IGBT device of claim 1 wherein the forming an n+ emitter by N-type ion implantation and annealing activation of the pair of active regions comprises:
and forming an N+ emitter by adopting a third photomask for the active region through N-type ion implantation, and annealing and activating.
7. A trench gate IGBT device manufactured by the trench gate IGBT device manufacturing method according to any one of claims 1 to 6, wherein the trench gate IGBT device comprises an active region and a termination region, the termination region surrounds the active region, the termination region is provided with a termination structure, the termination structure comprises a termination front structure, and the termination front structure comprises a silicon substrate, an N-RING stop RING, a G-RING withstand voltage RING, a LOCOS thick oxide layer, a BODY well region, a gate oxide layer, a dielectric layer, a metal layer, and a protective layer; the N-RING cutoff RING and the G-RING pressure-resistant RING are positioned on the same layer, and the silicon substrate is positioned on the lower layers of the N-RING cutoff RING and the G-RING pressure-resistant RING; a BODY well region is connected between two adjacent LOCOS thick oxide layers; the gate oxide layer, the dielectric layer, the metal layer and the protective layer are arranged above the LOCOS thick oxide layer from bottom to top; a contact hole is formed in the dielectric layer of the front structure of the terminal, and P-type impurities are filled in the contact hole; the active area is provided with an active structure, and the active structure comprises an active front structure; the active region front structure comprises a silicon substrate, a CS layer, a BODY well region, a gate oxide layer, an N+ emitter, a dielectric layer, a metal layer and a protective layer which are sequentially arranged from bottom to top; a plurality of grooves are formed in the CS layer, the grooves penetrate through the CS layer, and the gate oxide layer of the BODY well region is arranged on the inner wall of the grooves and above the BODY well region; the BODY well region is arranged on the CS layer; polysilicon is filled in the groove; an N+ emitter is arranged on the BODY well region; the dielectric layer of the active front structure is provided with a contact hole, and the contact hole is filled with P-type impurities.
8. The trench gate IGBT device of claim 7 wherein the termination structure further comprises a termination back structure comprising a back FS layer and a back P-type collector, the active structure comprising an active back structure; the active backside structure includes a backside FS layer and a backside P-type collector.
9. The simulation method of the trench gate IGBT device is characterized by comprising the following steps of:
acquiring information corresponding to a terminal structure of the trench gate IGBT device according to claim 8, and information corresponding to a method for manufacturing the trench gate IGBT device according to any one of claims 1 to 6;
dividing the front structure of the terminal according to a preset dividing rule to obtain a plurality of dividing areas;
determining simulation codes corresponding to the manufacturing method of the trench gate IGBT device, and performing structural simulation on each divided area by utilizing the simulation codes and the area parameters of each divided area to generate a corresponding simulation module;
combining simulation modules corresponding to the divided areas according to the area positions of the divided areas to obtain a primary combined structure;
performing planar structure simulation according to the terminal back structure to obtain a back simulation module;
integrating the primary combined structure with the back simulation module to obtain an integrated simulation terminal structure;
optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure by adopting a historical experience method to obtain an adjusted integrated simulation terminal structure;
and performing simulation operation on the adjusted integrated simulation terminal structure according to a preset operation rule to obtain simulation electrical performance parameters of the integrated simulation terminal structure.
10. The method for simulating the trench gate IGBT device according to claim 9, wherein the optimizing the adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure by using the historical experience method, to obtain the adjusted integrated simulation terminal structure, includes:
and searching out the historical virtual grid density which is the closest to the structure of each simulation module according to the stored historical data, and optimizing and adjusting the virtual grid density of each simulation module in the integrated simulation terminal structure according to the historical virtual grid density to obtain an adjusted integrated simulation terminal structure.
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