CN111540677A - Manufacturing process of three-layer step-shaped groove transistor - Google Patents
Manufacturing process of three-layer step-shaped groove transistor Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
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- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 18
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- 230000008021 deposition Effects 0.000 claims description 3
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- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000002243 precursor Substances 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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Abstract
The invention discloses a manufacturing process of a three-layer ladder-shaped groove transistor, which comprises the following steps: etching a first groove on a silicon wafer substrate; placing the silicon wafer substrate in an oxidation furnace tube for oxidation operation, and generating a silicon oxide protective layer on the inner side wall of the first groove; depositing a silicon nitride film layer on the silicon oxide protective layer of the first groove by a chemical vapor deposition process; using fluorine-containing gas to perform plasma treatment to form a sidewall; then, continuously etching the Si layer of the silicon wafer substrate downwards at the bottom of the first groove to form a second groove; with O2And (3) removing the silicon nitride film layer at the bottom of the first groove by using a plasma process to form a double-groove structure. The multi-groove design structure obtains larger transistor area in the same packaging volume, so that the static current passing and high voltage bearing capacity of the multi-groove structure are increased, and the maximized effective transistor area can be increased by 2-4 times.
Description
Technical Field
The invention belongs to the technical field of wafer production, and particularly relates to a manufacturing process of a three-layer stepped groove transistor.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry has also decreased (i.e., the smallest device or interconnect line that can be fabricated using a fabrication process). Improvements in IC performance have been achieved primarily by the ever shrinking dimensions of integrated circuit devices to increase their speed. This scaled down process has the advantage of improving production efficiency and reducing associated costs. At the same time, this scaling down process also increases the complexity of handling and manufacturing the ICs.
At present, in the manufacturing process of the MOSFET and IGBT element, the transistor is required to be grooved, and in the current process, only a single shallow groove is etched. As shown in fig. 1, for a single-trench transistor produced in the prior art, when the size of the transistor device is fixed, the effective area of the trench of the single-trench transistor is determined by the process (in the current MOSFET andIGBT device manufacturing method, the effective area that can be achieved is already limited), which results in a limited number of shallow trenches that can be etched on the surface of a unit volume, and a limited effective contact area of the walls of the formed single trench, which limits the static current passing through the single trench and the ability to carry high voltage, thereby making the overall performance of the transistor worse.
Meanwhile, the size of the effective transistor area is critical, and a single shallow trench can only have fixed and limited electronic characteristics.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a manufacturing process of a three-layer step-shaped trench transistor, which solves the technical problem that the power-on capacity and the high-voltage bearing capacity of a single-trench transistor in the prior art are limited.
The purpose of the invention can be realized by the following technical scheme:
a manufacturing process of a three-layer step-shaped groove transistor comprises the following steps:
s1, selecting a silicon wafer substrate, etching a first groove on the silicon wafer substrate to form a primary processing transistor, and cleaning to remove impurities on the side wall of the first groove;
s2, placing the preliminary processed transistor in an oxidation furnace tube for oxidation operation,so as to form a thickness of
A silicon oxide protective layer of (a);
s3, depositing a silicon nitride film on the silicon oxide protective layer of the first trench by plasma-activated chemical vapor deposition or low-pressure chemical vapor deposition;
s4, using fluorine-containing gas to perform plasma treatment, and providing a bias voltage potential to use the formed silicon nitride film layer as a side wall and stop etching on the silicon oxide protective layer;
s5, taking the silicon nitride film layer etched on the side wall of the first groove as a hard mask, and then continuously etching the Si layer of the silicon wafer substrate at the bottom of the first groove by a dry etching process to form a second groove;
s5.1, completely etching the silicon nitride thin film layer remained on the first groove through phosphoric acid liquid for the transistor etched with the second groove, and cleaning to remove impurities on the side wall of the second groove;
s6, placing the transistor in an oxidation furnace tube at 900-1050 deg.C to perform oxidation operation so as to form a thickness of the inner sidewall of the second trench
A silicon oxide protective layer of (a);
s7, uniformly covering the silicon oxide protective layer of the second groove by a chemical vapor deposition method to form an organic silicon isolation layer;
s8, using fluorine-containing gas to perform plasma treatment, and providing a bias voltage potential to form an organic silicon isolation layer as a side wall and stop etching on the silicon oxide protection layer;
s9, taking the organic silicon isolation layer etched on the side wall of the second groove as a hard mask, then continuously etching the Si layer of the silicon wafer substrate at the bottom of the second groove by a dry etching process to form a third groove, and cleaning and removing impurities on the side wall of the third groove to obtain the three-layer step-shaped groove transistor.
Further, the temperature of the oxidation operation in the oxidation furnace tube adopted in the S2 is 900-1050 ℃.
Further, the etching ratio of the silicon nitride thin film layer to the silicon oxide protective layer in S3 is greater than 10: 1.
Further, the plasma-enhanced chemical vapor deposition process employed in S3 is performed by using SiH at a temperature of 400-800 ℃2Cl2+NH3A deposition operation is performed for the raw material.
Further, in S6, an organic silicon isolation layer is uniformly formed on the silicon oxide protection layer of the first trench by using a chemical vapor deposition method using an organic precursor.
Furthermore, after the groove is formed each time, cleaning is performed to remove impurities, and then the next operation is performed.
Further, after the step S4 and before the step S5, the silicon oxide protection layer at the bottom end of the first trench between the silicon nitride thin film layers is removed by hydrofluoric acid.
Further, after the step S8 and before the step S9, the silicon oxide protection layer at the bottom end of the second trench between the silicon nitride thin film layers is removed by hydrofluoric acid.
Further, after completing the S9, the following steps are performed:
s10, removing the silicon oxide protective layer and the residual organic silicon isolation layer on the first trench and the second trench by hydrofluoric acid, and placing the transistor in an oxidation furnace tube at 1050 ℃ and 900 ℃ for oxidation operation again so as to uniformly cover the first trench, the second trench and the third trench with a thickness of
The silicon oxide protective layer.
Further, after completing the S10, the following steps are performed:
s11, doping the first trench, the second trench and the third trench with polysilicon of phosphorus or arsenic, so that the first trench, the second trench and the third trench are completely filled with polysilicon;
and S12, performing CMP or full etching process on the excessive polysilicon outside the first groove to completely remove the excessive polysilicon so as to flatten the polysilicon outside the first groove, thereby obtaining the formed transistor with three layers of stepped grooves.
The invention has the beneficial effects that:
according to the method, silicon nitride and polymers are used as an isolation edge layer (Spacer) combination according to the sequence to carry out three-step ladder-shaped groove process, and the three-groove design structure obtains a larger transistor area in the same packaging volume, so that the static current of the three grooves passes through and the high-voltage bearing capacity is increased, the overall performance of the transistor is greatly improved, and the maximized effective transistor area can be improved by 2-4 times.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional single trench transistor structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the forming structure of step S1 according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of the forming structure of step S2 according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of the forming structure of step S3 according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of the forming structure of step S4 according to the embodiment of the present invention;
FIG. 6 is a schematic view of the S4.1 step forming structure of the embodiment of the present invention;
FIG. 7 is a schematic diagram of the forming structure of step S5 according to the embodiment of the present invention;
FIG. 8 is a schematic view of the S5.1 step forming structure of the embodiment of the present invention;
FIG. 9 is a schematic view of the forming structure of step S6 according to the embodiment of the present invention;
FIG. 10 is a schematic view of the forming structure of step S7 according to the embodiment of the present invention;
FIG. 11 is a schematic view of the forming structure of step S8 according to the embodiment of the present invention;
FIG. 12 is a schematic view of the S8.1 step forming structure of the embodiment of the present invention;
FIG. 13 is a schematic view of the forming structure of step S9 according to the embodiment of the present invention;
FIG. 14 is a structural diagram of step S10 according to the embodiment of the present invention;
FIG. 15 is a schematic view of the forming structure of step S10 according to the embodiment of the present invention;
FIG. 16 is a schematic view of the forming structure of step S11 according to the embodiment of the present invention;
fig. 17 is a schematic diagram of the forming structure of step S12 according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment provides a process method for generating a double-groove transistor by using a silicon nitride isolation layer, which comprises the following steps:
s1, as shown in fig. 2, selecting a silicon wafer substrate, etching a first trench 11 on the silicon wafer substrate to form a transistor 1, and cleaning to remove impurities on the sidewall of the first trench 11.
S2, as shown in FIG. 3, the preliminary processed transistor 1 is placed in an oxidation furnace tube at a temperature of 900-1050 ℃ to perform an oxidation operation, so as to form a thickness of the inner sidewall of the first trench 11
While the silicon oxide protective layer 101 is also formed over the first trench 11.
S3, as shown in FIG. 4, using Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD), such as PECVD, with SiH at 800 ℃ and 400-2Cl2+NH3The deposition operation is carried out on the raw materials, and the formation mechanism is as follows:
3SiH2Cl2+4NH3→Si3N4+6HCl+6H2
then, uniformly covering a silicon nitride film layer 102 (i.e. a silicon nitride isolation layer) on the silicon oxide protection layer 101, wherein the etching ratio of the silicon nitride film layer 102 to the silicon oxide protection layer 101 is greater than 10:1, so as to achieve the purpose of
S4, as shown in FIG. 5, the plasma treatment is performed by using the fluorine-containing gas, and the bias potential is applied to form the silicon nitride thin film layer 102 as the sidewall, at which time the etching of the silicon wafer substrate upper layer is stopped on the silicon oxide protection layer 101.
S4.1, as shown in FIG. 6, the silicon oxide protection layer 101 at the bottom end of the first trench 11 between the silicon nitride thin film layers 102 is removed by hydrofluoric acid.
S5, as shown in fig. 7, the silicon nitride film layer 102 etched on the sidewall of the first trench 11 is used as a hard mask (hardmark), and then the Si layer of the silicon wafer substrate is continuously etched (etch) at the bottom of the first trench 11 by a dry etching process to form a second trench 12.
S5.1, as shown in fig. 8, the transistor 1 etched with the second trench 12 is completely etched on the silicon nitride thin film layer 102 remaining on the first trench 11 by using the phosphoric acid solution, and the impurities on the sidewall of the second trench 12 are removed by cleaning.
S6, as shown in FIG. 9, the transistor 1 is placed in an oxidation furnace at 1050 ℃ and 900 ℃ to perform an oxidation operation, so as to form a thickness of the second trench on the inner sidewall
The silicon oxide protective layer 101.
S7, as shown in fig. 10, the organic silicon thin film layer 103 is uniformly formed on the silicon oxide protection layer 101 of the second trench 12 by a chemical vapor deposition method using an organic precursor or a spin-on-polymer method, and at this time, the organic silicon thin film layer 103 is formed and simultaneously the organic silicon thin film layer 103 is present on the inner side wall of the first trench 11.
S8, as shown in FIG. 11, the plasma treatment is performed by using the fluorine-containing gas, and the bias potential is applied to form the nitrogen-containing organosilicon thin film layer 103 as a sidewall, at which time the etching of the silicon substrate upper layer is stopped on the silicon oxide protection layer 101 of the second trench 12.
S8.1, removing the silicon oxide protection layer 101 at the bottom end of the second trench 12 between the silicon nitride thin film layers 103 by hydrofluoric acid as shown in FIG. 12.
S9, as shown in fig. 13, using the organic silicon isolation layer 103 etched on the sidewall of the second trench 12 as a hard mask, then continuing to etch the Si layer of the silicon substrate at the bottom of the second trench 12 by a dry etching process to form a third trench 13, and cleaning and removing the impurities on the sidewall of the third trench 13 to obtain a three-layer step-shaped trench transistor.
S10, as shown in FIG. 14, the silicon oxide protection layer 101 and the residual organic silicon isolation layer 103 on the first trench 11 and the second trench 12 are removed by hydrofluoric acid, as shown in FIG. 15, the transistor 1 is again placed in an oxidation furnace at a temperature of 900-
The silicon oxide protective layer 101.
S11, as shown in fig. 16, the first trench 11, the second trench 12, and the third trench 13 are doped with polysilicon 104 of phosphorus or arsenic so that the polysilicon 104 completely fills the first trench 11, the second trench 12, and the third trench 13.
S12, as shown in fig. 17, the excess polysilicon 104 outside the first trench 11 is completely removed by CMP or full etching process, so as to planarize the polysilicon 104 outside the first trench 11, thereby obtaining a formed transistor with three layers of stepped trenches.
To sum up, this application uses silicon nitride and polymer as isolation boundary layer (Spacer) combination according to the preface, carries out three-step ladder trench technology, and three groove design structure gain bigger transistor area at same encapsulation volume for the quiescent current of three grooves passes through and bears the weight of high voltage ability and all can increase, thereby makes the bulk property of transistor material obtain great the improvement, and the effectual transistor area of its maximization can promote 2-4 times.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (10)
1. A manufacturing process of a three-layer step-shaped groove transistor is characterized by comprising the following steps:
s1, selecting a silicon wafer substrate, etching a first groove (11) on the silicon wafer substrate to form a primary processing transistor (1), and cleaning and removing impurities on the side wall of the first groove (11);
s2, placing the preliminary processed transistor (1) in an oxidation furnace tube to carry out oxidation operation so as to generate the thickness of the inner side wall of the first groove (11) to be
A silicon oxide protective layer (101);
s3, depositing a silicon nitride film layer (102) on the silicon oxide passivation layer (101) of the first trench (11) by plasma-enhanced chemical vapor deposition (PECVD) process or low pressure CVD;
s4, using fluorine-containing gas to perform plasma treatment, and providing a bias voltage potential to use the formed silicon nitride film layer (102) as a side wall and stop etching on the silicon oxide protective layer (101);
s5, taking the silicon nitride film layer (102) etched from the side wall of the first groove (11) as a hard mask, and then continuing to etch the Si layer of the silicon wafer substrate at the bottom of the first groove (11) by a dry etching process to form a second groove (12);
s5.1, completely etching the silicon nitride thin film layer (102) remained on the first groove (11) through phosphoric acid liquid for the transistor (1) etched with the second groove (12), and cleaning to remove impurities on the side wall of the second groove (12);
s6, placing the transistor (1) in an oxidation furnace tube at the temperature of 900-1050 ℃ to perform oxidation operation so as to form a thickness of the inner side wall of the second trench
A silicon oxide protective layer (101);
s7, uniformly covering and forming an organic silicon isolation layer (103) on the silicon oxide protection layer (101) of the second groove (12) by a chemical vapor deposition method;
s8, using fluorine-containing gas to perform plasma treatment, and providing a bias voltage potential, using the formed organic silicon isolation layer (103) as a side wall, and stopping etching on the silicon oxide protection layer (101);
s9, taking the organic silicon isolation layer (103) etched on the side wall of the second groove (12) as a hard mask, then continuing to etch the Si layer of the silicon wafer substrate at the bottom of the second groove (12) by a dry etching process to form a third groove (13), and cleaning and removing impurities on the side wall of the third groove (13) to obtain the three-layer step-shaped groove transistor.
2. The manufacturing process of a three-layer stepped trench transistor as claimed in claim 1, wherein the temperature of the oxidation operation in the oxidation furnace tube adopted in S2 is 900-1050 ℃.
3. The manufacturing process of the three-layer stepped trench transistor according to claim 1, wherein an etching ratio of the silicon nitride thin film layer (102) to the silicon oxide protective layer (101) in S3 is greater than 10: 1.
4. The manufacturing process of the three-layer stepped trench transistor as claimed in claim 1, wherein the plasma-enhanced chemical vapor deposition process employed in S3 is performed with SiH at a temperature of 400-800 ℃2Cl2+NH3A deposition operation is performed for the raw material.
5. The manufacturing process of a three-layer stepped trench transistor according to claim 1, wherein in S7, an organic precursor is used to uniformly cover and form an organosilicon isolation layer (102) on the silicon oxide protection layer (101) of the first trench (11) by a chemical vapor deposition method.
6. The process of manufacturing a three-layer stepped trench transistor as claimed in claim 1, wherein after each trench formation, a cleaning process is performed to remove impurities before the next step.
7. The process of manufacturing a three-layer stepped trench transistor according to claim 1,
after the step S4 and before the step S5, the silicon oxide protection layer (101) at the bottom end of the first trench (11) between the silicon nitride thin film layers (102) is removed by hydrofluoric acid.
8. The process of manufacturing a three-layer stepped trench transistor according to claim 1,
after the step S8 and before the step S9, the silicon oxide protection layer (101) at the bottom end of the second trench (12) between the silicon nitride thin film layers (103) is removed by hydrofluoric acid.
9. The manufacturing process of a three-layer stepped trench transistor according to claim 1, wherein after completion of the step S9, the following steps are performed:
s10, removing the silicon oxide protective layer (101) and the residual organic silicon isolation layer (103) on the first trench (11) and the second trench (12) by hydrofluoric acid, and then placing the transistor (1) in an oxidation furnace tube at a temperature of 900-
The silicon oxide protective layer (101).
10. The manufacturing process of a three-layer stepped trench transistor according to claim 9, wherein after completion of S10, the following steps are performed:
s11, doping the first trench (11), the second trench (12) and the third trench (13) with polysilicon (104) containing phosphorus or arsenic, so that the polysilicon (104) completely fills the first trench (11), the second trench (12) and the third trench (13);
s12, the excessive polysilicon (104) outside the first trench (11) is completely removed by applying CMP or full etching process so as to flatten the polysilicon (104) outside the first trench (11), and the formed transistor with three layers of stepped trenches is obtained.
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| CN202010470438.1A CN111540677B (en) | 2020-05-28 | 2020-05-28 | Manufacturing process of three-layer step-shaped groove transistor |
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