CN111403487B - Semiconductor device integrating MOSFET and diode and manufacturing method thereof - Google Patents

Semiconductor device integrating MOSFET and diode and manufacturing method thereof Download PDF

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Publication number
CN111403487B
CN111403487B CN202010378707.1A CN202010378707A CN111403487B CN 111403487 B CN111403487 B CN 111403487B CN 202010378707 A CN202010378707 A CN 202010378707A CN 111403487 B CN111403487 B CN 111403487B
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region
doped region
contact
gate
source
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CN111403487A (en
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郑亚良
李浩南
陈伟钿
周永昌
张永杰
孙倩
黎沛涛
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Alpha Power Solutions Ltd
Versitech Ltd
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Alpha Power Solutions Ltd
Versitech Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor device integrating a MOSFET and a diode and a manufacturing method thereof. The MOSFET comprises a first well region, a first source region, a first gate oxide layer and a first gate electrode, the diode comprises a second well region, a second source region, a second gate oxide layer and a second gate electrode, the semiconductor device further comprises a heavily doped region, a first contact region, a second contact region, a first modulation doped region, a second modulation doped region, a source metal region and a drain metal region, the first gate electrode is electrically isolated from the second gate electrode, the source metal region is electrically connected with the second gate electrode, and the heavily doped region is respectively contacted with the first gate oxide layer and the second gate oxide layer. By the above mode, the electric field intensity of the first gate oxide layer and the second gate oxide layer in the reverse voltage can be greatly reduced, so that the reliability of the semiconductor device is improved, and meanwhile, the conduction voltage drop of the diode can be reduced to reduce the power loss.

Description

Semiconductor device integrating MOSFET and diode and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device integrated with a MOSFET and a diode and a method for manufacturing the same.
Background
The body diode of the traditional silicon carbide power MOSFET (metal oxide semiconductor field effect transistor) has higher conduction voltage drop and higher power loss, and the power MOSFET integrated with the channel diode can greatly reduce the conduction voltage drop by making a gate oxide layer of the thin channel diode, thereby effectively reducing the power loss.
However, in carrying out the invention, the inventors have found that the prior art suffers from at least the following drawbacks: the gate oxide layer of the channel diode in the existing power MOSFET integrated with the channel diode is thinner, the gate oxide layer bears a very high electric field when in reverse voltage, the risk of damaging the device exists, and the reliability of the device is greatly affected.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device integrating a MOSFET and a diode and a manufacturing method thereof, which are used for solving the problem of reliability of a MOSFET gate oxide layer integrating a channel diode in the prior art.
The embodiment of the invention provides the following technical scheme for solving the technical problems:
in a first aspect, an embodiment of the present invention provides a semiconductor device integrating a MOSFET and a diode, including a semiconductor layer including a first face and a second face opposite to the first face, the MOSFET including: a first well region extending from the first face in a first direction; a first source region located within the first well region and extending from the first face in the first direction; a first gate oxide layer in contact with the first well region; a first gate electrode in contact with the first gate oxide layer; the diode includes: a second well region extending from the first surface in a first direction; a second source region located within the second well region and extending from the first face in the first direction; a second gate oxide layer in contact with the second well region; a second gate electrode in contact with the second gate oxide layer; the semiconductor device further includes: the heavily doped region is contacted with the first gate oxide layer and the second gate oxide layer; a trench extending from the first face to the heavily doped region along the first direction, wherein the first gate oxide layer, the first gate electrode, the second gate oxide layer and the second gate electrode are all located in the trench, and the trench comprises a first trench wall and a second trench wall; a first contact region located within the first well region, in contact with the first source region and extending from the first face in the first direction; a second contact region located within the second well region, in contact with the second source region and extending from the first face in the first direction; the first modulation doped region is positioned on the heavily doped region and is in contact with the first well region; the second modulation doped region is positioned on the heavily doped region and is in contact with the second well region; a source metal region in low resistance contact with the first source region, the second source region, the first contact region and the second contact region, and in contact with the second gate to achieve electrical connection; a metal leakage area positioned below the second surface and in low-resistance contact with the second surface; the first gate is electrically isolated from the second gate, the first source region, the second source region, the first modulation doped region and the second modulation doped region have a first conductivity type, the first well region, the second well region, the first contact region, the second contact region and the heavily doped region have a second conductivity type opposite to the first conductivity type, and the first direction is a direction perpendicular to the first face or the second face and from the first face to the second face.
Optionally, the first gate oxide layer between the first gate and the first trench wall is in a range of 40nm to 60nm, and the second gate oxide layer between the second gate and the second trench wall is in a range of 5nm to 30 nm.
Optionally, a lateral contact width of the second gate and the source metal region is in a range of 0.2um to 2.0 um.
Optionally, the heavily doped region has a lateral width in the range of 1.5um to 3.0um and a depth in the range of 0.3um to 1.0 um.
Optionally, the depth of the trench is in the range of 1.3um to 2.5 um.
Optionally, a lateral contact width of the heavily doped region and the first modulation doped region is in a range of 0 to 0.3um, and a lateral contact width of the heavily doped region and the second modulation doped region is in a range of 0 to 0.3 um.
Optionally, the widths of the first contact region and the second contact region are in the range of 0.5 to 2.0um, and the depths are in the range of 0.3 to 0.5 um.
Optionally, the semiconductor layer comprises a semiconductor material comprising one or more of silicon carbide, silicon, gallium nitride, or any other wide bandgap semiconductor material.
Optionally, the source metal region is in low resistance contact with the heavily doped region.
Optionally, the method further comprises: the third modulation doped region is contacted with the first modulation doped region and the heavy doped region; and the fourth modulation doped region is contacted with the second modulation doped region and the heavy doped region.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device integrating a MOSFET and a diode, including: providing a substrate; epitaxially growing a drift layer on a surface of the substrate; forming a heavily doped region on the surface of the drift layer; epitaxially growing a modulation doped region on the surface after the formation of the heavily doped region; forming a well region on the surface of the modulation doped region; forming a source region, a first contact region and a second contact region in the well region; etching a groove, wherein the groove divides the source region into a first source region and a second source region, divides the well region into a first well region and a second well region, and divides the modulation doping region into a first modulation doping region and a second modulation doping region; forming a first gate oxide layer, a first gate electrode, a second gate oxide layer and a second gate electrode in the groove; etching an opening above the second gate; depositing metal to form a source metal region so that the source metal region is in contact with the second grid electrode through the opening; depositing metal on the bottom surface of the substrate to form a metal leakage region; the heavily doped region is respectively contacted with the first gate oxide layer and the second gate oxide layer, the substrate, the drift layer, the source region and the modulation doped region have a first conductivity type, and the well region, the first contact region, the second contact region and the heavily doped region have a second conductivity type opposite to the first conductivity type.
Optionally, a heavily doped region is formed on the surface of the drift layer, and a third modulation doped region and a fourth modulation doped region are also formed.
Optionally, the forming a heavily doped region on the surface of the drift layer includes: patterning the surface of the drift layer to expose a first window corresponding to the heavily doped region; and performing ion implantation on the first window to form the heavily doped region.
Optionally, the forming a well region on the surface of the modulation doped region includes: epitaxially growing the well region on a surface of the modulation doped region; or, performing ion implantation on the surface of the modulation doped region to form the well region.
Optionally, the forming a source region, a first contact region and a second contact region in the well region includes: patterning the surface of the well region to form a second window corresponding to the source region/the first contact region and the second contact region; ion implantation is carried out on the second window to form the source region/the first contact region and the second contact region; patterning the surfaces after forming the source region/the first contact region and the second contact region to expose third windows corresponding to the first contact region and the second contact region/the source region; ion implantation is performed in the third window to form the first contact region and the second contact region/the source region.
Optionally, the etching the trench includes: patterning the surfaces of the source region, the first contact region and the second contact region to expose a fourth window corresponding to the trench; etching the groove through the fourth window; wherein the trench extends from a portion of the surface of the source region toward the substrate to the heavily doped region.
Optionally, forming a first gate oxide layer, a first gate electrode, a second gate oxide layer, and a second gate electrode in the trench includes: forming an oxide layer on the surface of the groove to form an oxide layer; depositing first polysilicon in the trench; etching the first polysilicon to form the second gate; after the second grid electrode is formed, continuing oxidation to form a first grid oxide layer and an electrical isolation layer; depositing a second polysilicon in the trench to form the first gate; generating oxide on the surface of the first grid electrode to form a dielectric layer; the second gate oxide layer is formed by the oxide layer, and the first gate and the second gate are electrically isolated through the electrical isolation layer.
Optionally, the etching an opening above the second gate includes: patterning the surface of the dielectric layer to expose a fifth window corresponding to the opening; and etching the opening through the fifth window.
Optionally, forming a heavily doped region on the surface of the drift layer further forms a third modulation doped region and a fourth modulation doped region, including: epitaxially growing a modulation doped region on the surface of the drift layer; patterning the surface of the modulation doped region to expose a sixth window corresponding to the heavily doped region; ion implantation is carried out on the sixth window to form the heavily doped region; wherein the third modulation doped region and the fourth modulation doped region are formed simultaneously with the formation of the heavily doped region.
Optionally, forming a heavily doped region on the surface of the drift layer further forms a third modulation doped region and a fourth modulation doped region, including: performing ion implantation on the surface of the drift layer to form a modulation doped region; patterning the surface of the modulation doped region to expose a seventh window corresponding to the heavily doped region; performing a first ion implantation in the seventh window to form the heavily doped region; wherein the third modulation doped region and the fourth modulation doped region are formed simultaneously with the formation of the heavily doped region.
The embodiment of the invention has the beneficial effects that: a semiconductor device integrating a MOSFET and a diode and a method of manufacturing the same are provided. The MOSFET comprises a first well region, a first source region, a first gate oxide layer and a first gate electrode, the diode comprises a second well region, a second source region, a second gate oxide layer and a second gate electrode, the semiconductor device further comprises a heavily doped region, a first contact region, a second contact region, a first modulation doped region, a second modulation doped region, a source metal region and a drain metal region, the first gate electrode is electrically isolated from the second gate electrode, the source metal region is electrically connected with the second gate electrode, and the heavily doped region is respectively contacted with the first gate oxide layer and the second gate oxide layer. By the above mode, the electric field intensity of the first gate oxide layer and the second gate oxide layer in the reverse voltage can be greatly reduced, so that the reliability of the semiconductor device is improved, and meanwhile, the conduction voltage drop of the diode can be reduced to reduce the power loss.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic structural diagram of a semiconductor device integrated with a MOSFET and a diode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a semiconductor device integrated with a MOSFET and a diode according to another embodiment of the present invention;
FIG. 3 is a schematic diagram showing a structure of other parts of a semiconductor device integrated with a MOSFET and a diode according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of providing a substrate and forming a drift layer according to an embodiment of the present invention;
FIG. 5 is a schematic illustration of forming heavily doped regions according to an embodiment of the present invention;
FIG. 6 is a schematic illustration of forming a modulated doped region in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of forming a well region according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of forming a source region, a first contact region and a second contact region according to an embodiment of the present invention;
FIG. 9 is a schematic illustration of forming a trench in accordance with an embodiment of the present invention;
fig. 10 to 15 are schematic diagrams illustrating formation of a first gate oxide, a first gate, a second gate oxide, and a second gate according to an embodiment of the present invention;
FIG. 16 is a schematic illustration of an embodiment of the present invention forming an opening;
FIG. 17 is a schematic illustration of forming a source metal region in accordance with an embodiment of the present invention;
FIG. 18 is a schematic illustration of forming a drain metal region according to an embodiment of the present invention;
fig. 19 to 20 are schematic views of forming a third modulation doped region and a fourth modulation doped region according to another embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It will be appreciated by those skilled in the art that embodiments of the invention will be described herein with reference to various cross-sectional and other schematic illustrations that are exemplary illustrations of idealized embodiments of the invention. Variations in the illustrated shapes, due to manufacturing techniques and/or tolerances, are to be expected. Embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing such as implant regions that are illustrated as being rectangular having generally rounded or curved features and/or implant concentration gradients at their edges. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. For the various layers and regions, embodiments of the present invention are described with reference to specific polarity conductivity types, however, as will be appreciated by those skilled in the art, the conductivity types of the layers and regions may be reversed to provide devices or arrangements of opposite conductivity types.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention. For illustrative purposes only, in this particular embodiment, the semiconductor device is a MOSFET integrated with a channel diode. Those skilled in the art will appreciate that the inventive concepts may be applied to other types of semiconductor devices. Those skilled in the art will also appreciate that in actual fabrication, the produced chip may include multiple MOSFETs or multiple channel diodes thereon, which are typically repeated in unit cells. Fig. 1 illustrates only some of the core elements of a MOSFET cell that integrates a channel diode.
As shown in fig. 1, the semiconductor device 100 integrating the MOSFET and the diode includes a semiconductor layer 110, the semiconductor layer 110 includes a first face 110a and a second face 110b opposite to the first face 110a, the MOSFET includes a first well region 52, a first source region 62, a first gate oxide 82 and a first gate 84, the first well region 52 extends from the first face 110a along a first direction defined as a direction perpendicular to the first face 110a or the second face 110b and from the first face 110a toward the second face 110b, the first source region 62 is located within the first well region 52 and extends from the first face 110a along the first direction, the first gate oxide 82 is in contact with the first well region 52, and the first gate 84 is in contact with the first gate oxide 82.
The diode includes a second well region 54, a second source region 64, a second gate oxide 92, and a second gate 94, the second well region 54 extending in a first direction from a first side 110a, the second source region 64 being located within the second well region 54 and extending in the first direction from the first side 110a, the second gate oxide 92 being in contact with the second well region 54, the second gate 94 being in contact with the second gate oxide 92.
The semiconductor device 100 further includes a heavily doped region 30, a trench 120, a first contact region 72, a second contact region 74, a first modulation doped region 42, a second modulation doped region 44, a source metal region 150, and a drain metal region 160, wherein the heavily doped region 30 is in contact with the first gate oxide 82 and the second gate oxide 92, the trench 120 extends from the first side 110a to the heavily doped region 30 along a first direction, the first gate oxide 82, the first gate 84, the second gate oxide 92, and the second gate 94 are all located in the trench 120, the trench 120 includes a first trench wall 120a and a second trench wall 120b, the first contact region 72 is located in the first well region 52, is in contact with the first source region 62 and extends from the first side 110a along the first direction, second contact region 74 is located within second well region 54, contacts second source region 64 and extends in the first direction from first side 110a, first modulated doping region 42 is located on heavily doped region 30 and contacts first well region 52, second modulated doping region 44 is located on heavily doped region 30 and contacts second well region 54, source metal region 150 is in low resistance contact (e.g., ohmic contact) with first source region 62, second source region 64, first contact region 72 and second contact region 74, source metal region 150 is also in contact with second gate 94 to make electrical connection, and drain metal region 160 is located under second side 110b and in low resistance contact (e.g., ohmic contact) with second side 110 b.
Wherein the first gate 84 is electrically isolated from the second gate 94 by an electrical isolation layer 134, the first source region 62, the second source region 64, the first modulation doped region 42, and the second modulation doped region 44 have a first conductivity type, and the first well region 52, the second well region 54, the first contact region 72, the second contact region 74, and the heavily doped region 30 have a second conductivity type opposite to the first conductivity type.
The first conductivity type may be N-type, P-type, or N-type, and the second conductivity type may be P-type, opposite to the second conductivity type, for example, when the first conductivity type is N-type, the second conductivity type is P-type, or when the first conductivity type is P-type, the second conductivity type is N-type. For convenience of description below regarding the first conductivity type and the second conductivity type, the first conductivity type is described by taking N type as an example, and the second conductivity type is described by taking P type as an example.
In this embodiment, the source metal region 150 is electrically connected to the second gate 94, and when a positive voltage is applied to the source metal region 150, the channel of the diode is opened, which is represented by a diode characteristic. By the mode, the conduction voltage drop of the diode can be reduced to be less than 1.5V or 1.5V, so that the defect of high conduction voltage drop of the body diode of the traditional silicon carbide power MOSFET is effectively overcome, and the power loss can be further reduced.
The heavily doped region 30 contacting the first gate oxide 82 and the second gate oxide 92 can reduce parasitic capacitance between the gate and the drain, which is beneficial to improving performance of the semiconductor device 100, and meanwhile, the presence of the heavily doped region 30 can reduce the influence of reverse voltage on the first gate oxide 82 and the second gate oxide 92, so as to avoid performance degradation or even failure of the semiconductor device 100.
Furthermore, the first and second modulation doped regions 42 and 44 having the first conductivity type (N-type) can greatly enhance the current capability of the MOSFET and the diode, thereby enhancing the performance of the semiconductor device 100.
In some embodiments, semiconductor layer 110 is made of a semiconductor material including one or more of silicon carbide (SiC), silicon (Si), gallium nitride (GaN), or any other wide bandgap semiconductor material. The silicon is a narrow bandgap semiconductor material, the bandgap is less than 2.3eV, the silicon carbide and gallium nitride are wide bandgap semiconductor materials, the bandgap is more than 2.3eV, any other wide bandgap semiconductor material may be aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium oxide (Ga 2O 3), etc., the semiconductor layer 110 may be made of silicon, any of the above wide bandgap semiconductor materials, and it should be understood by those skilled in the art that, along with the rapid development of semiconductor technology, the semiconductor material for making the semiconductor layer 110 may not be limited by the embodiment of the present invention.
In some embodiments, the semiconductor device 100 further includes a substrate 10 and a drift layer 20 on the substrate 10, the drift layer 20 being in contact with a surface of the substrate 10. Both the substrate 10 and the drift layer 20 have a first conductivity type (N-type), and the drift layer 20 may be obtained by depositing an epitaxial layer of N-type silicon carbide on the substrate 10. In some other embodiments, the base 10 is a 4-H silicon carbide substrate having a first conductivity type (N-type).
In the present embodiment, the drift layer 20 having the first conductivity type (N-type) is in contact with the heavily doped region 30 having the second conductivity type (P-type), and since the heavily doped region 30 forms a PN junction with the drift layer 20, the influence of the reverse voltage on the first gate oxide 82 and the second gate oxide 92 can be reduced by utilizing this characteristic, and the performance degradation or even the damage failure of the semiconductor device 100 can be avoided.
In some embodiments, the thickness Tox of the first gate oxide 82 between the first gate 84 and the first trench wall 120a is in the range of 40nm to 60nm, and the thickness Td of the second gate oxide 92 between the second gate 94 and the second trench wall 120b is in the range of 5nm to 30 nm.
It is contemplated that the thickness of the oxide layer at the contact with heavily doped region 30 may vary due to the different oxidation rates of the crystal planes.
As described above, due to the P-type heavily doped region 30, the electric field of the first gate oxide layer 82 and the second gate oxide layer 92 at the reverse voltage can be reduced, the reliability of the semiconductor device 100 can be greatly improved, the silicon dioxide layer can be ensured to be in the range allowing the intensity of the electric field to be borne, and the on-voltage drop of the diode can be further reduced by reducing the thickness of the second gate oxide layer 92, thereby being beneficial to reducing the power loss.
In some embodiments, the heavily doped region 30 has a lateral width a1 in the range of 1.5um to 3.0um and a depth d1 in the range of 0.3um to 1.0 um.
In the present embodiment, "lateral" is defined as a direction parallel to the paper surface of fig. 1 and perpendicular to the first direction, and "depth" is defined as a depth in a direction parallel to the first direction. The following description relating to "lateral" and "depth" also refers to this definition.
In some embodiments, the doping concentrations of the first and second modulation doped regions 42 and 44 are 8E15cm -3 To 1E17cm -3 The depth d2 of the first modulation doped region 42 is in the range of 0.5um to 2.0um, and the depth of the second modulation doped region 44 may be the same as or different from d 2.
In some embodiments, the depth d3 of the first well region 52 is in the range of 0.8um to 1.5um, the depth of the second well region 54 is in the range of 0.8um to 1.5um, and the depth of the second well region 54 may be the same as d3 or different.
In some embodiments, the lateral width a2 of the first contact region 72 is in the range of 0.5um to 2.0um, the depth d4 is in the range of 0.3um to 0.5um, the lateral width of the second contact region 74 is in the range of 0.5um to 2.0um, the depth is in the range of 0.3um to 0.5um, the lateral width of the second contact region 74 may be the same as or different from a2, and the depth of the second contact region 74 may be the same as or different from d 4.
In some embodiments, the lateral width a3 of the trench 120 is in the range of 1.5um to 3.0um, and the depth d5 is in the range of 1.3um to 2.5 um.
In some embodiments, the lateral contact width a4 of the heavily doped region 30 and the first modulation doped region 42 is in the range of 0 to 0.3um, the lateral contact width of the heavily doped region 30 and the second modulation doped region 44 is in the range of 0 to 0.3um, and the lateral contact width of the second modulation doped region 44 may be the same as a4 or different.
In some embodiments, the lateral contact width a5 of the second gate 94 and the source metal region 150 is in the range of 0.2um to 2.0 um.
In some embodiments, as shown in fig. 2, the semiconductor device 100 further includes a third modulation doped region 172 and a fourth modulation doped region 174, the third modulation doped region 172 is in contact with the first modulation doped region 42 and the heavily doped region 30, and the fourth modulation doped region 174 is in contact with the second modulation doped region 44 and the heavily doped region 30. The doping concentrations of the third modulation doped region 172 and the fourth modulation doped region 174 may be the same as or different from those of the first modulation doped region 42 and the second modulation doped region 44.
In the present embodiment, the third and fourth modulation doped regions 172 and 174 having the first conductivity type (N-type) can further improve the current capability of the MOSFET and the diode, thereby improving the performance of the semiconductor device 100.
In some embodiments, as shown in fig. 3, source metal region 150 is in low resistance contact (e.g., ohmic contact) with heavily doped region 30.
The embodiment of the invention also provides a manufacturing method of the semiconductor device for manufacturing the integrated MOSFET and the diode, and the manufacturing method is shown in fig. 4 to 20.
As shown in fig. 4, a substrate 10 is provided and a drift layer 20 is epitaxially grown on the surface of the substrate 10 using a suitable process, which may be vapor phase epitaxy. In fig. 4, the drift layer 20 is shown as only one layer, and it will be understood by those skilled in the art that the drift layer 20 may include two or more layers, such as one or more buffer layers, epitaxial layers, and combinations thereof, as may be desired to improve the flexibility of semiconductor device design and device performance.
As shown in fig. 5, a heavily doped region 30 is formed on the surface of the drift layer 20. The method comprises the following steps: the surface of the drift layer 20 is patterned to expose a window corresponding to the heavily doped region 30, and ion implantation is performed in the window to form the heavily doped region 30, wherein the ions may be P-type doping elements such as aluminum, boron, etc. In this particular embodiment, the weight The doping concentration of the doped region 30 is 5E18cm -3 To 1E20cm -3 Within a range of (2).
As shown in fig. 6, a modulation doped region 40 is epitaxially grown on the surface after the heavily doped region 30 is formed.
As shown in fig. 7, a well region 50 is formed on the surface of the modulation doped region 40. The method comprises the following steps: epitaxially growing a well region 50 on the surface of the modulated doping region 40 at an epitaxial growth concentration of 5E16cm -3 To 2E17cm -3 Within a range of (2). Ion implantation can also be directly performed on the surface of the modulation doped region 40 to form a well region 50, wherein the ion implantation concentration is 1E11cm -3 To 1E13cm -3 In the range of 30keV to 700keV, the ions are doping elements having the second conductivity type, such as P-type doping elements of aluminum, boron, etc.
As shown in fig. 8, a source region 60, a first contact region 72, and a second contact region 74 are formed within well region 50. The method comprises the following steps: the surface of well region 50 is patterned to form a second window corresponding to source region 60/first contact region 72 and second contact region 72, ion implantation is performed in the second window to form source region 60/first contact region 72 and second contact region 74, the surface after forming source region 60/first contact region 72 and second contact region 74 is patterned to expose a third window corresponding to first contact region 72 and second contact region 74/source region 60, and ion implantation is performed in the third window to form first contact region 72 and second contact region 74/source region 60.
In this embodiment, the source region 60 may be formed before the first contact region 72 and the second contact region 74 are formed, or may be formed after the first contact region 72 and the second contact region 74 are formed. Ion implantation concentration corresponding to formation of source region 60 is 1E14cm -3 To 3E15cm -3 In the range of 40keV to 400keV, the implanted ions are doping elements having the first conductivity type (N-type), such as nitrogen, phosphorus, arsenic, etc. Ion implantation concentration corresponding to formation of the first contact region 72 and the second contact region 74 is 1E14cm -3 To 3E15cm -3 In the range of 40keV to 800keV, the implanted ions are doping elements with the second conductivity type (P type), such as aluminumBoron, and the like.
In some embodiments, the lateral width a6 of the source region 60 is in the range of 3.0um to 6.0um and the depth is in the range of 0.3um to 0.5 um. The depth of the source region 60 may be the same as or different from the depth of the first contact region 72 and the second contact region 74.
As shown in fig. 9, a trench 120 is etched. The method comprises the following steps: the surfaces after forming source region 60, first contact region 72, and second contact region 74 are patterned to expose a fourth window corresponding to trench 120, and trench 120 is etched through the fourth window, wherein trench 120 extends from a portion of the surface of source region 60 toward substrate 10 or the first direction to heavily doped region 30. The groove 120 includes a first groove wall 120a and a second groove wall 120b.
Trench 120 divides source region 60 into first source region 62 and second source region 64, well region 50 into first well region 52 and second well region 54, and modulation doped region 40 into first modulation doped region 42 and second modulation doped region 44, wherein first well region 52, first source region 62, and first modulation doped region 42 are proximate first trench wall 120a, and second well region 54, second source region 64, and second modulation doped region 44 are proximate second trench wall 120b.
As shown in fig. 10 to 15, a first gate oxide 82, a first gate 84, a second gate oxide 92, and a second gate 94 are formed in the trench 120. The method comprises the following steps: oxide is grown on the surface after forming the trench 120 to form the oxide layer 132, thereby forming the second gate oxide layer 92, the formation may be oxidation, polysilicon is deposited in the trench 120, the second gate 94 is formed by etching polysilicon, oxidation is continued after forming the second gate 94, the first gate oxide layer 82 and the electrical isolation layer 134 between the first gate 84 and the second gate 94 are formed, the formation may be thermal oxidation of the second gate 94 directly, polysilicon is deposited in the trench 120 to form the first gate 84, and finally oxide, such as silicon dioxide, is deposited on the surface after forming the first gate 84 to form the dielectric layer 136. The formation of the electrical isolation layer 134 may electrically isolate the first gate 84 from the second gate 94, and the dielectric layer 136 may cover the first gate 84 and the second gate 94, and isolate and protect the first gate 84 and the second gate 94.
As shown in fig. 16, an opening 140 is etched over the second gate 94. The method comprises the following steps: the surface of dielectric layer 136 is patterned to expose a fifth window corresponding to opening 140, and opening 140 is etched through the fifth window. In some embodiments, the lateral width a5 of the opening 140 is in the range of 0.2um to 2.0 um.
As shown in fig. 17, the deposited metal forms a source metal region 150. After etching the opening 140, a metal is deposited to form a source metal region 150, the metal comprising one or more of titanium, nickel, aluminum, and the like. The source metal region 150 is in contact with the second gate 94 through the opening 140 to make electrical connection. The source metal region 150 is also in low resistance contact (e.g., ohmic contact) with the first contact region 72, the first source region 62, the second source region 64, and the second contact region 74, respectively.
As shown in fig. 18, the drain metal region 160 is formed by depositing metal on the bottom surface of the substrate 10, and the drain metal region 160 is in low-resistance contact (e.g., ohmic contact) with the bottom surface of the substrate 10.
Referring to fig. 19 and 20, in some embodiments, when forming the heavily doped region 30 on the surface of the drift layer 20, a third modulation doped region 172 and a fourth modulation doped region 174 are also formed. Wherein, the third modulation doped region 172 and the fourth modulation doped region 174 have the first conductivity type (N-type).
In some embodiments, when the heavily doped region 30 is formed on the surface of the drift layer 20, a third modulation doped region 172 and a fourth modulation doped region 174 are also formed. The method comprises the following steps: a modulation doped region 170 is epitaxially grown on the surface of the drift layer 20 at an epitaxial growth concentration of 8E15cm -3 To 1E17cm -3 Within a range of (1) the surface of the modulation doped region 170 is patterned to expose a sixth window corresponding to the heavily doped region 30, and ion implantation is performed in the sixth window to form the heavily doped region 30, wherein the ion implantation concentration is 1E14cm -3 To 3E15cm -3 In the range of 40keV to 400keV, the implanted ions are doping elements having the second conductivity type (P-type), such as aluminum, boron, etc. Wherein the heavily doped region 30 is formed simultaneously with the formation of the third modulation doped region 172 and the fourth modulation doped region 174.
In some embodiments, when the heavily doped region 30 is formed on the surface of the drift layer 20, a third modulation doped region 172 and a fourth modulation doped region 174 are also formed. The specific steps can also be as follows: ion implantation is performed on the surface of the drift layer 20 to form a modulation doped region 170, the ion implantation concentration is 1E12cm -3 To 1E14cm -3 The ion implantation energy is in the range of 40keV to 400keV, and the implanted ions are doping elements of the first conductivity type (N-type) such as nitrogen, phosphorus, arsenic, etc. The surface of the modulation doped region 170 is patterned to expose a seventh window corresponding to the heavily doped region 30, and ion implantation is performed in the seventh window to form the heavily doped region 30, wherein the ion implantation concentration is 1E14cm -3 To 3E15cm -3 In the range of 40keV to 400keV, the implanted ions are doping elements having the second conductivity type (P-type), such as aluminum, boron, etc. Wherein the heavily doped region 30 is formed simultaneously with the formation of the third modulation doped region 172 and the fourth modulation doped region 174.
Fig. 4 to 20 describe the corresponding steps in a specific embodiment. It should be understood by those skilled in the art that these specific embodiments are illustrative only and are not intended to limit the invention.
In each of the above steps, "patterning" is the process of treating a surface to obtain a desired pattern having windows for the ion implantation operation to be performed, by performing ion implantation at the windows to obtain the respective regions or layers. It will be appreciated by those skilled in the art that due to the complexity of the process involving "patterning", for simplicity of description only, those skilled in the art will be aware that "patterning" generally comprises the steps of: firstly oxidizing the surface to obtain an oxide layer, covering a layer of photoresist or photoresist on the oxide layer, then covering a layer of mask plate with patterns, taking the mask plate as a mask during photoetching, removing or retaining the photoresist or photoresist at the part corresponding to the patterns on the mask plate after photoetching, and removing the oxide layer corresponding to the removed part of the photoresist or photoresist, thereby obtaining a window capable of carrying out ion implantation. And after ion implantation is completed in the window, removing the residual photoresist or the photoresist and the residual oxide layer through a proper process.
The impurity concentration in the modulated doped region 170, the well region 50, and the like obtained by ion implantation as mentioned in the above embodiments may be uniformly distributed or unevenly distributed. For example, the impurity concentration of the modulation doped region 170 near the surface is low, the concentration increases to a peak value toward the bottom surface corresponding to the surface, and then gradually decreases, so that the impurity concentration distribution of the modulation doped region 170 has a retrograde doping profile. Ion implantation may be single implantation, or may include multiple or repeated implantation.
Furthermore, it will be appreciated by those skilled in the art that each of the figures 4-20 does not necessarily correspond to only one step or process. Rather, as semiconductor manufacturing processes typically include many steps, one drawing or more of fig. 4-20 may correspond to two or more steps for brevity and compactness. For example, fig. 5 includes steps of patterning the surface, ion implantation, and the like.
Furthermore, in the methods described above in connection with fig. 4 to 20 and their variants, the steps are not necessarily limited, but the order of some steps may be freely adjusted according to actual needs. The formation steps of the source region 60, the first contact region 72, and the second contact region 74 and may be adjusted according to actual needs. For example, the steps of forming the first contact region 72 and the second contact region 74 may be performed before the source region 60 is formed, or may be performed after the source region 60 is formed.
Those skilled in the art will appreciate that elements (e.g., elements, regions, layers, etc.) in the various figures are not drawn to scale for clarity of illustration. Furthermore, the individual elements in the drawings are not necessarily actual shapes. For example, in the above embodiments, the modulated doping regions 40, the well regions 50, the source regions 60, etc. are all shown as squares in cross-section schematic views, and it will be understood by those skilled in the art that these are for illustrative purposes only, e.g., the actual doping profile typically has a transition region or slope or gradient rather than a profile where the gradient is infinite at a point or boundary. As another example, fig. 9 shows that the lateral width of the heavily doped region 30 is greater than the lateral width of the trench, and in fact, the lateral widths of the two may be the same, while fig. 9 also shows that the lateral contact width of the heavily doped region 30 and the first modulation doped region 42 is approximately equal to the lateral contact width of the heavily doped region 30 and the second modulation doped region 44, and in fact, the two may be unequal, and thus, each of the drawings is for illustration purposes and not limiting the corresponding embodiment.
Finally, it is to be noted that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, which are not to be construed as additional limitations on the scope of the invention, but rather as providing for a more thorough understanding of the present invention. And under the idea of the invention, the technical features described above are continuously combined with each other, and many other variations exist in different aspects of the invention as described above, which are all considered as the scope of the description of the invention; further, modifications and variations of the present invention may be apparent to those skilled in the art in light of the foregoing teachings, and all such modifications and variations are intended to be included within the scope of this invention as defined in the appended claims.

Claims (20)

1. A semiconductor device integrating a MOSFET and a diode, comprising a semiconductor layer, wherein the semiconductor layer comprises a first surface and a second surface opposite to the first surface,
the MOSFET includes:
a first well region extending from the first face in a first direction;
a first source region located within the first well region and extending from the first face in the first direction;
a first gate oxide layer in contact with the first well region;
a first gate electrode in contact with the first gate oxide layer;
the diode includes:
a second well region extending from the first surface in a first direction;
a second source region located within the second well region and extending from the first face in the first direction;
a second gate oxide layer in contact with the second well region;
a second gate electrode in contact with the second gate oxide layer;
the semiconductor device further includes:
the heavily doped region is contacted with the first gate oxide layer and the second gate oxide layer;
a trench extending from the first face to the heavily doped region along the first direction, wherein the first gate oxide layer, the first gate electrode, the second gate oxide layer and the second gate electrode are all located in the trench, and the trench comprises a first trench wall and a second trench wall;
A first contact region located within the first well region, in contact with the first source region and extending from the first face in the first direction;
a second contact region located within the second well region, in contact with the second source region and extending from the first face in the first direction;
the first modulation doped region is positioned on the heavily doped region and is in contact with the first well region;
the second modulation doped region is positioned on the heavily doped region and is in contact with the second well region;
a source metal region in low resistance contact with the first source region, the second source region, the first contact region and the second contact region, and in contact with the second gate to achieve electrical connection;
a metal leakage area positioned below the second surface and in low-resistance contact with the second surface;
the first gate is electrically isolated from the second gate, the first source region, the second source region, the first modulation doped region and the second modulation doped region have a first conductivity type, the first well region, the second well region, the first contact region, the second contact region and the heavily doped region have a second conductivity type opposite to the first conductivity type, and the first direction is a direction perpendicular to the first face or the second face and from the first face to the second face.
2. The semiconductor device of claim 1, wherein a thickness of the first gate oxide layer between the first gate and the first trench wall is in a range of 40nm to 60nm, and a thickness of the second gate oxide layer between the second gate and the second trench wall is in a range of 5nm to 30 nm.
3. The semiconductor device of claim 1, wherein a lateral contact width of the second gate to the source metal region is in a range of 0.2um to 2.0 um.
4. The semiconductor device of claim 1, wherein the heavily doped region has a lateral width in the range of 1.5um to 3.0um and a depth in the range of 0.3um to 1.0 um.
5. The semiconductor device of claim 1, wherein a lateral width of the trench is in a range of 1.5um to 3.0um and a depth is in a range of 1.3um to 2.5 um.
6. The semiconductor device of claim 1, wherein a lateral contact width of the heavily doped region with the first modulation doped region is in a range of 0 to 0.3um, and a lateral contact width of the heavily doped region with the second modulation doped region is in a range of 0 to 0.3 um.
7. The semiconductor device of claim 1, wherein the first contact region and the second contact region each have a width in the range of 0.5 to 2.0um and a depth in the range of 0.3 to 0.5 um.
8. The semiconductor device of claim 1, wherein the semiconductor layer comprises a semiconductor material comprising one or more of silicon carbide, silicon, gallium nitride, or any other wide bandgap semiconductor material.
9. The semiconductor device of claim 1, wherein the source metal region is in low resistance contact with the heavily doped region.
10. The semiconductor device according to any one of claims 1 to 9, further comprising:
the third modulation doped region is contacted with the first modulation doped region and the heavy doped region;
and the fourth modulation doped region is contacted with the second modulation doped region and the heavy doped region.
11. A method of manufacturing a semiconductor device that integrates a MOSFET and a diode, comprising:
providing a substrate;
epitaxially growing a drift layer on a surface of the substrate;
forming a heavily doped region on the surface of the drift layer;
Epitaxially growing a modulation doped region on the surface after the formation of the heavily doped region;
forming a well region on the surface of the modulation doped region;
forming a source region, a first contact region and a second contact region in the well region;
etching a groove, wherein the groove divides the source region into a first source region and a second source region, divides the well region into a first well region and a second well region, and divides the modulation doping region into a first modulation doping region and a second modulation doping region;
forming a first gate oxide layer, a first gate electrode, a second gate oxide layer and a second gate electrode in the groove;
etching an opening above the second gate;
depositing metal to form a source metal region so that the source metal region is in contact with the second grid electrode through the opening;
depositing metal on the bottom surface of the substrate to form a metal leakage region;
the substrate, the drift layer, the source region and the modulation doped region have a first conductivity type, and the well region, the first contact region, the second contact region and the heavily doped region have a second conductivity type opposite to the first conductivity type.
12. The method of manufacturing according to claim 11, wherein a heavily doped region is formed on the surface of the drift layer, and a third modulation doped region and a fourth modulation doped region are further formed.
13. The method of manufacturing of claim 11, wherein forming a heavily doped region on a surface of the drift layer comprises:
patterning the surface of the drift layer to expose a first window corresponding to the heavily doped region;
and performing ion implantation on the first window to form the heavily doped region.
14. The method of manufacturing of claim 11, wherein forming a well region on a surface of the modulation doped region comprises:
epitaxially growing the well region on a surface of the modulation doped region;
or, performing ion implantation on the surface of the modulation doped region to form the well region.
15. The method of manufacturing of claim 11, wherein forming a source region, a first contact region, and a second contact region within the well region comprises:
patterning the surface of the well region to form a second window corresponding to the source region/the first contact region and the second contact region;
Ion implantation is carried out on the second window to form the source region/the first contact region and the second contact region;
patterning the surfaces after forming the source region/the first contact region and the second contact region to expose third windows corresponding to the first contact region and the second contact region/the source region;
ion implantation is performed in the third window to form the first contact region and the second contact region/the source region.
16. The method of manufacturing of claim 11, wherein etching the trench comprises:
patterning the surfaces of the source region, the first contact region and the second contact region to expose a fourth window corresponding to the trench;
etching the groove through the fourth window;
wherein the trench extends from a portion of the surface of the source region toward the substrate to the heavily doped region.
17. The method of manufacturing of claim 11, wherein forming a first gate oxide, a first gate, a second gate oxide, and a second gate in the trench comprises:
forming an oxide layer on the surface of the groove to form an oxide layer;
Depositing first polysilicon in the trench;
etching the first polysilicon to form the second gate;
after the second grid electrode is formed, continuing oxidation to form a first grid oxide layer and an electrical isolation layer;
depositing a second polysilicon in the trench to form the first gate;
depositing oxide on the surface of the first grid electrode to form a dielectric layer;
the second gate oxide layer is formed by the oxide layer, and the first gate and the second gate are electrically isolated through the electrical isolation layer.
18. The method of manufacturing of claim 17, wherein etching an opening over the second gate comprises:
patterning the surface of the dielectric layer to expose a fifth window corresponding to the opening;
and etching the opening through the fifth window.
19. The method of manufacturing according to claim 12, wherein forming a heavily doped region on the surface of the drift layer further forms a third modulation doped region and a fourth modulation doped region, comprising:
epitaxially growing a modulation doped region on the surface of the drift layer;
patterning the surface of the modulation doped region to expose a sixth window corresponding to the heavily doped region;
Ion implantation is carried out on the sixth window to form the heavily doped region;
wherein the third modulation doped region and the fourth modulation doped region are formed simultaneously with the formation of the heavily doped region.
20. The method of manufacturing according to claim 12, wherein forming a heavily doped region on the surface of the drift layer further forms a third modulation doped region and a fourth modulation doped region, comprising:
performing ion implantation on the surface of the drift layer to form a modulation doped region;
patterning the surface of the modulation doped region to expose a seventh window corresponding to the heavily doped region;
ion implantation is carried out on the seventh window to form the heavily doped region;
wherein the third modulation doped region and the fourth modulation doped region are formed simultaneously with the formation of the heavily doped region.
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