CN116092939A - Manufacturing method of planar gate SiC MOSFET device - Google Patents
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- CN116092939A CN116092939A CN202211503298.9A CN202211503298A CN116092939A CN 116092939 A CN116092939 A CN 116092939A CN 202211503298 A CN202211503298 A CN 202211503298A CN 116092939 A CN116092939 A CN 116092939A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 29
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 25
- 239000000463 material Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000007943 implant Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a manufacturing method of a planar gate SiC MOSFET device, which comprises the following steps: s1, providing a substrate, and preparing an epitaxial layer on the substrate; s2, preparing a first hard mask layer on the epitaxial layer; s3, etching a first groove on the first hard mask layer, and then performing ion implantation in the first groove to form a JFET region; s4, preparing a second hard mask layer on the JFET region and the first hard mask layer; s5, processing the first hard mask layer and the second hard mask layer; s6, removing the first hard mask layer to prepare a P well region; s7, preparing an N+spacer; s8, preparing a P+ region; s9, preparing a gate oxide layer and a Poly layer; s10, preparing and forming an ILD layer; s11, depositing metal. The manufacturing method of the planar gate SiC MOSFET device can effectively reduce the on-resistance, protect gate oxide when the device is blocked for voltage resistance, and improve the reliability of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor products, and particularly relates to a manufacturing method of a planar gate SiC MOSFET device.
Background
Power MOSFETs (metal-oxide field effect transistors) have been widely used in a variety of fields as common power semiconductor devices. Most of the current power MOSFETs are made of silicon, but it is difficult to further increase the voltage and current density of the power MOSFET devices due to the physical characteristics of the silicon material. SiC (silicon carbide) has great advantages over silicon materials in physical properties as a wide bandgap semiconductor material. Power MOSFET devices based on SiC materials have been successfully used in some fields, such as new energy automobiles, photovoltaics, and the like.
SiC MOSFETs are currently also classified into two main categories, planar gate and trench gate. Trench gate SiC MOSFETs are lower in on-resistance than planar gate SiC MOSFETs, but trench gates have weaker gate protection due to the deep penetration of the gate into the drift region, and even have to be protected by sacrificing channel density. The planar gate device has the JFET region, and PN junction depletion layers at two sides of the JFET region can be expanded to the lower part of the gate oxide layer when the voltage is blocked, so that a certain protection effect is achieved on the gate oxide layer, and the planar gate device has a larger advantage in the aspect of reliability. In addition, since SiC materials are hard and have instability in trench etching, planar gate devices are also more advantageous in process stability. The existing automotive main drive SiC MOSFET application is mainly a planar gate SiC MOSFET.
Fig. 2.1 is a cross-section of a SiC planar MOSFET device structure fabricated using existing fabrication methods: after the hard mask is removed after the injection of the P well and the N+ region is completed, a new hard mask is produced and opened by photoetching, and then the ion injection is carried out, so that the on-resistance of the region is reduced. The manufacturing process of the conventional planar gate SiC MOSFET is as follows:
1. growing an epitaxial layer 101 on a 4H-SiC substrate 100 having a primary reference plane crystal orientation <11-20>, as shown in fig. 3.1 a;
2. forming a hard mask layer 102 on the epitaxial layer 101 using an LPCVD (low pressure chemical vapor deposition) method, as shown in fig. 3.1 b;
3. photoetching and etching to open the hard mask layer P well region, removing photoresist, and then performing ion implantation to form a P well region 103, as shown in FIG. 3.1 c;
4. an LPCVD method is used for growing an isolation layer with a certain thickness, and then the isolation layer with the same thickness is etched downwards to form an N+ Spacer 104, as shown in fig. 3.1 d;
5. ion implantation to form an n+ region 105, followed by removal of the n+ Spacer 104 and the hard mask layer 102, as shown in fig. 3.1 e;
6. growing a new hard mask layer, opening a JFET region of the hard mask layer by photoetching, removing photoresist, performing ion implantation to form a JFET region 106, and removing the hard mask layer, wherein the JFET region is shown in FIG. 3.1 f;
7. growing a new hard mask layer, opening a P+ region of the hard mask layer by photoetching, removing photoresist, performing ion implantation to form a P+ region 107, and removing the hard mask layer, wherein the hard mask layer is shown in fig. 3.1 g;
8. growing a gate oxide layer 108 by using hot oxygen, depositing a Poly layer 109, opening a source contact hole area by photoetching, sequentially etching the Poly layer 109 and the gate oxide layer 108 until reaching the surface of the epitaxial layer 101, and removing photoresist, wherein the photoresist is shown in FIG. 3.1 h;
9. growing an isolation oxide layer by using an LPCVD method, photoetching and etching to open a source contact hole area, then etching the isolation oxide layer to the surface of the epitaxial layer 101 to form an ILD layer 110, continuing to etch the epitaxial layer 101 downwards until the N+ area 105 is etched through, enabling the contact hole to contact the P+ area 107, and then removing photoresist, as shown in figure 3.1 i;
10. metal 111 is deposited as shown in fig. 3.1 j.
Planar gate SiC MOSFETs have a JFET region that is the middle region of two P-wells. Because the N-type epitaxial layer of the JFET region is connected with high potential, the P-well is connected with low potential and the doping concentration of the P-well is higher than that of the JFET region during forward conduction, the depletion layer can expand to the JFET region, and the on-resistance is increased. In practice, the on-resistance of the JFET region is an important component of the overall on-resistance of the planar MOSFET device. In order to reduce the on-resistance, it is necessary to implant the JFET region with N-type impurities or widen the JFET region width. However, since the gate oxide is present above the JFET region and the P-type region is not used to protect the gate oxide, the electric field at the gate oxide above the JFET region is high during reverse breakdown voltage, which has a certain influence on the breakdown voltage and reliability of the device. To reduce this effect, the JFET region width is typically reduced. To sum up, in order to achieve both reliability and on-resistance, the JFET region width is typically reduced while the N-type implant in that region is increased.
The common JFET implantation method is to etch the hard mask by using a photolithography plate, and when the JFET region width is small, there is a high requirement for the bias of the photolithography process. Too large offset can cause the JFET region to cover a channel on one side, if the injection dosage of the JFET region is higher, the channel length on one side can be shortened, short channel effect occurs even a drain-source short circuit phenomenon occurs when the device is switched on and the JFET region on the other side, which is not injected with any impurity due to photoetching offset, can greatly increase on-resistance, as shown in fig. 3, the a region covers the channel, and the drain-source series connection can be caused; the b region is not implanted with any impurity, and on-resistance increases.
Another way is to perform JFET implantation over the entire active region, which avoids the problems of photolithographic misalignment, but the dose of the low energy implant cannot be increased because of the integral implant. Because the increased dose of the low energy implant affects the channel region, resulting in a shift in the threshold. And the decrease in on-resistance is very limited because the surface concentration cannot be increased.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a manufacturing method of a planar gate SiC MOSFET device, which aims to effectively reduce on-resistance, protect gate oxide when the device is blocked for voltage resistance and improve the reliability of the device.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: the manufacturing method of the planar gate SiC MOSFET device comprises the following steps:
s1, providing a substrate, and preparing an epitaxial layer on the substrate;
s2, preparing a first hard mask layer on the epitaxial layer;
s3, etching a first groove on the first hard mask layer, and then performing ion implantation in the first groove to form a JFET region;
s4, preparing a second hard mask layer on the JFET region and the first hard mask layer;
s5, processing the first hard mask layer and the second hard mask layer to enable the thicknesses of the first hard mask layer and the second hard mask layer to be the same;
s6, removing the first hard mask layer to form a P well injection mask layer, and then performing ion injection to form a P well region;
s7, preparing an N+ Spacer, and performing ion implantation to form an N+ region;
s8, removing the N+ Spacer and the second hard mask layer to prepare a P+ region;
s9, sequentially preparing a gate oxide layer and a Poly layer, opening a source contact hole area by photoetching, and sequentially etching the gate oxide layer and the Poly layer until the surface of the epitaxial layer is reached;
s10, preparing an isolation oxide layer, opening a source contact hole area by photoetching, and then etching the isolation oxide layer to the surface of the epitaxial layer to form an ILD layer;
s11, depositing metal.
In the step S1, the substrate is made of 4H-SiC, and the crystal orientation is <11-20>.
In the step S2, a first hard mask layer is formed on the epitaxial layer by an LPCVD process.
In the step S4, a second hard mask layer is prepared by an LPCVD process.
In step S5, the second hard mask layer is first ground by using a CMP process, and then the first hard mask layer and the second hard mask layer are processed by using dry etching, so that the first hard mask layer and the second hard mask layer are in the same thickness, the processed second hard mask layer is located outside the first hard mask layer, and the second hard mask layer covers the JFET region.
In the step S6, the first hard mask layer is removed by using a reactive ion etching process.
In the step S7, an LPCVD process is used to grow an isolation layer with a certain thickness, then the isolation layer with the same thickness is etched downwards to form an n+ Spacer, and ion implantation is performed to form an n+ region.
In the step S8, the n+ Spacer and the second hard mask layer are removed, a new hard mask layer is grown, the p+ region of the hard mask layer is opened by photolithography etching, the p+ region is formed after ion implantation, and then the hard mask layer is removed.
In the step S9, the gate oxide layer is grown by thermal oxygen, and then the Poly layer is deposited.
The manufacturing method of the planar gate SiC MOSFET device can effectively reduce the on-resistance, protect gate oxide when the device is blocked for voltage resistance, and improve the reliability of the device.
Drawings
The present specification includes the following drawings, the contents of which are respectively:
FIGS. 1 a-1 k are schematic diagrams of the planar gate SiC MOSFET device manufacturing process of the present invention;
fig. 2.1 is a cross-section of a SiC planar MOSFET device structure fabricated using existing fabrication methods;
fig. 3.1 a-3.1 j are schematic diagrams of prior art planar gate SiC MOSFET device fabrication processes.
Detailed Description
The following detailed description of the embodiments of the invention, given by way of example only, is presented in the accompanying drawings to aid in a more complete, accurate and thorough understanding of the concepts and aspects of the invention, and to aid in its practice, by those skilled in the art.
In order to make the planar SiC MOSFET device possess a sufficiently small JFET width to meet the requirements of reliability on the gate oxide electric field, and also make a higher concentration implant in the JFET region to reduce on-resistance.
The invention provides a novel manufacturing method of a SiC planar power MOSFET, which comprises the following steps: and utilizing the deposition and etching of the film layer to convert the hard mask implanted by the JFET into the hard mask implanted by the P-well, namely the JFET and the P-well are self-aligned.
The process provided by the invention removes the photoetching step during P well injection, eliminates alignment deviation caused by the step, ensures the normal function of the device, and improves the performance; in addition, the use of one photomask plate is reduced, and the production cost is reduced.
Specifically, as shown in fig. 1a to 1k, the present invention provides a method for manufacturing a planar gate SiC MOSFET device, including the steps of:
s1, providing a substrate 300, and preparing an epitaxial layer 301 on the substrate 300;
s2, preparing a first hard mask layer 302 on the epitaxial layer 301;
s3, etching a first groove on the first hard mask layer 302, and then performing ion implantation in the first groove to form a JFET region 303;
s4, preparing a second hard mask layer 304 on the JFET region 303 and the first hard mask layer 302;
s5, processing the first hard mask layer 302 and the second hard mask layer 304 to enable the thicknesses of the first hard mask layer 302 and the second hard mask layer 304 to be the same;
s6, removing the first hard mask layer 302 to form a P well injection mask layer, and then performing ion injection to form a P well region 305;
s7, preparing an N+ Spacer306, and performing ion implantation to form an N+ region 307;
s8, removing the N+ Spacer306 and the second hard mask layer 304 to prepare a P+ region 308;
s9, sequentially preparing a gate oxide layer 309 and a Poly layer 310, opening a source contact hole area by photoetching, and sequentially etching the gate oxide layer 309 and the Poly layer 310 until the surface of the epitaxial layer 301;
s10, preparing an isolation oxide layer, opening a source contact hole area by photoetching, and then etching the isolation oxide layer to the surface of the epitaxial layer 301 to form an ILD layer 311;
s11, depositing metal 312.
In the above step S1, the substrate 300 is made of 4H-SiC and has a crystal orientation of<11-20>In the main reference plane the crystal orientation is<11-20>A buffer layer and a drift region having a certain doping concentration are epitaxially grown on the 4H SiC substrate 300. Typical buffer doping concentration is 1E18cm -3 The doping concentration and thickness of the drift region are determined according to the withstand voltage value of the device, the thickness of the drift region of a typical 1200V device is 10-12 um, and the doping concentration is 8E15cm -3 —1E16cm -3 . As shown in fig. 1a, the crystal orientation is at the main reference plane<11-20>An epitaxial layer 301 is grown on the 4H-SiC substrate 300.
As shown in fig. 1b, in the step S2, a first hard mask layer 302 is formed on the upper surface of the epitaxial layer 301 by using an LPCVD (low pressure chemical vapor deposition) process, and the material of the first hard mask layer may be SiO 2 Polysilicon, siN, or other material suitable for a hard mask layer.
As shown in fig. 1c, the first hard mask layer JFET region is opened by a photolithographic etch, and the photoresist is removed followed by ion implantation to form JFET region 303.
As shown in fig. 1D, a second hard mask layer 304 having a certain thickness D is grown by an LPCVD (low pressure chemical vapor deposition) process, and the second hard mask layer 304 covers the underlying first hard mask layer 302 and JFET region 303, and the material of the second hard mask layer 304 should have a higher selectivity to the material of the first hard mask layer 302.
In this embodiment, the selection ratio of the material of the second hard mask layer 304 to the material of the first hard mask layer 302 is above 1:6.
As shown in fig. 1e, the same thickness D is polished down using a CMP (chemical mechanical polishing) method, then the first hard mask layer 302 and the second hard mask layer 304 are brought to the same thickness using dry etching, the second hard mask layer 304 over the first hard mask layer 302 is removed, and the second hard mask layer 304 covering the JFET region 303 remains.
As shown in fig. 1f, the first hard mask layer 302 is removed by using a reactive ion etching process, a P-well implantation mask layer is formed on the epitaxial layer 301, and then ion implantation is performed to form a P-well region 305, and the jfet region 303 is located outside the P-well region 305.
As shown in fig. 1g, an LPCVD process is used to grow an isolation layer with a certain thickness, then the isolation layer with the same thickness is etched down to form an n+ Spacer306, and ion implantation is performed to form an n+ region 307, where the n+ Spacer306 and the n+ region 307 are located above the P-well region 305, the n+ Spacer306 is in contact with the second hard mask layer 304, and the n+ region 307 is located between the second hard mask layer 304 and the n+ Spacer 306.
As shown in fig. 1h, the n+ Spacer306 and the second hard mask layer 304 are removed, then a new hard mask layer is grown, a new hard mask layer p+ region is opened by lithography etching, a p+ region 308 is formed after ion implantation, and then the hard mask layer is removed.
As shown in fig. 1i, a gate oxide layer 309 is grown by thermal oxygen, the gate oxide layer 309 covers the JFET region 303, the P-well region 305 and the n+ region 307, then a Poly layer 310 is deposited on the gate oxide layer 309, a source contact hole region is opened by photolithography etching, then the gate oxide layer 309 and the Poly layer 310 are sequentially etched until reaching the surface of the epitaxial layer 301, and then the photoresist is removed.
As shown in fig. 1j, an isolation oxide layer is deposited and grown, the source contact hole area is opened by photolithographic etching, then the isolation oxide layer is etched to the surface of the epitaxial layer 301, an ILD layer 311 is formed, the ILD layer 311 covers the Poly layer 310 and the n+ region 307, and then the photoresist is removed.
As shown in fig. 1k, a metal 312 is deposited, the metal 312 overlying ILD layer 311 and n+ region 307.
According to the manufacturing method of the SiC planar power MOSFET, the self-alignment is formed between the JFET region and the P-well region, and smaller P-well spacing and higher JFET injection can be designed on the basis, so that on-resistance is effectively reduced, gate oxide is protected when the device is blocked and withstand voltage is achieved, and reliability of the device is improved. In addition, the method reduces the use of one photomask plate and reduces the production cost.
The invention is described above by way of example with reference to the accompanying drawings. It will be clear that the invention is not limited to the embodiments described above. As long as various insubstantial improvements are made using the method concepts and technical solutions of the present invention; or the invention is not improved, and the conception and the technical scheme are directly applied to other occasions and are all within the protection scope of the invention.
Claims (9)
1. The manufacturing method of the planar gate SiC MOSFET device is characterized by comprising the following steps:
s1, providing a substrate, and preparing an epitaxial layer on the substrate;
s2, preparing a first hard mask layer on the epitaxial layer;
s3, etching a first groove on the first hard mask layer, and then performing ion implantation in the first groove to form a JFET region;
s4, preparing a second hard mask layer on the JFET region and the first hard mask layer;
s5, processing the first hard mask layer and the second hard mask layer to enable the thicknesses of the first hard mask layer and the second hard mask layer to be the same;
s6, removing the first hard mask layer to form a P well injection mask layer, and then performing ion injection to form a P well region;
s7, preparing an N+ Spacer, and performing ion implantation to form an N+ region;
s8, removing the N+ Spacer and the second hard mask layer to prepare a P+ region;
s9, sequentially preparing a gate oxide layer and a Poly layer, opening a source contact hole area by photoetching, and sequentially etching the gate oxide layer and the Poly layer until the surface of the epitaxial layer is reached;
s10, preparing an isolation oxide layer, opening a source contact hole area by photoetching, and then etching the isolation oxide layer to the surface of the epitaxial layer to form an ILD layer;
s11, depositing metal.
2. The method of manufacturing a planar gate SiC MOSFET device according to claim 1, wherein in step S1, the substrate is made of 4H-SiC and the crystal orientation is <11-20>.
3. The method of fabricating a planar gate SiC MOSFET device according to claim 1, wherein in step S2, a first hard mask layer is formed on the epitaxial layer using an LPCVD process.
4. A method of fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, wherein in step S4, the second hard mask layer is prepared by an LPCVD process.
5. A method of fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, wherein in step S5, the second hard mask layer is first polished by a CMP process, and then the first hard mask layer and the second hard mask layer are processed by dry etching, so that the first hard mask layer and the second hard mask layer are at the same thickness, the processed second hard mask layer is located outside the first hard mask layer and the second hard mask layer covers the JFET region.
6. A method of fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, wherein in step S6, the first hard mask layer is removed using a reactive ion etching process.
7. A method for fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, wherein in step S7, an LPCVD process is used to grow an isolation layer of a certain thickness, then the isolation layer of the same thickness is etched down to form an n+ Spacer, and ion implantation is performed to form an n+ region.
8. A method for fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, wherein in step S8, the n+ Spacer and the second hard mask layer are removed, a new hard mask layer is grown, the p+ region of the hard mask layer is opened by photolithography etching, the p+ region is formed after ion implantation, and then the hard mask layer is removed.
9. A method of fabricating a planar gate SiC MOSFET device according to any one of claims 1 to 3, characterized in that in step S9, the gate oxide layer is grown by thermal oxygen, followed by deposition of the Poly layer.
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