CN110660863A

CN110660863A - Silicon carbide MOSFET power device and preparation method thereof

Info

Publication number: CN110660863A
Application number: CN201911005732.9A
Authority: CN
Inventors: 王谦; 柏松; 杨勇
Original assignee: CETC 55 Research Institute
Current assignee: CETC 55 Research Institute
Priority date: 2019-10-22
Filing date: 2019-10-22
Publication date: 2020-01-07

Abstract

The invention provides a silicon carbide MOSFET power device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate with heavily doped first doping type, and forming a lightly doped epitaxial layer with the first doping type on the first surface; forming a well region in the epitaxial layer; forming a source region surrounding the JFET region in the well region, and forming a contact region in the well region surrounding the source region; doping the first doping type in the defined JFET region to form a JFET buried layer type doping region; forming a gate structure on the surface of the epitaxial layer, and depositing a surface passivation layer on the surface of the gate structure; and forming a gate metal electrode electrically connected with the gate structure, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate. According to the invention, the buried layer type doped region is formed after N-type ion implantation is carried out on the JFET region of the conventional planar gate MOSFET power device, so that the resistance of the JFET region is reduced, the electric field intensity in the gate oxide is prevented from being improved, and the breakdown risk of the gate oxide is reduced.

Description

Silicon carbide MOSFET power device and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor device structures and preparation, and particularly relates to a silicon carbide MOSFET power device and a preparation method thereof.

Background

With the continuous development of power electronic technology towards high energy efficiency, high power density and miniaturization, higher requirements are put on the power consumption and the switching speed of the power switching device. SiC (silicon carbide) as a third-generation semiconductor material has a series of excellent characteristics such as large forbidden band width, high critical breakdown electric field strength, high thermal conductivity and the like, and is very suitable for manufacturing high-temperature, high-frequency and high-power electronic devices. The SiC power switch device can simultaneously realize excellent performances of high breakdown voltage, low on-resistance, high switching speed, easy heat dissipation and the like, has obvious competitiveness in the power electronic technology with high energy efficiency, high power and high temperature, and becomes a research hotspot of the current power semiconductor technology. Particularly, the SiC MOSFET has the performance advantages that the Si MOSFET is incomparable with the IGBT, such as wide forbidden band width, high breakdown voltage, low on-resistance, high switching speed, high energy conversion efficiency, easy heat dissipation, radiation resistance and the like. SiC MOSFETs are rapidly being studied and commercialized as a new generation of power switching devices that have attracted attention. However, compared with foreign countries, the research on the SiC MOSFET power device in China is in the primary stage, the product is mainly imported from foreign countries, and the research and development process of the SiC MOSFET power device is urgently needed to be accelerated.

The on-resistance is one of the most important performance indexes of the power device, and how to reduce the on-resistance of the device is a technical difficulty. Particularly in a planar gate type SiC MOSFET, due to the presence of the parasitic JFET region, a resistance is imparted to the device at the JFET region, thereby increasing the on-resistance of the device. In addition, the dielectric constant of the SiC material is close to that of the SiO gate dielectric₂3 times of the material, and the SiC material has higher critical breakdown electric field intensity (3 MV/cm). Therefore, when the device is operated in the blocking state, it will be in SiO₂High electric field intensity is introduced, so that the breakdown of the high electric field intensity is damaged, and the device fails. Chinese patent No. cn201710678411.x discloses a box-like heavily doped SiC MOSFET device in a JFET region and a method for manufacturing the same, wherein the heavily doped JFET region can not only improve the doping concentration of the region, but also reduce the depletion effect of p-wells on both sides of the region, thereby reducing the parasitic resistance of the JFET region of the device. However, the structure reduces the resistance of the JFET region, and simultaneously increases the electric field intensity in the gate oxide when the device is in a blocking state, so that the gate oxide breakdown risk is increased.

Therefore, it is necessary to provide a SiC MOSFET power device and a method for manufacturing the same, which can effectively reduce the resistance of the JFET region and simultaneously reduce the electric field strength in the gate oxide.

Disclosure of Invention

In order to solve the problems, the invention provides a silicon carbide MOSFET power device and a preparation method thereof, which are used for solving the problems that in the prior art, due to the existence of JFET (junction field effect transistor) area resistance, the on-resistance of the device is large, and the electric field intensity in gate oxide is large.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a preparation method of a silicon carbide MOSFET power device comprises the following steps:

s1: providing a substrate with heavily doped first doping type, wherein the substrate is provided with a first surface and a second surface, and an epitaxial layer with lightly doped first doping type is formed on the first surface;

s2: determining a JFET area in the epitaxial layer, and doping the second doping type in the area surrounding the JFET area in the epitaxial layer to form a well area;

s3: heavily doping the first doping type in the well region to form a source region surrounding the JFET region, and heavily doping the second doping type in the region surrounding the source region in the well region to form a contact region;

s4: doping the JFET region with a first doping type to form a JFET buried layer type doping region;

s5: forming a gate structure on the surface of the epitaxial layer, wherein the gate structure at least covers the JFET buried layer type doped region, depositing a surface passivation layer on the surface of the gate structure, and forming a first window corresponding to the gate structure in the surface passivation layer;

s6: forming a source region ohmic contact metal layer on the surfaces of the source region and the protection region, and forming a drain region ohmic contact metal layer on the second surface of the substrate;

s7: and forming a gate metal electrode electrically connected with the gate structure in the first window, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate.

In this technical solution, preferably, when the first doping type is an N type, the second doping type is a P type; when the first doping type is P type, the second doping type is N type.

Preferably, in step S1, a buffer layer is formed in advance of the first surface of the substrate, and then an epitaxial layer is formed on the buffer layer.

Preferably, in step S3, the depth of the contact region is greater than that of the source region, and the depth of the contact region is less than that of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

Preferably, in step S4, the forming the JFET buried layer type doped region includes the following steps:

s4-1: depositing an injection shielding layer on the surface of the epitaxial layer;

s4-2: forming an injection mask layer on the surface of the injection shielding layer, etching the injection mask layer through a photoetching process to form an injection mask pattern, wherein the injection mask pattern at least covers the well region;

s4-3: taking the implantation mask pattern as an implantation mask, and performing ion implantation in the JFET area;

s4-4: and activating the implanted ions to form a JFET buried layer type doped region.

Preferably, in step S4-1, the thickness of the injection shielding layer is 30 to 50 nm; in step S4-3, the number of times of ion implantation is 3-5, the implantation energy is 150-450 keV, and the implantation dose is 3e¹¹～8e¹¹cm^-2(ii) a In the step S4-4, the temperature of the activation treatment is 1650-1750 ℃, and the time of the activation treatment is 20-40 min.

Preferably, in step S5, the forming the gate structure and the surface passivation layer includes the following steps:

s5-1: forming a gate dielectric material layer on the surface of the epitaxial layer by adopting a dry thermal oxidation technology;

s5-2: forming a polycrystalline silicon layer on the surface of the gate dielectric material layer;

s5-3: forming a surface passivation material layer on the surfaces of the polycrystalline silicon layer and the exposed gate dielectric material layer;

s5-4: and etching the surface passivation material layer and the gate dielectric material layer to expose at least the second window corresponding to the source region, and forming a gate structure and a surface passivation layer.

Preferably, a silicon carbide MOSFET power device, comprising:

a substrate heavily doped with a first doping type, having a first surface and a second surface;

a lightly doped epitaxial layer of a first doping type on the first surface of the substrate;

the JFET buried layer type doped region doped with the first doping type is positioned in the epitaxial layer;

the well region doped with the second doping type is positioned in the epitaxial layer and surrounds the JFET buried layer type doping region;

the source region with the heavily doped first doping type is positioned in the well region and surrounds the JFET buried layer type doping region;

the contact region with the heavily doped second doping type is positioned in the well region and surrounds the source region;

the gate structure is positioned on the surface of the JFET buried layer type doped region;

a gate metal electrode;

a source metal electrode;

a drain metal electrode;

the source region is in ohmic contact with the metal layer;

the drain region is in ohmic contact with the metal layer;

the grid metal electrode is electrically connected with the grid structure, the source metal electrode is electrically connected with the source region, and the drain metal electrode is electrically connected with the second surface of the substrate;

the source region ohmic contact metal layer is positioned on the surfaces of the source region and the contact region and is positioned below the source metal electrode; the drain ohmic contact metal layer is positioned between the second surface of the substrate and the drain metal electrode.

Preferably, when the first doping type is N-type, the second doping type is P-type; when the first doping type is P type, the second doping type is N type.

Preferably, the depth of the JFET buried layer type doped region is 0.2-0.3 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.5 mu m, and the ion doping concentration of the JFET buried layer type doped region is 5e¹⁶～1e¹⁷ cm^-3。

Preferably, the depth of the contact region is greater than the depth of the source region and less than the depth of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

Preferably, the silicon carbide MOSFET power device further comprises a buffer layer located between the substrate and the epitaxial layer; the epitaxial layer is made of 4H-SiC, and the crystal orientation of the substrate deviates from the (11-20) direction by an inclination angle of 4 +/-0.5 degrees.

Preferably, the surface of the gate structure further comprises a surface passivation layer, and the thickness of the surface passivation layer is 0.6-1.0 μm.

Advantageous effects

The invention optimizes the structure of the device, and particularly forms a buried layer type heavily doped structure after n-type ion implantation is carried out in a JFET (junction field effect transistor) area of a conventional planar gate MOSFET (metal-oxide-semiconductor field effect transistor) power device. The structure can improve the doping concentration of the JFET region, increase the carrier concentration of the JFET region and increase the current transmission capability; the depletion effect of the double-side well region on the JFET region can be reduced, so that more carriers can participate in conduction. Accordingly, the buried layer type heavily doped structure can reduce the JFET region resistance of the SiC MOSFET device, preferably reducing the on-resistance of the device. In addition, the buried layer type heavily doped structure does not increase the doping concentration of a JFET (junction field effect transistor) region below the gate oxide, so that the increase of the electric field intensity in the gate oxide can be avoided, the gate oxide breakdown risk is reduced, and the gate oxide reliability is improved.

The device structure and the preparation process are simple, the effect is obvious, and the device structure and the preparation method have wide application prospects in the novel MOSFET power device structure and the preparation method.

Drawings

The invention is further illustrated with reference to the following figures and examples.

Fig. 1 is a flow chart of a method for manufacturing a silicon carbide MOSFET power device according to the present invention.

Fig. 2 to 14 are schematic structural views of steps in the preparation of the silicon carbide MOSFET power device of the present invention:

FIG. 2 is a schematic diagram of a structure for providing a substrate in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 3 is a schematic diagram of the structure of the epitaxial layer formed in the preparation of the silicon carbide MOSFET power device of the present invention;

FIG. 4 is a schematic diagram of the structure of the buffer layer formed in the fabrication of the silicon carbide MOSFET power device of the present invention;

FIG. 5 is a schematic diagram of a well region formed in the fabrication of a silicon carbide MOSFET power device according to the present invention;

FIG. 6 is a schematic diagram of the structure for forming source and contact regions in the fabrication of a silicon carbide MOSFET power device of the present invention;

FIG. 7 is a schematic structural diagram of a buried doped region for forming a JFET in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 8 is a schematic structural diagram of a gate dielectric material layer formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 9 is a schematic diagram of a polysilicon layer formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 10 is a schematic diagram of a structure for forming a surface passivation layer in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 11 is a schematic diagram of a gate structure and a second window formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 12 is a schematic structural diagram of a source and drain ohmic contact metal layer formed during fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

fig. 13 is a schematic diagram of a first window formation in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention.

Fig. 14 is a schematic diagram of the structure of the electrode formed in the preparation of the silicon carbide MOSFET power device of the present invention.

In the drawings:

101. substrate 102, buffer layer 103, epitaxial layer 104, well region

105. Source region 106, contact region 107, JFET buried layer type doped region 108, and gate dielectric material layer

109. Polysilicon layer 110, surface passivation material layer 111, gate dielectric layer 112, and surface passivation layer

113. Second window 114, source ohmic contact metal layer 115, drain ohmic contact metal layer 116, first window

117. Source metal electrode 118, gate metal electrode 119, drain metal electrode 120, gate structure

1011. First surface 1012 and second surface

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Example 1:

please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1 to 14, the present invention provides a method for manufacturing a silicon carbide MOSFET power device, comprising the following steps:

s1: providing a substrate with heavily doped first doping type, wherein the substrate is provided with a first surface and a second surface, and a lightly doped epitaxial layer with the first doping type is formed on the first surface;

s2: defining a JFET area in the epitaxial layer, and doping the second doping type in the epitaxial layer surrounding the JFET area to form a well region;

s3: heavily doping the first doping type in the well region to form a source region surrounding the JFET region, and heavily doping the second doping type in the well region surrounding the source region to form a contact region;

s5: forming a gate structure on the surface of the epitaxial layer, wherein the gate structure at least covers the JFET buried layer type doped region, and depositing a surface passivation layer on the surface of the gate structure, wherein a first window corresponding to the gate structure is formed in the surface passivation layer;

s6: and forming a gate metal electrode electrically connected with the gate structure in the first window, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate.

The following describes in detail a method for manufacturing a silicon carbide MOSFET power device according to the present invention with reference to the accompanying drawings.

As shown in S1 of fig. 1 and fig. 2 to 4, step S1 is performed to provide a substrate 101 heavily doped with the first doping type, wherein the substrate 101 has a first surface 1011 and a second surface 1012, and the epitaxial layer 103 lightly doped with the first doping type is formed on the first surface 1011;

as an example, the first doping type is N-type doping and the second doping type is P-type doping.

Specifically, a semiconductor substrate is provided and ion-doped with a first doping type, which may be N-type or P-type, and is selected to be N-type and heavily doped in this embodiment, i.e., an N + type semiconductor substrate, and is defined to have a first surface and a second surface. In addition, the material of the substrate 101 may be a semiconductor substrate containing a silicon carbide (SiC) material, both of which are selected to be 4H — SiC in the present embodiment, and further, the substrate 101 is off-oriented by (4 ± 0.5) ° tilt in the (11-20) direction.

As an example, in step 1), the buffer layer 102 is formed before the first surface 1011 of the substrate 101, and then the epitaxial layer 103 is formed on the buffer layer 102.

In addition, an epitaxial layer 103 is formed on any surface of the substrate 101, such as the first surface 1011 in this embodiment, wherein the doping type of the epitaxial layer 103 is selected to be the same as the doping type of the substrate 101, but the epitaxial layer 103 is a lightly doped material layer (i.e., an N-type epitaxial layer) whose material is a semiconductor substrate containing a silicon carbide (SiC) material, in this embodiment 4H-SiC is selected.

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate 101 and the epitaxial layer 103, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment, is selected to be 0.7 μm.

As shown in S2 of fig. 1 and fig. 5, step S2 is performed to define a JFET region in the epitaxial layer 103 and perform doping of the second doping type in the epitaxial layer 103 surrounding the JFET region to form a well region 104;

specifically, the purpose of this step is to form a well region 104 having a doping type different from that of the epitaxial layer 103, and in this embodiment, is selected to form a P-type well region. In addition, the inner side of the well region 104 and the JFET region are preferably in contact, but of course, in other embodiments, there may be a predetermined distance therebetween, and the shape of the well region 104 is a ring, and may be a circular ring or a square ring, and in this embodiment, is selected to be a circular ring.

As shown in S3 of fig. 1 and fig. 6, step S3 is performed to heavily dope the well 104 with the first doping type to form the source region 105 surrounding the JFET region, and to heavily dope the well 104 surrounding the source region 105 with the second doping type to form the contact region 106;

as an example, the depth of contact region 106 is greater than the depth of source region 105 and less than the depth of well region 104; the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5-1 μm.

Specifically, in this step, a source region and a contact region are formed in the well region 104, wherein the doping type of the source region 105 is opposite to that of the well region 104, N-type heavy doping is selected in this embodiment, the doping type of the contact region 106 is the same as that of the well region, P-type heavy doping is selected in this embodiment, the contact region 106 is used to form a body diode, release reverse current in the device, and release holes, preferably, the contact region 106 is in contact with the source region 105, and the upper surfaces of the contact region and the source region are both flush with the upper surface of the epitaxial layer, further, the depth of the source region 105 is 0.2 μm to 0.5 μm, the depth of the contact region 106 is 0.5 μm to 0.8 μm, in this embodiment, the depth of the source region 105 is 0.3 μm, the depth of the contact region 106 is 0.7 μm, the depth of the contact region 106 is greater than that of the source region 105, so that the reverse withstand voltage, the voltage endurance of the device is further improved. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.7 μm.

As shown in S4 of fig. 1 and fig. 7, proceed to step 4), doping the defined JFET region 107 with a first doping type to form a JFET buried layer doped region 107;

specifically, in the present application, doping of the same doping type as that of the epitaxial layer is performed in the JFET region in the well region 104, which is N-type ion implantation in this embodiment, it should be noted that the present invention optimizes the device structure, and particularly, after ion implantation is performed in the JFET region of the conventional planar gate silicon carbide MOSFET power device, a JFET buried layer type doping region is formed, so that the resistance of the JFET region is reduced, and at the same time, the electric field strength in the gate oxide can be reduced, thereby avoiding breakdown thereof.

As an example, in step S4, the specific step of forming the buried layer type heavily doped JFET region 107 includes:

s4-1, depositing an injection shielding layer on the surface of the epitaxial layer 103;

s4-2, forming an injection mask layer on the surface of the injection shielding layer, etching the injection mask layer through a photoetching process to form an injection mask pattern, wherein the injection mask pattern at least covers the well region;

s4-3, taking the implantation mask pattern as an implantation mask, and performing ion implantation in the defined JFET region;

s4-4 performs an activation process on the implanted ions to form the JFET buried layer doped region 107.

Specifically, in the specific step of forming the JFET buried layer doped region 107, an implantation mask layer of a material including, but not limited to, SiO, is deposited on the surface of the epitaxial layer 103 by a chemical vapor deposition technique (e.g., PECVD, LPCVD)₂(ii) a Secondly, forming an implantation mask layer on the surface of the implantation shielding layer, in this embodiment, a photoresist is used as the implantation mask layer, i.e., the surface of the implantation shielding layer is coated with a photoresist, and then the photoresist is exposedForming an injection mask pattern after the developing and hardening process, wherein the injection mask pattern covers the position of the well region 104 or extends to the inner side of the well region 104; then, carrying out ion implantation by taking the implantation mask pattern as an implantation mask, and meanwhile, taking the implantation shielding layer as a shielding layer for ion implantation, wherein the thickness of the implantation shielding layer is 30-50 nm, preferably 36-39 nm, and is selected to be 38nm in the embodiment, so as to reduce the ion channel effect of the MOSFET device; then, after ion implantation, removing the photoresist layer and the implantation shielding layer; and finally, activating the implanted ions by a high-vacuum high-temperature annealing furnace to obtain a final JFET buried layer type doped region with the same doping type as the epitaxial layer.

For example, in step S4-1, the thickness of the injection shielding layer is 30-50 nm; in step S4-3, the number of times of ion implantation is 3-5, the implantation energy is 150-450 keV, and the implantation dose is 3e¹¹～8e¹¹cm^-2(ii) a In the step S4-4, the temperature of the activation treatment is 1650-1750 ℃, and the time of the activation treatment is 20-40 min.

Specifically, the ion doping can be performed by multiple ion implantations, the implantation times are determined according to actual requirements, wherein in different implantation times, each implantation energy is selected from 150-450 keV, and each implantation dosage is selected from 3e¹¹～8e¹¹cm^-2Further, the implantation energy is preferably 160 to 180keV or 200 to 250keV, and the implantation dose is preferably 3e¹¹～5e¹¹cm^-2Or the implantation dose is preferably 4e¹¹～5e¹¹cm^-2In this embodiment, the implantation times are 4 times, the first implantation energy is 420keV, and the implantation dose is 7e¹¹ cm^-2(ii) a Accordingly, 320keV, 4e¹¹ cm^-2；240keV，4e¹¹cm^-2；180keV，3e¹¹cm^-2The injection operation is carried out, the activation treatment is carried out by adopting a high-vacuum high-temperature annealing furnace, the treatment temperature is preferably 1690-1730 ℃, 1700 ℃ is selected in the embodiment, the treatment time is preferably 26-33 min, and 30min is selected in the embodiment.

Go toThe depth of the JFET buried layer type doped region is 0.2-0.4 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.6 mu m, and the ion implantation concentration of the JFET buried layer type doped region 107 is 5e¹⁶～1e¹⁷ cm^-3. Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the JFET buried layer type doped region is selected to be 0.3 μm below the surface of the epitaxial layer, the depth range is 0.4 μm, and the ion implantation concentration of the JFET doped region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶cm^-3In this embodiment, 7e is selected¹⁶ cm^-3. In fact, most SiC MOSFETs in the prior art basically stay in the conventional planar gate stage, while the present application innovatively improves the existing device structure and comprehensively considers the effects of doping concentration and doping range (lateral and longitudinal), which all cause different device performances and even reduce the device performance, and it is difficult to find a suitable device structure which simultaneously reduces the resistance and the electric field strength in the gate oxide.

As shown in S5 of fig. 1 and fig. 8 to 13, step S5 is performed to form a gate structure 120 on the surface of the epitaxial layer 103, the gate structure 120 at least covers the JFET buried layer type doped region 107, and a surface passivation layer 112 is deposited on the surface of the gate structure, wherein a first window 116 corresponding to the gate structure 120 is formed in the surface passivation layer 112, and the thickness of the surface passivation layer 112 is 0.8 to 1.5 μm.

As an example, in step S5, the specific steps of forming the gate structure 120 and the surface passivation layer 112 include:

s5-1, forming a gate dielectric material layer 108 on the surface of the epitaxial layer by adopting a dry thermal oxidation technology;

s5-2, forming a polysilicon layer 109 on the surface of the gate dielectric material layer;

s5-3, forming a surface passivation material layer 110 on the surface of the polysilicon layer 109 and the exposed gate dielectric material layer;

s5-4 etches the surface passivation material layer 110 and the gate dielectric material layer 108 to expose at least the second windows 113 corresponding to the source regions 105 and form the gate structures 120 and the surface passivation layer 112.

Specifically, in the present application, a gate dielectric material layer 108 is formed on the surface of the epitaxial layer by using a dry thermal oxidation technique, and the material of the gate dielectric material layer 108 includes, but is not limited to, silicon dioxide, and the thickness thereof is 50 to 80nm, preferably 60 to 70nm, and in this embodiment, is 65 nm. In addition, a layer of SiO is deposited on the surface of the device by adopting PECVD or LPCVD technology₂As surface passivation layer, SiO₂The thickness of (A) is 0.6-1.0 μm, preferably 0.7-0.9 μm, and in this embodiment is selected to be 0.8 μm, but the material of the surface passivation material layer may also be other passivation materials known to those skilled in the art. Further, after the surface passivation material layer 110 and the gate dielectric material layer 108 are etched, preferably, the width of the polysilicon layer 109 is smaller than the width of the gate dielectric layer 111, the width of the surface passivation layer 112 is equal to the width of the gate dielectric layer 111, the surface passivation layer 112 and the gate dielectric layer 111 cover the polysilicon layer 109, and in this embodiment, the gate dielectric layer 111 completely covers the JFET doping region and extends to the well region to contact with the edge of the source region 105 near the inner side of the well region, in addition, the second window 113 may correspond to the source region 105, and preferably, the second window 113 corresponds to the source region and the contact region.

As an example, between step S5 and step S6, a source ohmic contact metal layer 114 is formed on the surface of the source region 105 and the contact region 106, and a drain ohmic contact metal layer 115 is formed on the second surface of the substrate 101.

Specifically, the method further comprises the step of forming a source ohmic contact metal layer and a drain ohmic contact metal layer, and further, the source ohmic contact metal layer 114 and the drain ohmic contact metal layer 115 respectively comprise a Ti layer, a Ni layer and an Au layer which are sequentially stacked from bottom to top, so that the contact resistance can be reduced, and the electrical connection characteristics of the electrodes can be optimized. Preferably, the step of forming the first window 116 in the surface passivation layer 112 is performed after forming the source ohmic contact metal layer 115, so that the device structure can be effectively protected and the stability of the device can be ensured.

As shown in S6 of fig. 1 and fig. 14, step S6 is performed to form a gate metal electrode 118 electrically connected to the gate structure 120 in the first window 116, form a source metal electrode 117 on the surface of the source region 105, and form a drain metal electrode 119 on the second surface of the substrate 101.

Specifically, contact electrodes are formed on the gate structure 116, the source region 105 and the second surface 1012 of the substrate 101 to complete the preparation of the whole device, wherein preferably, the source region metal electrode 117 forms the surface of the source region 105 and the contact region 106, and in addition, the material of the gate metal electrode 118, the source region metal electrode 117 and the drain region metal electrode 119 is any material known to those skilled in the art, and is not limited thereto.

As shown in fig. 14, the present invention further provides a SiC MOSFET power device, wherein the SiC MOSFET power device prepared by any one of the above preparation methods includes:

a heavily doped substrate 101 of a first doping type having a first surface 1011 and a second surface 1012;

an epitaxial layer 103 lightly doped with a first doping type on a first surface 1011 of the substrate 101;

a JFET buried layer type doped region 107 doped with the first doping type and formed in the epitaxial layer 103;

a well region 104 doped with the second doping type, formed in the epitaxial layer 103 and surrounding the JFET buried doped region 107;

a source region 105 with a heavy doping of the first doping type, which is positioned in the well region 104 and surrounds the JFET doping region 107;

a contact region 106 with a heavily doped second doping type, located in the well region 104 and surrounding the source region 105;

the gate structure is positioned on the surface of the JFET buried layer type doped region 107;

a gate metal electrode 118, a source metal electrode 117, and a drain metal electrode 119, the gate metal electrode 118 electrically connected to the gate structure 120, the source metal electrode 117 electrically connected to at least the source region 105, and the drain metal electrode 119 electrically connected to the second surface 1012 of the substrate 101.

As an example, the material of epitaxial layer 103 is 4H-SiC, and the crystal orientation of substrate 101 is deviated by (4 + -0.5) ° tilt angle from the (11-20) direction.

Illustratively, a buffer layer 102 is further included between the substrate 101 and the epitaxial layer 103.

As an example, the first doping type is N-type doping, and the second doping type is P-type doping; the depth of the contact region is greater than that of the source region and less than that of the well region.

In addition, an epitaxial layer 103 is formed on any surface of the substrate 101, such as the first surface 1011 in this embodiment, wherein the doping type of the epitaxial layer 103 is selected to be the same as the doping type of the substrate 101, but the epitaxial layer is a lightly doped material layer (i.e., an N-type epitaxial layer) whose material is a semiconductor substrate containing a silicon carbide (SiC) material, in this embodiment 4H-SiC is selected.

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate and the epitaxial layer, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and is selected to be 0.7 μm in this embodiment.

As an example, the surface of the gate structure 120 further includes a surface passivation layer 112, and the thickness of the surface passivation layer 112 is 0.8-1.5 μm.

In particular, the material of the surface passivation layer 112 includes, but is not limited to, SiO₂And SiO₂Has a thickness of 0.6 to 1.0 μm, preferably 0.7 to 0.9 μm, in the present embodiment, SiO₂The thickness of (2) is 0.8. mu.m. In addition, the surface passivation layer 112 has a first window 116 thereon, and the gate metal electrode 118 is electrically connected to the gate structure 120 through the first window.

By way of example, JFThe depth of the ET buried layer type doped region is 0.2-0.4 μm below the surface of the epitaxial layer, the depth range is 0.3-0.6 μm, and the ion implantation concentration of the JFET buried layer type doped region 107 is 5e¹⁶～1e¹⁷ cm^-3。

Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the JFET buried layer type doped region is selected to be 0.3 μm below the surface of the epitaxial layer, the depth range is 0.4 μm, and the ion implantation concentration of the JFET doped region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶ cm^-3In this embodiment, 7e is selected¹⁶ cm^-3. It should be noted that the invention optimizes the device structure, and particularly, after ion implantation (such as N-type ion implantation) is performed in the JFET region of the conventional planar gate silicon carbide MOSFET power device, a JFET buried layer type doped region is formed, so that the resistance of the JFET region is reduced, and simultaneously, the electric field intensity in the gate oxide can be reduced, and the breakdown of the JFET region is avoided.

By way of example, a source ohmic contact metal layer 114 and a drain ohmic contact metal layer 115 are further included, the source ohmic contact metal layer 115 is located on the surface of the source region 105 and the contact region 106 and is located below the source metal electrode 117, and the drain ohmic contact metal layer 115 is located between the second surface 1012 of the substrate 101 and the drain metal electrode 119.

Specifically, the source ohmic contact metal layer 114 and the drain ohmic contact metal layer 115 each include a Ti layer, a Ni layer, and an Au layer stacked in this order from bottom to top, so that contact resistance can be reduced, and electrical connection characteristics of the electrodes can be optimized.

Specifically, the doping type of the source region 105 is opposite to that of the well region 104, and is selected to be N-type heavily doped in this embodiment, the doping type of the contact region 106 is the same as that of the well region, and is selected to be P-type heavily doped in this embodiment, the contact region 106 is used to form a body diode, release the reverse current in the device, and the holes are released, preferably contact region 106 is in contact with source region 105, and the upper surfaces of the guard and source regions are both flush with the upper surface of the epitaxial layer, in addition, the depth of the source region 105 is 0.2-0.5 μm, the depth of the contact region 106 is 0.5-0.8 μm, in this embodiment, the depth of source region 105 is 0.3 μm, the depth of contact region 106 is 0.7 μm, the depth of contact region 106 is greater than the depth of source region 105, therefore, the reverse voltage-resistant capability of the device can be enhanced, and the voltage-resistant capability of the device is further improved along with the increase of the depth of the contact region 106 in a certain range. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.7 μm.

In summary, the present invention provides a method for manufacturing a silicon carbide MOSFET power device, comprising the following steps: s1, providing a substrate with a heavy doping of the first doping type, wherein the substrate is provided with a first surface and a second surface, and an epitaxial layer with a light doping of the first doping type is formed on the first surface; s2, defining a JFET area in the epitaxial layer, and doping the second doping type in the epitaxial layer surrounding the JFET area to form a well region; s3 heavily doping the well region with the first doping type to form a source region surrounding the JFET region, and heavily doping the well region surrounding the source region with the second doping type to form a contact region; s4, doping the JFET region with a first doping type to form a JFET buried layer type doping region; s5, forming a gate structure on the surface of the epitaxial layer, wherein the gate structure at least covers the JFET buried layer type doped region, and depositing a surface passivation layer on the surface of the gate structure, wherein a first window corresponding to the gate structure is formed in the surface passivation layer; s6 forming a gate metal electrode electrically connected to the gate structure in the first window, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate. Through the technical scheme, the structure of the device is optimized, particularly, after ion implantation (such as N-type ion implantation) is carried out in a JFET (junction field effect transistor) area of a conventional planar gate silicon carbide MOSFET (metal oxide semiconductor field effect transistor) power device, a JFET buried layer type doped area is formed, the resistance of the JFET area is reduced, and meanwhile, the electric field intensity in gate oxide can be reduced, and the breakdown of the JFET area is avoided; the device structure and the preparation process are simple, the effect is obvious, and the silicon carbide MOSFET power device structure and the preparation method have wide application prospects. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

Example 2:

as an example, the first doping type is P-type doping and the second doping type is N-type doping.

Specifically, a semiconductor substrate is provided and ion-doped with a first doping type, which may be N-type or P-type, and is selected to be P-type in this embodiment and heavily doped, i.e., P + -type semiconductor substrate, and is defined to have a first surface and a second surface, in this embodiment, the upper surface is defined as the first surface, and the back surface of the substrate is defined as the second surface. In addition, the material of the substrate 101 may be a semiconductor substrate containing a silicon carbide (SiC) material, both of which are selected to be 4H — SiC in the present embodiment, and further, the substrate 101 is off-oriented by (4 ± 0.5) ° tilt in the (11-20) direction.

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate 101 and the epitaxial layer 103, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment, is selected to be 0.6 μm.

specifically, the purpose of this step is to form a well region 104, which has a doping type different from that of the epitaxial layer 103, and in this embodiment is chosen to form an N-type well region. In addition, the inner side of the well region 104 and the JFET region are preferably in contact, but in other embodiments, the two regions may have a predetermined distance therebetween, and the shape of the well region 104 is a ring, and may be a circular ring or a square ring, and in this embodiment, is selected to be a square ring.

Specifically, in this step, a source region and a contact region are formed in the well region 104, wherein the doping type of the source region 105 is opposite to that of the well region 104, P-type heavy doping is selected in this embodiment, the doping type of the contact region 106 is the same as that of the well region, N-type heavy doping is selected in this embodiment, the contact region 106 is used to form a body diode, release reverse current in the device, and release holes, preferably, the contact region 106 is in contact with the source region 105, and the upper surfaces of the contact region and the source region are both flush with the upper surface of the epitaxial layer, further, the depth of the source region 105 is 0.2 μm to 0.5 μm, the depth of the contact region 106 is 0.5 μm to 0.8 μm, in this embodiment, the depth of the source region 105 is 0.2 μm, the depth of the contact region 106 is 0.5 μm, the depth of the contact region 106 is greater than that of the source region 105, so that the reverse withstand voltage capability, the voltage endurance of the device is further improved. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.6 μm.

specifically, in the present application, doping of the same doping type as that of the epitaxial layer is performed in the JFET region in the well region 104, which is P-type ion implantation in this embodiment, it should be noted that the present invention optimizes the device structure, and particularly, after ion implantation is performed in the JFET region of the conventional planar gate silicon carbide MOSFET power device, a JFET buried layer type doping region is formed, so that the resistance of the JFET region is reduced, and at the same time, the electric field strength in the gate oxide can be reduced, thereby avoiding breakdown thereof.

Specifically, in the specific step of forming the JFET buried layer doped region 107, an implantation mask layer of a material including, but not limited to, SiO, is deposited on the surface of the epitaxial layer 103 by a chemical vapor deposition technique (e.g., PECVD, LPCVD)₂(ii) a Secondly, forming an injection mask layer on the surface of the injection shielding layer, in the embodiment, photoresist is used as the injection mask layer, namely, photoresist is coated on the surface of the injection shielding layer, then exposure, development and hardening processes are carried out on the photoresist to form an injection mask pattern, and the injection mask pattern covers the position of the well region 104 or extends to the inner side of the well region 104; then, ion implantation is performed by using the implantation mask pattern as an implantation mask, and the implantation shielding layer is used as ion implantationThe thickness of the injected shielding layer is 30-50 nm, preferably 36-39 nm, in the embodiment, 39nm is selected for reducing the ion channel effect of the MOSFET device; then, after ion implantation, removing the photoresist layer and the implantation shielding layer; and finally, activating the implanted ions by a high-vacuum high-temperature annealing furnace to obtain a final JFET buried layer type doped region with the same doping type as the epitaxial layer.

Specifically, the ion doping can be performed by multiple ion implantations, the implantation times are determined according to actual requirements, wherein in different implantation times, each implantation energy is selected from 150-450 keV, and each implantation dosage is selected from 3e¹¹～8e¹¹cm^-2Further, the implantation energy is preferably 160 to 180keV or 200 to 250keV, and the implantation dose is preferably 3e¹¹～5e¹¹cm^-2Or the implantation dose is preferably 4e¹¹～5e¹¹cm^-2In this embodiment, the implantation times are 5 times, the first implantation energy is 500keV, and the implantation dose is 9e¹¹ cm^-2；410keV，7e¹¹ cm^-2(ii) a 350keV, 6e¹¹ cm^-2；260keV，6e¹¹cm^-2；160keV，2e¹¹ cm^-2The injection operation is carried out, the activation treatment is carried out by adopting a high-vacuum high-temperature annealing furnace, the treatment temperature is preferably 1690-1730 ℃, 1700 ℃ is selected in the embodiment, the treatment time is preferably 26-33 min, and 30min is selected in the embodiment.

Furthermore, the depth of the JFET buried layer type doped region is 0.2-0.4 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.6 mu m, and the ion implantation concentration of the JFET buried layer type doped region 107 is 5e¹⁶～1e¹⁷ cm^-3. Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the JFET buried layer type doped region is selected to be 0.2 μm below the surface of the epitaxial layer, the depth range is 0.3 μm, and the ion implantation concentration of the JFET doped region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶cm^-3In this embodiment, 8e is selected¹⁶ cm^-3. In fact, most SiC MOSFETs in the prior art basically stay in the conventional planar gate stage, while the present application innovatively improves the existing device structure and comprehensively considers the effects of doping concentration and doping range (lateral and longitudinal), which all cause different device performances and even reduce the device performance, and it is difficult to find a suitable device structure which simultaneously reduces the resistance and the electric field strength in the gate oxide.

Specifically, in the present application, a gate dielectric material layer 108 is formed on the surface of the epitaxial layer by using a dry thermal oxidation technique,the material of the gate dielectric material layer 108 includes, but is not limited to, silicon dioxide, and the thickness thereof is 50 to 80nm, preferably 60 to 70nm, and in the present embodiment, 60nm is selected. In addition, a layer of SiO is deposited on the surface of the device by adopting PECVD or LPCVD technology₂As surface passivation layer, SiO₂The thickness of (A) is 0.6 to 1.0 μm, preferably 0.7 to 0.9 μm, and in the present embodiment, 0.7 μm is selected. Of course, the material of the surface passivation layer may also be other passivation materials known to those of ordinary skill in the art. Further, after the surface passivation material layer 110 and the gate dielectric material layer 108 are etched, preferably, the width of the polysilicon layer 109 is smaller than the width of the gate dielectric layer 111, the width of the surface passivation layer 112 is equal to the width of the gate dielectric layer 111, the surface passivation layer 112 and the gate dielectric layer 111 cover the polysilicon layer 109, and in this embodiment, the gate dielectric layer 111 completely covers the JFET doping region and extends to the well region to contact with the edge of the source region 105 near the inner side of the well region, in addition, the second window 113 may correspond to the source region 105, and preferably, the second window 113 corresponds to the source region and the contact region.

In addition, an epitaxial layer 103 is formed on any surface of the substrate 101, such as the first surface 1011 in this embodiment, wherein the doping type of the epitaxial layer 103 is selected to be the same as the doping type of the substrate 101, but the epitaxial layer is a lightly doped material layer (i.e., a P-type epitaxial layer) whose material is a semiconductor substrate containing a silicon carbide (SiC) material, in this embodiment 4H-SiC is selected.

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate and the epitaxial layer, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment, is selected to be 0.6 μm.

In particular, the material of the surface passivation layer 112 includes, but is not limited to, SiO₂And SiO₂Has a thickness of 0.6 to 1.0 μm, preferably 0.7 to 0.9 μm, in the present embodiment, SiO₂The thickness of (2) is 0.7. mu.m. In addition, the surface passivation layer 112 has a first window 116 thereon, and the gate metal electrode 118 is electrically connected to the gate structure 120 through the first window.

For example, the depth of the JFET buried layer type doped region is 0.2-0.4 μm below the surface of the epitaxial layer, the depth range is 0.3-0.6 μm, and the ion implantation concentration of the JFET buried layer type doped region 107 is 5e¹⁶～1e¹⁷ cm^-3。

Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the JFET buried layer type doped region is selected to be 0.2 μm below the surface of the epitaxial layer, the depth range is 0.3 μm, and the ion implantation concentration of the JFET doped region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶ cm^-3In this embodiment, 8e is selected¹⁶ cm^-3. It should be noted that the invention optimizes the device structure, and particularly, after ion implantation (such as N-type ion implantation) is performed in the JFET region of the conventional planar gate silicon carbide MOSFET power device, a JFET buried layer type doped region is formed, so that the resistance of the JFET region is reduced, and simultaneously, the electric field intensity in the gate oxide can be reduced, and the breakdown of the JFET region is avoided.

Specifically, the doping type of the source region 105 is opposite to that of the well region 104, and is selected to be P-type heavily doped in this embodiment, the doping type of the contact region 106 is the same as that of the well region, and is selected to be N-type heavily doped in this embodiment, the contact region 106 is used to form a body diode, release the reverse current in the device, and the holes are released, preferably contact region 106 is in contact with source region 105, and the upper surfaces of the guard and source regions are both flush with the upper surface of the epitaxial layer, in addition, the depth of the source region 105 is 0.2-0.5 μm, the depth of the contact region 106 is 0.5-0.8 μm, in this embodiment, the depth of source region 105 is 0.2 μm, the depth of contact region 106 is 0.5 μm, the depth of contact region 106 is greater than the depth of source region 105, therefore, the reverse voltage-resistant capability of the device can be enhanced, and the voltage-resistant capability of the device is further improved along with the increase of the depth of the contact region 106 in a certain range. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.6 μm.

Example 3:

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate 101 and the epitaxial layer 103, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment, is selected to be 0.8 μm.

Specifically, in this step, a source region and a contact region are formed in the well region 104, wherein the doping type of the source region 105 is opposite to that of the well region 104, N-type heavy doping is selected in this embodiment, the doping type of the contact region 106 is the same as that of the well region, P-type heavy doping is selected in this embodiment, the contact region 106 is used to form a body diode, release reverse current in the device, and release holes, preferably, the contact region 106 is in contact with the source region 105, and the upper surfaces of the contact region and the source region are both flush with the upper surface of the epitaxial layer, further, the depth of the source region 105 is 0.2 μm to 0.5 μm, the depth of the contact region 106 is 0.5 μm to 0.8 μm, in this embodiment, the depth of the source region 105 is 0.8 μm, the depth of the contact region 106 is greater than that of the source region 105, so that the reverse withstand voltage capability of the device can be enhanced, and the depth of the contact region, the voltage endurance of the device is further improved. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.7 μm.

Specifically, in the specific step of forming the JFET buried layer doped region 107, an implantation mask layer of a material including, but not limited to, SiO, is deposited on the surface of the epitaxial layer 103 by a chemical vapor deposition technique (e.g., PECVD, LPCVD)₂(ii) a Secondly, forming an injection mask layer on the surface of the injection shielding layer, in the embodiment, photoresist is used as the injection mask layer, namely, photoresist is coated on the surface of the injection shielding layer, then exposure, development and hardening processes are carried out on the photoresist to form an injection mask pattern, and the injection mask pattern covers the position of the well region 104 or extends to the inner side of the well region 104; then, carrying out ion implantation by taking the implantation mask pattern as an implantation mask, and meanwhile, taking the implantation shielding layer as a shielding layer for ion implantation, wherein the thickness of the implantation shielding layer is 30-50 nm, preferably 36-39 nm, and is selected to be 36nm in the embodiment, so that the ion channel effect of the MOSFET device is reduced; and then, after the ion implantation is carried out,removing the photoresist layer and the injection shielding layer; and finally, activating the implanted ions by a high-vacuum high-temperature annealing furnace to obtain a final JFET buried layer type doped region with the same doping type as the epitaxial layer.

Specifically, the ion doping can be performed by multiple ion implantations, the implantation times are determined according to actual requirements, wherein in different implantation times, each implantation energy is selected from 150-450 keV, and each implantation dosage is selected from 3e¹¹～8e¹¹cm^-2Further, the implantation energy is preferably 160 to 180keV or 200 to 250keV, and the implantation dose is preferably 3e¹¹～5e¹¹cm^-2Or the implantation dose is preferably 4e¹¹～5e¹¹cm^-2In this embodiment, the implantation times are 3 times, the first implantation energy is 400keV, and the implantation dose is 8e¹¹ cm^-2(ii) a Accordingly, 300keV, 5e¹¹ cm^-2；190keV，5e¹¹cm^-2The injection operation is carried out, the activation treatment is carried out by adopting a high-vacuum high-temperature annealing furnace, the treatment temperature is preferably 1690-1730 ℃, 1700 ℃ is selected in the embodiment, the treatment time is preferably 26-33 min, and 30min is selected in the embodiment.

Furthermore, the depth of the JFET buried layer type doped region is 0.2-0.4 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.6 mu m, and the ion implantation concentration of the JFET buried layer type doped region 107 is 5e¹⁶～1e¹⁷ cm^-3. Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the buried doped region of the JFET is selected to be 0.4 μm below the surface of the epitaxial layer and in the range of 0.6 μm, JThe concentration of ion implantation of the FET doped region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶cm^-3In this embodiment, 6e is selected¹⁶ cm^-3. In fact, most SiC MOSFETs in the prior art basically stay in the conventional planar gate stage, while the present application innovatively improves the existing device structure and comprehensively considers the effects of doping concentration and doping range (lateral and longitudinal), which all cause different device performances and even reduce the device performance, and it is difficult to find a suitable device structure which simultaneously reduces the resistance and the electric field strength in the gate oxide.

Specifically, in the present application, a gate dielectric material layer 108 is formed on the surface of the epitaxial layer by using a dry thermal oxidation technique, and the material of the gate dielectric material layer 108 includes, but is not limited to, silicon dioxide, and the thickness thereof is 50 to 80nm, preferably 60 to 70nm, and in this embodiment, 70nm is selected. In addition, a layer of SiO is deposited on the surface of the device by adopting PECVD or LPCVD technology₂As surface passivation layer, SiO₂The thickness of the film is 0.6 to 1.0 μm,preferably 0.7 to 0.9 μm, and in the present embodiment, 0.9 μm is selected. Of course, the material of the surface passivation layer may also be other passivation materials known to those of ordinary skill in the art. Further, after the surface passivation material layer 110 and the gate dielectric material layer 108 are etched, preferably, the width of the polysilicon layer 109 is smaller than the width of the gate dielectric layer 111, the width of the surface passivation layer 112 is equal to the width of the gate dielectric layer 111, the surface passivation layer 112 and the gate dielectric layer 111 cover the polysilicon layer 109, and in this embodiment, the gate dielectric layer 111 completely covers the JFET doping region and extends to the well region to contact with the edge of the source region 105 near the inner side of the well region, in addition, the second window 113 may correspond to the source region 105, and preferably, the second window 113 corresponds to the source region and the contact region.

Further, preferably, a buffer layer 102 is formed between the substrate 101 and the epitaxial layer 103 for better matching between the substrate and the epitaxial layer, and the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment, is selected to be 0.8 μm.

In particular, the material of the surface passivation layer 112 includes, but is not limited to, SiO₂And SiO₂Has a thickness of 0.6 to 1.0 μm, preferably 0.7 to 0.9 μm, in the present embodiment, SiO₂The thickness of (2) was 0.9. mu.m. In addition, the surface passivation layer 112 has a first window 116 thereon, and the gate metal electrode 118 is electrically connected to the gate structure 120 through the first window.

Specifically, the depth of the JFET buried layer type doped region is preferably 0.25-0.35 mu m below the surface of the epitaxial layer, and the depth range is preferably 0.4-0.5 mu m. In this embodiment, the depth of the buried doped region of the JFET is selected to be 0.4 μm below the surface of the epitaxial layerThe depth range is 0.6 μm, and the ion implantation concentration of the JFET doping region is 5e¹⁶～1e¹⁷ cm^-3Preferably 6e¹⁶～8e¹⁶ cm^-3In this embodiment, 6e is selected¹⁶ cm^-3. It should be noted that the invention optimizes the device structure, and particularly, after ion implantation (such as N-type ion implantation) is performed in the JFET region of the conventional planar gate silicon carbide MOSFET power device, a JFET buried layer type doped region is formed, so that the resistance of the JFET region is reduced, and simultaneously, the electric field intensity in the gate oxide can be reduced, and the breakdown of the JFET region is avoided.

Specifically, the doping type of the source region 105 is opposite to that of the well region 104, and is selected to be N-type heavily doped in this embodiment, the doping type of the contact region 106 is the same as that of the well region, and is selected to be P-type heavily doped in this embodiment, the contact region 106 is used to form a body diode, release the reverse current in the device, and the holes are released, preferably contact region 106 is in contact with source region 105, and the upper surfaces of the guard and source regions are both flush with the upper surface of the epitaxial layer, in addition, the depth of the source region 105 is 0.2-0.5 μm, the depth of the contact region 106 is 0.5-0.8 μm, in this embodiment, the depth of source region 105 is 0.5 μm, the depth of contact region 106 is 0.8 μm, the depth of contact region 106 is greater than the depth of source region 105, therefore, the reverse voltage-resistant capability of the device can be enhanced, and the voltage-resistant capability of the device is further improved along with the increase of the depth of the contact region 106 in a certain range. Further, a predetermined distance is provided between the source region 105 and the well region 104, and the distance between the inner side wall of the source region 105 and the inner side wall of the well region 104 is 0.5 to 1 μm, preferably 0.6 to 0.8 μm, and in this embodiment is 0.8 μm.

The above is only a preferred embodiment of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims

1. A preparation method of a silicon carbide MOSFET power device is characterized by comprising the following steps:

2. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: when the first doping type is N type, the second doping type is P type; and when the first doping type is P type, the second doping type is N type.

3. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in step S3, the depth of the contact region is greater than the depth of the source region, and the depth of the contact region is less than the depth of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

4. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in the step S4, the forming the JFET buried layer type doped region includes the following steps:

5. The method of manufacturing a silicon carbide MOSFET power device of claim 4, wherein: in the step S4-1, the thickness of the injection shielding layer is 30-50 nm; in the step S4-3, the number of times of ion implantation is 3-5, the implantation energy is 150-450 keV, and the implantation dose is 3e¹¹～8e¹¹cm^-2(ii) a In the step S4-4, the temperature of the activation treatment is 1650-1750 ℃, and the time of the activation treatment is 20-40 min.

6. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in step S5, the forming of the gate structure and the surface passivation layer includes the following steps:

7. A silicon carbide MOSFET power device, comprising:

a lightly doped epitaxial layer of a first doping type on a first surface of the substrate;

the source region is heavily doped with the first doping type, is positioned in the well region and surrounds the JFET buried layer type doping region;

a gate metal electrode;

a source metal electrode;

a drain metal electrode;

the source region is in ohmic contact with the metal layer;

the drain region is in ohmic contact with the metal layer;

8. The silicon carbide MOSFET power device of claim 7, wherein: when the first doping type is N type, the second doping type is P type; and when the first doping type is P type, the second doping type is N type.

9. The silicon carbide MOSFET power device of claim 7, wherein: the depth of the JFET buried layer type doped region is 0.2-0.3 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.5 mu m, and the ion doping concentration of the JFET buried layer type doped region is 5e¹⁶～1e¹⁷cm^-3。

10. The silicon carbide MOSFET power device of claim 7, wherein: the depth of the contact region is greater than that of the source region and less than that of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.