JP3436220B2 - Vertical semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical semiconductor device.

[0002]

BACKGROUND ART Power MOS (Metal Oxide Semiconducto)
r) A field effect transistor is a kind of semiconductor device used for power conversion and power control of, for example, household electric appliances and motors of automobiles. FIG. 11 is a sectional view showing a general structure of a power MOS field effect transistor. Such a power MOS field effect transistor is, for example,
"Transistor technology SPECI" published by CQ Publishing Co., Ltd.
AL No. 54 "on page 31. The power MOS field effect transistor will be described below.

Power MOS field effect transistor 500
Includes a gate electrode 550, an n ⁺ type drain region 510 and n ⁺ type source regions 540a and 540b.

An n ⁻ type silicon region 520 is located on the n ⁺ type drain region 510. A p-type silicon region 530a and a p-type silicon region 530b are located in the n ⁻ type silicon region 520. A predetermined space is provided between the p-type silicon region 530a and the p-type silicon region 530b. The n ⁻ type silicon region 520 located at this distance is referred to as a region A. The p-type silicon region 530a and the n ⁻ -type silicon region 520 form a pn junction 580a. Further, the p-type silicon region 530b and the n ⁻ type silicon region 520 form a pn junction 580b.

P-type silicon region 530a, p-type silicon
In the area 530b, n ⁺Mold source region 54
0a, n⁺The mold source region 540b is located. p type
N in the silicon region 530a⁺Mold source region 540
a and n^-Region located between the mold silicon region 520
Is a region B. In addition, in the p-type silicon region 530b
Of which n⁺Mold source regions 540b and n^-Type silicon region 5
A region located between the two and 20 is referred to as a region C.

A gate electrode 550 covered with an insulating layer 560 is located on the regions A, B and C.
A conductive layer 570 is positioned so as to cover the gate electrode 550. The conductive layer 570 includes an n ⁺ type source region 540a,
540b and p-type silicon regions 530a and 530b.

Next, the operation of the power MOS field effect transistor 500 will be described. First, the ON operation of the power MOS field effect transistor 500 will be described. n ⁺
A positive voltage is applied to the mold drain region 510.
The n ⁺ type source regions 540a and 540b are grounded. The p-type silicon regions 530a and 530b are grounded. When a positive voltage is applied to the gate electrode 550 in this state, the electrons in the p-type silicon regions 530a and 530b gather in the regions B and C, respectively, and an n-type channel is formed. As a result, the n ⁺ type source region 54
The electrons supplied from 0a and 540b are n-type channels,
Flowing through the n ⁻ type silicon region 520, the n ⁺ type drain region 5
Reach 10. In other words, power MOS field-effect transistor 500 from the n ⁺ -type drain region 510 n ⁺ -type source region 540a, an operation to flow a current to 540b.

Next, the OFF operation of the power MOS field effect transistor 500 will be described. Gate electrode 550
When n is changed from a positive voltage to a negative voltage or it is grounded, the n-type channel disappears. Accordingly, the power MOS field effect transistor 500 from the n ⁺ -type drain region 510 n ⁺ -type source region 540a, an operation of not current flows to 540b.

By the way, when the power MOS field effect transistor 500 is OFF, the n ⁺ type source region 540a,
It is due to the depletion layer that no current flows between 540b and the n ⁺ type drain region 510. That is, at the time of OFF, the depletion layer spreads from the pn junctions 580a and 580b into the p-type silicon regions 530a and 530b and the n ⁻ -type silicon region 520. This depletion layer serves as the n ⁺ type source regions 540a and 540b and the n ⁺ type drain region 51.
It prevents the current from flowing between 0 and it.

However, the n ⁺ type source regions 540a, 54
When the potential difference between 0b and the n ⁺ type drain region 510 exceeds a certain value, the power MOS field effect transistor 50
0 causes avalanche breakdown or dielectric breakdown, which causes a current to flow between the n ⁺ type source regions 540a and 540b and the n ⁺ type drain region 510.

The upper limit of the voltage at which the power MOS field effect transistor does not cause avalanche breakdown or dielectric breakdown is called the breakdown voltage of the power MOS field effect transistor.
More specifically, the following examples are used to define the breakdown voltage of the power MOS field effect transistor. The breakdown voltage of a power MOS field effect transistor is a drain voltage when a current of 10 mA or more flows between the drain region and the source region by grounding the gate electrode and the source region and applying a voltage to the drain region. is there.

[0012]

Since the power MOS field effect transistor is used for electric power, it has to have a high breakdown voltage. Further, in order to reduce the power consumption of the power MOS field effect transistor, it is necessary to lower the resistance of the power MOS field effect transistor during ON operation. As described above, the power MOS field effect transistor is required to have high withstand voltage and low resistance during ON operation.

The breakdown voltage can be improved by taking the power MOS field effect transistor 500 shown in FIG. 11 as an example, by lowering the n-type impurity concentration of the n ^-- type silicon region 520. That is, when the n ⁻ -type silicon region 520 has a low n-type impurity concentration, the depletion layer spreads widely, so that the breakdown voltage of the power MOS field effect transistor 500 is improved.

On the other hand, it is n
^This is achieved by increasing the n-type impurity concentration of the -type silicon region 520. That is, the n ⁻ type silicon region 52
When the n-type impurity concentration of 0 is increased, the resistance of the n ⁻ -type silicon region 520 is lowered, so that the resistance at the time of ON operation is lowered.

As described above, in the power MOS field effect transistor, there is a problem that the resistance during ON operation increases when trying to improve the breakdown voltage, and the breakdown voltage decreases when trying to decrease the resistance during ON operation.

An object of the present invention is to suppress a decrease in breakdown voltage,
An object of the present invention is to provide a vertical semiconductor device capable of reducing the resistance during ON operation.

Another object of the present invention is to provide a vertical semiconductor device capable of increasing the breakdown voltage while lowering the resistance during ON operation.

[0018]

According to the present invention, there is provided a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type and a fourth semiconductor region of the first conductivity type. A vertical semiconductor device having a semiconductor region, wherein the first semiconductor region emits carriers of the first conductivity type, and the second semiconductor region serves as a path through which carriers of the first conductivity type flow. The second semiconductor region includes a high-concentration region having a high first-conductivity-type impurity concentration and a low-concentration region having a low first-conductivity-type impurity concentration, and the third semiconductor region is joined to the second semiconductor region. The fourth semiconductor region is a vertical semiconductor device that absorbs carriers of the first conductivity type.

According to the present invention having the above structure, it is possible to reduce the resistance during ON operation while suppressing the decrease in breakdown voltage. That is, the second semiconductor region of the present invention includes a high-concentration region having a high first-conductivity-type impurity concentration and a low-concentration region having a low first-conductivity-type impurity concentration. Since the high-concentration region of the second semiconductor region has a relatively high first-conductivity-type impurity concentration, its resistance is low. Therefore, the resistance during ON operation of the vertical semiconductor device can be reduced accordingly.
On the other hand, in the low-concentration region of the second semiconductor region, the first-conductivity-type impurity concentration is low, so that the depletion layer easily spreads in the second semiconductor region. Therefore, it is possible to prevent the breakdown voltage of the vertical semiconductor device from decreasing.

The present invention can have the following structures. That is, in the present invention, the third semiconductor region includes a high-concentration region having a high second-conductivity-type impurity concentration and a second high-concentration region.
And a low-concentration region having a low conductivity-type impurity concentration.

According to this, since the third semiconductor region includes the low concentration region of the second conductivity type having a low impurity concentration, the depletion layer easily spreads in the second semiconductor region. Therefore, the breakdown voltage of the vertical semiconductor device can be improved. There are, for example, the following three aspects of this structure.

In the first aspect of the present invention, the low-concentration region of the third semiconductor region is located between the high-concentration region of the third semiconductor region and the fourth semiconductor region. Furthermore, the semiconductor device further includes another semiconductor region of the first conductivity type, the other semiconductor region serves as a path for carriers of the first conductivity type, and the other semiconductor region is a low concentration region of the third semiconductor region. The vertical semiconductor device is located between the fourth semiconductor region and the other semiconductor region, and is joined to the low concentration region of the third semiconductor region.

A second aspect of the present invention is a vertical semiconductor device according to the present invention, wherein the low-concentration region of the third semiconductor region extends to the fourth semiconductor region.

A third aspect of the present invention is provided with another semiconductor region of the second conductivity type, wherein the other semiconductor region is
The second-conductivity-type impurity concentration is lower than that of the low-concentration region of the third semiconductor region, and the other semiconductor region is located between the low-concentration region of the third semiconductor region and the fourth semiconductor region. It is a vertical semiconductor device.

The present invention can have the following structure. That is, in the present invention, the third semiconductor region has a single-layer structure, and further includes another semiconductor region of the first conductivity type, and the other semiconductor region serves as a path through which carriers of the first conductivity type flow, The other semiconductor region is located between the third semiconductor region and the fourth semiconductor region,
The other semiconductor region is joined to the third semiconductor region.

The present invention can have the following structures. That is, in the present invention, the high concentration region of the second semiconductor region is in contact with the third semiconductor region, and the high concentration region of the second semiconductor region is in contact with the fourth semiconductor region.
If then, the low-concentration region of the second semiconductor region is located between said third semiconductor region and the fourth semiconductor region, a low concentration region of said second semiconductor region, the junction and the third semiconductor region is doing.

The present invention can have the following structures. That is, in the present invention, the high concentration region of the second semiconductor region is joined to the high concentration region of the third semiconductor region.

According to this, it becomes possible to reduce the resistance during the ON operation of the vertical semiconductor device. That is, the second
Since the high-concentration region of the semiconductor region and the high-concentration region of the third semiconductor region both have high impurity concentrations, the depletion layer is difficult to extend in these regions. Therefore, in these areas, JF
ET (Junction Field EffectT)
Since it is difficult to generate the transistor effect, the dimensions of these regions can be reduced. As a result, the vertical semiconductor device can be miniaturized, and the resistance during ON operation can be reduced.

The present invention can have the following structure. That is, in the present invention, the second semiconductor region is completely depleted when the vertical semiconductor device is in the OFF operation.

According to this, since the second semiconductor region is completely depleted, the breakdown voltage can be further improved.

As the vertical semiconductor device according to the present invention,
For example, there is a vertical MOS field effect transistor. In this case, the first semiconductor region is the source region. The second semiconductor region is a drift region. The third semiconductor region is a body region. The fourth semiconductor region is a drain region.

The present invention is an inverter circuit for converting DC power into AC power, including the vertical semiconductor device.
It is an inverter circuit.

Since the inverter circuit according to the present invention includes the vertical semiconductor device, it has low power consumption and can be used under high voltage conditions.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Device Structure} FIG. 1 is a sectional view of a power MOS field effect transistor 1 according to a first embodiment of the present invention. The power MOS field effect transistor 1 includes a gate electrode 24, n ⁺ type source regions 20a, 20b and n ^+.
A mold drain region 10 is included.

The n ⁺ type drain region 10 is formed on a silicon substrate. n ⁺ type drain region 10 has n
The type drift region 12a, the p type body region 14a, and the p ⁺ type body region 16a are sequentially stacked. This is referred to as a laminated portion 34. A pn junction 26a is formed by the n-type drift region 12a and the p-type body region 14a.

On the n ⁺ type drain region 10, an n type drift region 12b, ap type body region 14b, and ap ⁺ type body region 16b are sequentially stacked. This is referred to as a laminated portion 36. The laminated portion 36 is formed so as to be spaced apart from the laminated portion 34. N-type drift region 12b and p-type body region 14
The pn junction 26b is formed with b.

On the n ⁺ type drain region 10 and between the laminated portion 34 and the laminated portion 36, an n type drift region 18a and an n ⁺ type drift region 18b are laminated in order. The n-type impurity concentration in the n ⁺ -type drift region 18b is
It is higher than the n-type impurity concentration in the n-type drift region 18a.
Specific numerical values of the n-type impurity concentration in these regions will be described later.

The n-type drift region 18a and the p-type body region 14a form a pn junction 28a. The n-type drift region 18a and the p-type body region 14b have a pn
The joint portion 28b is formed. n ⁺ type drift region 1
8b and the p ⁺ type body region 16a, the pn junction 30a
Are formed. The n ⁺ type drift region 18b and the p ⁺ type body region 16b form a pn junction 30b.

In the p ⁺ type body region 16a and the p ⁺ type body region 16b, n ⁺ type source regions 20a and n ⁺ are respectively provided.
The mold source region 20b is located. A region A of the p ⁺ type body region 16a located between the n ⁺ type source region 20a and the n ⁺ type drift region 18b is referred to as a region A. p
^A region B of the ⁺ type body region 16b located between the n ⁺ type source region 20b and the n ⁺ type drift region 18b is referred to as a region B. The gate electrode 2 is formed on the regions A and B and the n ⁺ type drift region 18b with the gate oxide layer 22 interposed therebetween.
4 is located.

The power MOS field effect transistor 1 having the above structure may have the following structure. These can be applied to other embodiments described later.

In the power MOS field effect transistor 1, as shown in FIG. 1, the depth of the n ⁺ type drift region 18b is the same as the depth of the p ⁺ type body regions 16a and 16b. The depth of the n ⁺ type drift region 18b is p ⁺
It may be larger or smaller than the depth of the mold body regions 16a, 16b.

In the power MOS field effect transistor 1, the n ⁺ type drift region 18b is located above,
The n-type drift region 18a is located below. n-type drift region 18a is positioned above, n ⁺ -type drift region 18
b may be located below.

Instead of the gate oxide layer 22, another insulating layer such as a silicon nitride layer may be used.

The conductivity type of each region may be the opposite conductivity type. For example, the drain region, the source region and the drift region may be p-type and the body region may be n-type.

{Device operation} Next, this power MO
The operation of the S field effect transistor 1 will be described. First, the ON operation of the power MOS field effect transistor 1 will be described.

A positive voltage, for example, 0.1 V is applied to the n ⁺ type drain region 10. n ⁺ type source region 2
0a and 20b are grounded. p ⁺ type body region 1
6a, 16b and p-type body regions 14a, 14b are
It is grounded. In this state, when a positive voltage, for example, 5V is applied to the gate electrode 24, the electrons in the p ⁺ type body regions 16a and 16b gather in the regions A and B, respectively, and an n type channel is formed. This gives n ⁺
The electrons supplied from the mold source regions 20a and 20b are n
It flows through the type channel, the n ⁺ type drift region 18b, and the n type drift region 18a, and reaches the n ⁺ type drain region 10. Some electrons flow from the n-type drift region 18a through the n-type drift region 12a and reach the n ⁺ -type drain region 10. In addition, some electrons are generated in the n-type drift region 18a.
Flows from the n-type drift region 12b to the n ⁺ -type drain region 10. In other words, power MOS field-effect transistor 1 is of n ⁺ -type drain region 10 n ⁺ -type source region 20a, an operation to flow a current to 20b.

This power MOS field effect transistor 1
According to the above, it is possible to reduce the resistance during the ON operation. That is, since the n ⁺ type drift region 18b has a higher n type impurity concentration than the n type drift region 18a, the resistance of the n ⁺ type drift region 18b is lower than the resistance of the n type drift region 18a. Therefore, the resistance during the ON operation of the power MOS field effect transistor 1 can be reduced accordingly. As a result, the power consumption of the power MOS field effect transistor 1 can be reduced.

The power MOS field effect transistor 1 can also reduce the resistance during ON operation from the following points.
That is, in the power MOS field effect transistor 1, the n ⁺ type drift region 18b is the p ⁺ type body region 16
It is located between a and the p ⁺ type body region 16b, and is joined to these regions. n ⁺ type drift region 18b
Has a relatively high n-type impurity concentration. The p ⁺ type body regions 16a and 16b have a relatively high p type impurity concentration.
Therefore, in the n ⁺ type drift region 18b, the depletion layer is unlikely to extend, so that a JFET (Junction F) is formed between the p ⁺ type body region 16a and the p ⁺ type body region 16b.
It becomes difficult for the field effect transistor effect to occur. Therefore, the n ⁺ type drift region 18
Since the width of b can be reduced, the power MOS field effect transistor 1 can be miniaturized. This is O
It contributes to the reduction of resistance during N operation.

Next, the OFF operation of the power MOS field effect transistor 1 will be described. When the gate electrode 24 is changed from a positive voltage to a negative voltage or grounded, the n-type channel disappears. Accordingly, the power MOS field-effect transistor 1 is of n ⁺ -type drain region 10 n ⁺ -type source region 20a, the operation passes no current to 20b.

The power MOS field effect transistor 1 is O
During the FF operation, the depletion layer causes the pn junctions 26a and 26a.
From b, 28a, 28b, 30a, 30b, n type drift region 18a, n ⁺ type drift region 18b, n type drift region 12a, n type drift region 12b, p type body region 14a, p type body region 14b, p ⁺ Mold body region 1
6a and the p ⁺ type body region 16b.
When the power MOS field effect transistor 1 is turned off, the depletion layer causes the n ⁺ type drain region 10 and the n ⁺
The current is prevented from flowing between the mold source regions 20a and 20b.

According to the power MOS field effect transistor 1, the breakdown voltage can be increased. The reason will be described below. In a power MOS field effect transistor, generally, the depth of the p ⁺ type body region is large, and n
As the impurity concentration of the type silicon substrate decreases, the depletion layer expands, and the breakdown voltage improves.

P of the power MOS field effect transistor 1
The type body regions 14a and 14b have a low impurity concentration.
Is uniform. Power MOS field effect transistor 1
Is p ⁺Immediately below the mold body regions 16a, 16b,
Since it has such p-type body regions 14a and 14b, it is depleted.
The layers are easy to spread.

As described above, the power MOS field effect transistor 1 can achieve low resistance and high breakdown voltage.

Next, a specific example of the impurities and the concentration of each region will be described.

(1) n-type drift region 18a n-type impurity: phosphorus, arsenic or antimony n-type impurity concentration: 5 × 10 ¹⁵ / cm ³ (2) n ⁺ type drift region 18b n-type impurity: phosphorus, arsenic or antimony n-type impurity concentration: 1 × 10 ¹⁶ / cm ³ (3) n-type drift regions 12a, 12b n-type impurity: arsenic, antimony or phosphorus n-type impurity concentration: 1 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ³ (4 ) P-type body regions 14a and 14b p-type impurity: boron p-type impurity concentration: 3 × 10 ¹⁵ / cm ³ Depending on the setting of the impurity concentration, the depletion layer is spread over the entire region and is completely depleted. Will also be possible. Complete depletion is preferable in order to increase the breakdown voltage of the power MOS field effect transistor. An example of specific conditions for complete depletion will be described.

Concentration of n-type impurities in the n-type drift region 18a
Degree: 3 × 10¹⁵/ Cm³ n⁺N-type impurity concentration of the type drift region 18b: 1 × 10
¹⁶/ Cm³ n-type impurity concentration in the n-type drift regions 12a and 12b: 1
× 10¹⁵~ 3 x 10 ¹⁵/ Cm³ P-type impurity concentration of p-type body regions 14a and 14b: 3 ×
10¹⁵/ Cm³ {Simulation of device performance} Next, power MO
The S field effect transistor 1 was simulated and
From the results of the above, the resistance of the power MOS field effect transistor 1
How much pressure, and how much resistance during ON operation
I asked.

First, the degree of breakdown voltage of the power MOS field effect transistor 1 will be described. FIG. 2A shows a power MO.
A part of the cross section of the S field effect transistor 1 is shown.
The simulation conditions are as follows.

N⁺N-type impurity concentration of the drain region 10
Degree: 5 × 10¹⁸/ Cm³ n-type impurity concentration in the n-type drift region 12a: 1 × 10¹⁵
~ 3 x 10¹⁵/ Cm ³ n-type impurity concentration of the n-type drift region 18a: 3 × 10¹⁵
/ Cm³ n-type impurity concentration of the n-type drift region 18b: 1 × 10¹⁶
/ Cm³ P-type impurity concentration in p-type body region 14a: 3 × 10¹⁵/
cm³ p⁺P-type impurity concentration of the type body region 16a: 5 × 10¹⁵
~ 9 × 10¹⁵/ Cm³Gate voltage: 0V Drain voltage: in the range of 0 to 230V, 1V at a time
Increase voltage Source voltage: 0V Body voltage: 0V FIG. 2B shows that the drain voltage is 22 when OFF.
The power of the power MOS field effect transistor 1 at 0 V
It is a figure which shows a rank distribution. Equipotential is divided by 10V step
I'm clothed. As can be seen from Fig. 2 (B), the drift region
The equipotential lines 38 are distributed over the entire region and body region.
There is. This is because the drift and body regions are completely empty.
It means becoming scarce.

As described above, when the drain voltage is 220 V, the power MOS field effect transistor 1 is not dielectrically broken down because of the depletion layer in the drift region and the body region.

Next, the resistance of the power MOS field effect transistor 1 during ON operation will be described. Figure 3
FIG. 4 is a graph showing the result of simulating the relationship between the gate voltage and the drain current of the power MOS field effect transistor 1. According to this graph, the drain current I _d when the gate voltage is 10 V is 9.5 × 1.
It becomes 0 ⁻⁷ A / μm. Then, using this result, the O of the power MOS field effect transistor 1 having a breakdown voltage of 220 V is
When calculating the resistance (R _ON ) during N operation, 0.4Ω ・ mm
It becomes ² . The calculation formula is as follows.

R _ON = (V _d / I _d ) × cell size Here, V _d : 0.1 V I _d : 9.5 × 10 ⁻⁷ A / μm Cell size: 3.8 μm {Device manufacturing method} Next, a manufacturing process of the power MOS field effect transistor 1 will be described. 4 and 5
[FIG. 7] is a process drawing for explaining this.

As shown in FIG. 4A, a silicon substrate including the n ⁺ type drain region 10 is prepared. The drain region 10 has a thickness of 400 to 500 μm.

An n-type silicon layer 12 is formed on the drain region 10 by, for example, epitaxial growth. The thickness of the n-type silicon layer 12 is 1 to 10 μm. The n-type silicon layer 12 becomes the n-type drift regions 12a and 12b.

Next, the p-type silicon layer 14 is formed on the n-type silicon layer 12 by, for example, epitaxial growth. The p-type silicon layer 14 has a thickness of 1 to 10 μm. The p-type silicon layer 14 includes p-type body regions 14a and 1a.
4b.

Next, the p ⁺ type silicon layer 16 is formed on the p type silicon layer 14 by, for example, epitaxial growth. The p ⁺ type silicon layer 16 has a thickness of 1 to 4 μm. The p ⁺ type silicon layer 16 includes a p ⁺ type body region 16a,
16b.

As shown in FIG. 4B, the mask layer 40 is formed on the p ⁺ type silicon layer 16 by using thermal oxidation, a CVD method or the like.
To form. The mask layer 40 is made of a silicon oxide layer.

The mask layer 40 is patterned by photolithography and etching. This allows
An opening 42 is formed in the mask layer 40.

Using the mask layer 40 as a mask, the p ⁺ type silicon layer 16, the p type silicon layer 14 and the n type silicon layer 12 are selectively etched to form a trench 44 under the opening 42. The trench 44 is the n ⁺ type drain region 1
It has reached 0. The depth d of the trench 44 is 5 to 25
μm, and the width w is 0.5 to 4.0 μm. By this etching, the p ⁺ type silicon layer 16 becomes
The p ⁺ type body region 16a and the p ⁺ type body region 16b are separated. The p-type silicon layer 14 is separated into a p-type body region 14a and a p-type body region 14b. Also, n
The type silicon layer 12 is divided into an n type drift region 12a and an n type drift region 12b.

As shown in FIG. 4C, a thickness of 0.5 to
A 4.0 μm polysilicon layer 46 is formed on the mask layer 40 to fill the trenches 44. An amorphous silicon layer or a single crystal silicon layer may be used instead of the polysilicon layer. And the polysilicon layer 4
Anneal 6 Annealing temperature is 400-600 ° C
Is. The annealing time is 6 to 18 hours. Then, the polysilicon layer 46 is etched back to form the trench 4
The polysilicon layer 46 is left only in the region 4.

Next, using the mask layer 40 as a mask, n-type impurities are ion-implanted into the upper layer of the polysilicon layer 46. The conditions are as follows.

Ion: As or P Dose amount: 5 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² Implantation energy: 30 to 180 KeV As shown in FIG. 5 (A), the structure of FIG. 4 (C) is heat-treated. , N ⁺ type drift region 18b and n type drift region 18a are formed.

As shown in FIG. 5B, the gate oxide layer 22 and the gate electrode 24 are laminated on the p ⁺ type body 16a, the n ⁺ type drift region 18b and the p ⁺ type body 16b by using a known method. Form a thing.

As shown in FIG. 1, p
N ⁺ type source regions 20a and 20b are formed in ⁺ type bodies 16a and 16b, respectively. Alternatively, the n ⁺ type source regions 20a and 20b may be formed first, and then the stacked body of the gate oxide layer 22 and the gate electrode 24 may be formed. This also applies to the later embodiments. Through the above steps, the power MOS field effect transistor 1 is completed.

The power MOS field effect transistor according to the subsequent embodiments can also be manufactured by using the same method as the method for manufacturing the power MOS field effect transistor 1.

The first embodiment is a power MOS.
It is a field effect transistor. However, the present invention is not limited to this, and can be applied to other vertical semiconductor devices. This also applies to other embodiments described later.

[Second Embodiment] FIG. 6 is a sectional view of a power MOS field effect transistor 3 according to a second embodiment of the present invention. The parts having the same functions as those of the power MOS field effect transistor 1 according to the first embodiment shown in FIG. Power M
The part of the OS field effect transistor 3 which is different from the power MOS field effect transistor 1 will be described, and the description of the same parts will be omitted.

The power MOS field effect transistor 3 is
Unlike the power MOS field effect transistor 1, the n-type drift region 12a and the n-type drift region 12b are not provided. Instead, in the power MOS field effect transistor 3, the p type body regions 14a and 14b reach the n ⁺ type drain region 10, respectively.

The power MOS field effect transistor 3 has the following unique effects. Since the power MOS field effect transistor 3 does not include the n-type drift region 12a and the n-type drift region 12b, the area of the drift region can be reduced accordingly. Therefore, complete depletion of the drift region is facilitated.

Further, according to the power MOS field effect transistor 3, for the same reason as the power MOS field effect transistor 1, the O of the power MOS field effect transistor 3 is reduced.
It is possible to reduce the resistance during N operation.

[Third Embodiment] FIG. 7 is a sectional view of a power MOS field effect transistor 5 according to a third embodiment of the present invention. The parts having the same functions as those of the power MOS field effect transistor 1 according to the first embodiment shown in FIG. Power M
The parts of the OS field effect transistor 5 different from the power MOS field effect transistor 1 will be described, and the description of the same parts will be omitted.

The power MOS field effect transistor 5 is
Unlike the power MOS field effect transistor 1, the n-type drift region 12a and the n-type drift region 12b are not provided. Instead, in the power MOS field effect transistor 5, the p ⁻ type body region 32a is located between the p type body region 14a and the n ⁺ type drain region 10, and p ^{− −}
The type body region 32b is located between the p type body region 14b and the n ⁺ type drain region 10. The p type impurity concentration of the p ⁻ type body regions 32a and 32b is lower than the p type impurity concentration of the p type body regions 14a and 14b. p ^-
The p-type impurity concentration of the mold body regions 32a and 32b is, for example, 1 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ³ .

According to the power MOS field effect transistor 5, the following unique effects occur. The power MOS field effect transistor 5 includes n-type drift regions 12a and 12b.
Instead, since the p ⁻ type body regions 32a and 32b are provided, the area of the drift region can be reduced accordingly.
Therefore, complete depletion of the drift region is facilitated.

Further, according to the power MOS field effect transistor 5, the O of the power MOS field effect transistor 5 is the same as that of the power MOS field effect transistor 1 for the same reason.
It is possible to reduce the resistance during N operation.

[Fourth Embodiment] FIG. 8 is a sectional view of a power MOS field effect transistor 7 according to a fourth embodiment of the present invention. The parts having the same functions as those of the power MOS field effect transistor 1 according to the first embodiment shown in FIG. Power M
The parts of the OS field effect transistor 7 different from the power MOS field effect transistor 1 will be described, and the description of the same parts will be omitted.

The power MOS field effect transistor 7 is
Unlike the power MOS field effect transistor 1, the p-type body regions 14a and 14b are not provided. Instead,
In the power MOS field effect transistor 7, the n-type drift region 12a and the n-type drift region 12b reach the p ⁺ type body regions 16a and 16b, respectively.

This power MOS field effect transistor 7
According to the above, for the same reason as that of the power MOS field effect transistor 1, that is, since the n ⁺ type drift region 18b is provided, it is possible to reduce the resistance of the power MOS field effect transistor 7 during the ON operation.

[Fifth Embodiment] FIG. 9 is a sectional view of a power MOS field effect transistor 9 according to a fifth embodiment of the present invention. The parts having the same functions as those of the power MOS field effect transistor 1 according to the first embodiment shown in FIG. Power M
The parts of the OS field effect transistor 9 different from the power MOS field effect transistor 1 will be described, and the description of the same parts will be omitted.

The power MOS field effect transistor 9 is
Unlike the power MOS field effect transistor 1, the n-type drift region 18a is not provided. Instead, in the power MOS field effect transistor 9, the n ⁺ type drift region 18b reaches the n ⁺ type drain region 10.

This power MOS field effect transistor 9
According to the method, the n ⁺ type drift region 18b is provided instead of the n type drift region 18a. Therefore, the power MO
It is possible to further reduce the resistance when the S field effect transistor 9 is ON.

[Example of Circuit Having Embodiment of Present Invention]
FIG. 10 shows an inverter circuit 52 including the power MOS field effect transistor 1. The inverter circuit 52 is
Convert DC power source 50 such as battery into 3 phase AC
The rotation of the phase motor 48 is controlled. Inverter circuit 52
Are used, for example, to drive the motors of electric vehicles. Instead of the power MOS field effect transistor 1, the power MOS field effect transistors 3, 5,
It is also possible to use 7 and 9.

[Brief description of drawings]

FIG. 1 is a power MO according to a first embodiment of the present invention.
3 is a sectional view of an S field effect transistor 1. FIG.

FIG. 2A is a partial cross-sectional view of the power MOS field effect transistor 1 according to the first embodiment of the present invention. FIG. 6B is a diagram showing a simulation of the potential distribution of the power MOS field effect transistor 1 according to the first embodiment of the present invention.

FIG. 3 is a power MO according to the first embodiment of the present invention.
5 is a graph showing the result of simulating the relationship between the gate voltage and the drain current of the S field effect transistor 1.

FIG. 4 is a power MO according to the first embodiment of the present invention.
FIG. 6 is a process drawing for explaining a manufacturing process of the S field effect transistor 1.

FIG. 5 is a power MO according to the first embodiment of the present invention.
FIG. 6 is a process drawing for explaining a manufacturing process of the S field effect transistor 1.

FIG. 6 is a power MO according to a second embodiment of the present invention.
3 is a cross-sectional view of an S field effect transistor 3. FIG.

FIG. 7 is a power MO according to a third embodiment of the present invention.
3 is a cross-sectional view of an S field effect transistor 5. FIG.

FIG. 8 is a power MO according to a fourth embodiment of the present invention.
6 is a cross-sectional view of an S field effect transistor 7. FIG.

FIG. 9 is a power MO according to a fifth embodiment of the present invention.
3 is a cross-sectional view of an S field effect transistor 9. FIG.

FIG. 10 is a circuit diagram of an inverter circuit 52 including a power MOS field effect transistor 1.

FIG. 11 is a cross-sectional view of a conventional general power MOS field effect transistor.

[Explanation of symbols]

1, 3, 5, 7, 9 Power MOS field effect transistor 10 n ⁺ type drain regions 12a, 12b n type drift regions 14a, 14b p type body regions 16a, 16b p ⁺ type body regions 18a, 18b n ⁺ type drift regions 20a, 20b n ⁺ type source region 22 gate oxide layer 24 gate electrodes 26a, 26b pn junction 28a, 28b pn junction 30a, 30b pn junction 32a, 32b p ⁻ type body region 40 mask layer 44 trench 46 polysilicon layer 52 Inverter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] 1. A first conductive type first semiconductor region, a first conductive type
Type second semiconductor region, second conductivity type third semiconductor region, and
And a vertical semiconductor device having a first conductivity type fourth semiconductor region
And the first semiconductor region emits carriers of the first conductivity type.
Then, carriers of the first conductivity type flow in the second semiconductor region.
Becomes a path, said second semiconductor region has a higher impurity concentration of the first conductivity type
High concentration region and low concentration region where the first conductivity type impurity concentration is low
A third semiconductor region is joined to the second semiconductor region,
A high-concentration region having a high second-conductivity-type impurity concentration;
A low-concentration region having a low conductivity type impurity concentration, wherein the low-concentration region of the third semiconductor region is the fourth semiconductor region.
Extends to pass, the fourth semiconductor region, write sucks first conductive carrier
A vertical semiconductor device. 2. A first conductivity type first semiconductor region, a first conductivity type.
Type second semiconductor region, second conductivity type third semiconductor region,
A fourth semiconductor region of one conductivity type and the other half of the second conductivity type
A vertical semiconductor device having a conductor region, wherein the first semiconductor region emits carriers of a first conductivity type.
Then, carriers of the first conductivity type flow in the second semiconductor region.
Becomes a path, said second semiconductor region has a higher impurity concentration of the first conductivity type
High concentration region and low concentration region where the first conductivity type impurity concentration is low
A third semiconductor region is joined to the second semiconductor region,
A high-concentration region having a high second-conductivity-type impurity concentration;
A low-concentration region of low conductivity type impurity concentration, wherein the fourth semiconductor region absorbs carriers of the first conductivity type.
However, the other semiconductor region is a low concentration region of the third semiconductor region.
The impurity concentration of the second conductivity type is lower than that of the region, and the other semiconductor region is in the low concentration region of the third semiconductor region.
Vertical half located between the region and the fourth semiconductor region
Conductor device. 3. A first conductivity type first semiconductor region, a first conductivity type.
Type second semiconductor region , second conductivity type third semiconductor region, and
And a vertical semiconductor device having a first conductivity type fourth semiconductor region
And the first semiconductor region emits carriers of the first conductivity type.
Then, carriers of the first conductivity type flow in the second semiconductor region.
Becomes a path, said second semiconductor region has a higher impurity concentration of the first conductivity type
High concentration region and low concentration region where the first conductivity type impurity concentration is low
It includes a band, a high concentration region of the second semiconductor region, the third semiconductor territory
And a high concentration region of the second semiconductor region is connected to the fourth semiconductor region.
And a low concentration region of the second semiconductor region is connected to the third semiconductor region.
Is located between the first semiconductor region and the fourth semiconductor region, and the low-concentration region of the second semiconductor region is the third semiconductor region.
Region, the third semiconductor region is joined to the second semiconductor region, and the fourth semiconductor region absorbs carriers of the first conductivity type.
A vertical semiconductor device. 4. A first conductivity type first semiconductor region, a first conductivity type.
Type second semiconductor region, second conductivity type third semiconductor region, and
And a vertical semiconductor device having a first conductivity type fourth semiconductor region
And the first semiconductor region emits carriers of the first conductivity type.
Then, carriers of the first conductivity type flow in the second semiconductor region.
Becomes a path, said second semiconductor region has a higher impurity concentration of the first conductivity type
High concentration region and low concentration region where the first conductivity type impurity concentration is low
It includes a band, a high concentration region of the second semiconductor region, the third semiconductor territory
And a high concentration region of the second semiconductor region is connected to the fourth semiconductor region.
And a low concentration region of the second semiconductor region is connected to the third semiconductor region.
Is located between the first semiconductor region and the fourth semiconductor region, and the low-concentration region of the second semiconductor region is the third semiconductor region.
A third semiconductor region is joined to the second semiconductor region,
A high-concentration region having a high second-conductivity-type impurity concentration;
A low-concentration region of low conductivity type impurity concentration, wherein the fourth semiconductor region absorbs carriers of the first conductivity type.
A vertical semiconductor device.