JP2004039774A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2004039774A
JP2004039774A JP2002192998A JP2002192998A JP2004039774A JP 2004039774 A JP2004039774 A JP 2004039774A JP 2002192998 A JP2002192998 A JP 2002192998A JP 2002192998 A JP2002192998 A JP 2002192998A JP 2004039774 A JP2004039774 A JP 2004039774A
Authority
JP
Japan
Prior art keywords
layer
body layer
drain
conductivity type
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002192998A
Other languages
Japanese (ja)
Other versions
JP4171251B2 (en
Inventor
Eiji Nishibe
西部　栄次
Shuichi Kikuchi
菊地　修一
Masabumi Uehara
上原　正文
Katsuyoshi Anzai
安齊　勝義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2002192998A priority Critical patent/JP4171251B2/en
Publication of JP2004039774A publication Critical patent/JP2004039774A/en
Application granted granted Critical
Publication of JP4171251B2 publication Critical patent/JP4171251B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve an operating breakdown voltage of a DMOS type high breakdown transistor. <P>SOLUTION: A body layer includes a first body layer 3 deeply formed by including a channel region CH between an n+-type source layer and an n-type first drain layer 4, and a second body layer 6 overhanging from the first body layer 3 to a region under the layer 4 and shallowly formed. Since the impurity concentration of the layer 6 can be set low irrespective of that of the layer 3, an electric field by a drain voltage can be alleviated in this part. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路に内蔵される、ＤＭＯＳ（Ｄｉｆｆｕｓｅｄ　ＭＯＳ）タイプの高耐圧トランジスタに関する。
【０００２】
【従来の技術】
高耐圧ＭＯＳトランジスタは、高いソースドレイン耐圧（ＢＶＤＳ）、あるいは高いゲート耐圧を有しており、ＬＣＤドライバー、ＥＬドライバーや電源回路等に応用されている。
【０００３】
図１１は従来例に係るＤＭＯＳタイプのＮチャネル型の高耐圧トランジスタの構造を示す断面図である。Ｐ型のシリコン基板１００の表面に、Ｎ型ウエル領域１０１が形成され、このＮ型ウエル領域１０１の表面にＰ型のボディ層１０２が形成されている。またＰ型のボディ層１０２の表面に、ゲート酸化膜１０３、厚いフィールド酸化膜１０４Ａ，１０４Ｂが形成されている。そして、ゲート酸化膜１０３から隣接するフィールド酸化膜１０４Ａの一部上に延在するゲート電極１０５が形成されている。
【０００４】
ゲート電極１０５の一方の端に隣接し、ボディ層１０２の表面にＮ＋型ソース層１０６が形成されている。また、Ｎ＋型ソース層１０６に隣接して、ボディ層１０２の電位固定用のＰ＋層１０７が形成されている。
【０００５】
更に、ウエル領域１０１の表面領域及びボディ層１０２の表面に部分的に重畳する領域にＮ型の第１ドレイン層１０８が形成されている。また、ゲート電極１０５の他方の端から離間して、Ｎ型の第１ドレイン層１０８の表面に配置されたＮ＋型の第２ドレイン層１０９が形成されている。
【０００６】
上記の高耐圧ＭＯＳトランジスタ構造によれば、第２ドレイン層１０９に高いドレイン電圧を印加した場合に、Ｎ型ウエル領域１０１及びボディ層１０２に空乏層が広がり、ドレイン電界が緩和されるため、高いソースドレイン耐圧を得ることができる。また、Ｎ型の第１ドレイン層１０８を設けているので、トランジスタのオン抵抗を下げることができる。
【０００７】
また、ゲート電極１０５はゲート酸化膜１０３から隣接するフィールド酸化膜１０４Ａの一部上に延在しているため、ゲート酸化膜１０３の破壊にも強い構造を有している。
【０００８】
【発明が解決しようとする課題】
しかしながら、上述した高耐圧トランジスタは、その動作耐圧が低いという問題があった。ここで、動作耐圧は、高耐圧トランジスタがオンであり、チャネル電流が流れている状態でのソースドレイン間耐圧をいう。
【０００９】
その原因は、本発明者の検討によれば、図１１に示すように、第２ドレイン層１０９に印加されるドレイン電圧が高くなると、ボディ層１０２の上縁部（図中のＡの部分）で電界が集中し、ブレークダウンを生じるためである。
【００１０】
【課題を解決するための手段】
そこで、本発明はボディ層の不純物分布を工夫して、ボディ層の上縁部の電界を緩和した。即ち、図８に示すように、ボディ層は、Ｎ＋型ソース層とＮ型の第１ドレイン層４との間のチャネル領域ＣＨを含んで深く形成された第１のボディ層３と、この第１のボディ層３からＮ型の第１ドレイン層４の下の領域に張り出して浅く形成された第２のボディ層６とから構成されるようにした。
【００１１】
これにより、第２のボディ層６の不純物濃度は第１のボディ層３の不純物濃度とは無関係に低く設定できるようになるので、ドレイン電圧による電界をこの部分で緩和することができる。一方、チャネル領域ＣＨについては、第１のボディ層３と第２のボディ層６とが重畳されているので、チャネル不純物濃度を高く設定でき、ソースドレイン間のパンチスルーを防止できる。更に、第１のボディ層３は深く形成されているので、Ｎ型ウエル領域２との接合付近では第２のボディ層６の不純物濃度に影響されず、第１のボディ層３とＮ型ウエル領域２との接合耐圧も高く確保することができる。
【００１２】
したがって、この構造によれば、高耐圧トランジスタの動作耐圧を向上できると共に、ソースドレイン間のパンチスルーを防止してトランジスタサイズを縮小できる。
【００１３】
【発明の実施の形態】
次に、本発明の実施形態による半導体装置及びその製造方法について図面を参照しながら説明する。
【００１４】
まず、図１に示すように、Ｐ型シリコン基板１の表面にイオン注入・熱拡散によりＮ型ウエル領域２を形成する。ここで、イオン注入は、例えばリン（３１Ｐ＋）を加速エネルギー１４０〜１６０ＫｅＶ、ｄｏｓｅ量５×１０１２／ｃｍ２の条件で行う。その後、１２００℃で１５時間程度の熱拡散を行う。
【００１５】
次に、図２に示すように、Ｐ型の第１のボディ層３、Ｎ型の第１ドレイン層４を形成する。このＮ型の第１ドレイン層４は、Ｐ型の第１のボディ層３に隣接して形成される。ただし、図のようにＮ型の第１ドレイン層４とＰ型の第１のボディ層３とは必ずしも接触していることは必要ではなく、離間されていてもよい。
【００１６】
ここで、Ｐ型の第１のボディ層３形成のためのイオン注入は、不図示のフォトレジスト層をマスクとして、例えばボロン（１１Ｂ＋）を加速エネルギー８０ＫｅＶ、ｄｏｓｅ量１．５×１０１３／ｃｍ２の条件で行う。
【００１７】
また、Ｎ型の第１ドレイン層４を形成するためのイオン注入は、不図示のフォトレジスト層をマスクとして、例えば砒素（７５Ａｓ＋）を加速エネルギー１６０ＫｅＶ、ｄｏｓｅ量２×１０１２／ｃｍ２、続いてリン（３１Ｐ＋）を加速エネルギー１００ＫｅＶ、ｄｏｓｅ量１×１０１２／ｃｍ２、条件で行う。上記のイオン注入後、１１００℃で４時間程度の熱拡散を行う。
【００１８】
次に、図３に示すように、フォトレジスト層５をマスクとして、Ｐ型の第２のボディ層６を形成するためのイオン注入を行う。このイオン注入は、例えば、ボロン（１１Ｂ＋）を加速エネルギー１２０ＫｅＶ、ｄｏｓｅ量１×１０１３／ｃｍ２〜２×１０１３／ｃｍ２の条件で行う。Ｐ型の第２のボディ層６は、Ｐ型の第１のボディ層３に重畳され、このＰ型の第１のボディ層３からＮ型の第１ドレイン層４の一部の下の領域に張り出して形成される。Ｐ型の第２のボディ層６は、Ｎ型の第１ドレイン層４と部分的に重畳されるが、Ｎ型の第１ドレイン層４はＰ型の第２のボディ層６よりも浅く形成される。
【００１９】
次に、図４に示すように、ＬＯＣＯＳ（Ｌｏｃａｌ　Ｏｘｉｄａｔｉｏｎ　Ｏｆ　Ｓｉｌｉｃｏｎ）法を用いて、フィールド酸化膜７Ａ，７Ｂを形成する。フィールド酸化膜は一般には素子分離用に形成されるが、この半導体装置では高耐圧トランジスタの耐圧を向上するために利用している。その膜厚は目標耐圧によって異なるが、３００ｎｍ〜１１００ｎｍ程度である。また、このフィールド酸化処理により、Ｐ型の第２のボディ層６は、拡散係数の違いからＮ型の第１ドレイン層４よりも深く拡散されるため、Ｎ型の第１ドレイン層４の一部の下の領域に広がって形成される。
【００２０】
次に、図５に示すように、フィールド酸化膜７Ａの所定領域を部分的にエッチングして、Ｐ型の第１のボディ層３及び第２のボディ層３の重畳領域の表面を露出する。そして、熱酸化することによりゲート酸化膜８を形成する。その膜厚はトランジスタのゲート耐圧の目標耐圧によって異なるが、１５ｎｍ〜２５０ｎｍ程度である。当然であるが、フィールド酸化膜７Ａ，７Ｂは、ゲート酸化膜９よりも相当厚い膜厚を有している。
【００２１】
そして、前面にポリシリコン層をＬＰＣＶＤ法を用いて堆積し、このポリシリコン層を選択的にエッチングすることにより、ゲート電極９形成する。このゲート電極９の一端はＰ型の第１のボディ層３及び第２のボディ層６の重畳領域の表面上に配置する。また、ゲート電極９の他端は、ゲート酸化膜８上からフィールド酸化膜７Ａの一部上に延在するように形成する。
【００２２】
なお、Ｐ型の第１のボディ層３はＮ型の第１ドレイン層４と接している事は必要ではなく、後述するソース層側に（図上では左側に）離れていてもよい。
【００２３】
次に、図６に示すように、Ｎ＋型の第２ドレイン層の形成予定領域をマスクするフォトレジスト層１０を形成し、イオン注入を行い、ボディ層電位固定用のＰ＋層１１を形成する。このイオン注入は、Ｐチャネルトランジスタのソースドレイン形成用のイオン注入を兼用することができ、例えばボロン（１１Ｂ＋）を加速エネルギー３０ＫｅＶ、ｄｏｓｅ量２×１０１５／ｃｍ２程度の条件で打ち込む。
【００２４】
次に、図７に示すように、イオン注入により、Ｎ＋型ソース層１２、Ｎ＋型の第２ドレイン層１３を形成する。Ｎ＋型ソース層１２は、フォトレジスト層１４がマスクとなり、ゲート電極９の一端に整合すると共に、Ｐ＋層１１に隣接して形成される。また、Ｎ＋型の第２ドレイン層１３は、フィールド酸化膜７Ａ，７Ｂの間の、Ｎ型の第１ドレイン層４の表面に形成される。
【００２５】
このイオン注入は、例えば、リン（３１Ｐ＋）をｄｏｓｅ量１×１０１４／ｃｍ２、加速エネルギー７０ＫｅＶの条件で打ち込み、更に、砒素（７５Ａｓ＋）をｄｏｓｅ量６×１０１５／ｃｍ２、加速エネルギー８０ＫｅＶの条件で打ち込む。
【００２６】
そして、図８に示すように、層間絶縁膜としてＢＰＳＧ膜１５をＣＶＤ法により堆積する。その後、Ｐ＋層１１及びＮ＋型ソース層１２の境界領域上、
及びＮ＋型の第２ドレイン層１３上にコンタクトホールを形成し、ソース電極１６、ドレイン電極１７を形成する。
【００２７】
このようにして完成した半導体装置の不純物濃度分布を図９に示す。図９（ａ）は図８のＸ線上の不純物分布、即ち、チャネル領域ＣＨの表面からＮ型ウエル領域２の深さ方向に沿った不純物分布を示している。図９（ｂ）は図８のＹ線上の不純物分布、即ち、Ｎ型の第１ドレイン層４の表面からＮ型ウエル領域２の深さ方向に沿った不純物分布を示している。
【００２８】
第２のボディ層６は、第１のボディ層３からＮ型の第１ドレイン層４の下の領域に張り出しているので、この張り出し領域の不純物濃度は第１のボディ層３の不純物濃度とは無関係に低く設定されている。（図９（ｂ）参照）これにより、ドレイン電圧による電界をこの部分で緩和することができる。
【００２９】
一方、Ｎ＋型ソース層１２とＮ型の第１ドレイン層４との間に画定されるチャネル領域ＣＨについては、第１のボディ層３と第２のボディ層６とが重畳されているので、チャネル不純物濃度が高く設定され、ソースドレイン間のパンチスルーを防止できる。更に、第１のボディ層３は深く形成されているので、Ｎ型ウエル領域２との接合付近では第２のボディ層６の不純物濃度に影響されず、第１のボディ層３とＮ型ウエル領域２との接合耐圧も高く確保することができる。（図９（ａ）参照）
図１０はドレイン電圧とソースドレイン間に流れる動作電流との関係を示す図である。図１０（ａ）は本発明に係る特性、図１０（ｂ）は従来例に係る特性を示している。従来例では、動作耐圧が４０Ｖと低いが、本発明によれば８０Ｖ程度まで向上していることが実験的に確認された。
【００３０】
なお、上記実施形態では、Ｎチャネル型ＭＯＳトランジスタについて説明したが、本発明はＰチャネル型ＭＯＳトランジスタについても同様に適用することができる。
【００３１】
【発明の効果】
本発明によれば、ＤＭＯＳタイプのトランジスタにおいて、ボディ層を、チャネル領域ＣＨに深く形成された第１のボディ層３と、この第１のボディ層３からＮ型の第１ドレイン層４の下の領域に張り出して浅く形成された第２のボディ層６とから構成した。これにより、トランジスタの動作耐圧を向上できると共に、ソースドレイン間のパンチスルーを防止してトランジスタサイズを縮小できるという効果を奏する。
【図面の簡単な説明】
【図１】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図２】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図３】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図４】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図５】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図６】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図７】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図８】本発明の実施形態による半導体装置及びその製造方法を示す断面図である。
【図９】本発明の実施形態による半導体装置の不純物濃度分布を示す図である。
【図１０】ドレイン電圧とソースドレイン間に流れる動作電流との関係を示す図である。
【図１１】従来例に係る半導体装置を示す断面図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DMOS (Diffused MOS) type high breakdown voltage transistor built in a semiconductor integrated circuit.
[0002]
[Prior art]
A high breakdown voltage MOS transistor has a high source / drain breakdown voltage (BVDS) or a high gate breakdown voltage, and is applied to an LCD driver, an EL driver, a power supply circuit, and the like.
[0003]
FIG. 11 is a cross-sectional view showing the structure of a conventional DMOS type N-channel high breakdown voltage transistor. An N-type well region 101 is formed on the surface of a P-type silicon substrate 100, and a P-type body layer 102 is formed on the surface of the N-type well region 101. A gate oxide film 103 and thick field oxide films 104A and 104B are formed on the surface of the P-type body layer 102. Then, a gate electrode 105 extending from the gate oxide film 103 to a part of the adjacent field oxide film 104A is formed.
[0004]
An N + type source layer 106 is formed on the surface of the body layer 102 adjacent to one end of the gate electrode 105. Further, a P + layer 107 for fixing the potential of the body layer 102 is formed adjacent to the N + type source layer 106.
[0005]
Further, an N-type first drain layer 108 is formed in a surface region of the well region 101 and a region partially overlapping the surface of the body layer 102. Further, an N + type second drain layer 109 disposed on the surface of the N type first drain layer 108 is formed apart from the other end of the gate electrode 105.
[0006]
According to the high breakdown voltage MOS transistor structure described above, when a high drain voltage is applied to the second drain layer 109, the depletion layer spreads in the N-type well region 101 and the body layer 102, and the drain electric field is relaxed. Source / drain breakdown voltage can be obtained. Further, since the N-type first drain layer 108 is provided, the on-resistance of the transistor can be reduced.
[0007]
In addition, since the gate electrode 105 extends from the gate oxide film 103 to a part of the adjacent field oxide film 104A, the gate electrode 105 has a structure that is strong against destruction of the gate oxide film 103.
[0008]
[Problems to be solved by the invention]
However, the above-mentioned high breakdown voltage transistor has a problem that its operating breakdown voltage is low. Here, the operating breakdown voltage refers to the breakdown voltage between the source and the drain when the high breakdown voltage transistor is on and a channel current is flowing.
[0009]
According to the study of the present inventor, the cause is that as shown in FIG. 11, when the drain voltage applied to the second drain layer 109 increases, the upper edge of the body layer 102 (portion A in the figure) This is because the electric field concentrates at the point, causing breakdown.
[0010]
[Means for Solving the Problems]
Therefore, the present invention devises the impurity distribution of the body layer to reduce the electric field at the upper edge of the body layer. That is, as shown in FIG. 8, the body layer includes a first body layer 3 deeply formed including a channel region CH between the N + type source layer and the N type first drain layer 4, and And a shallow second body layer 6 extending from the first body layer 3 to a region below the N-type first drain layer 4.
[0011]
Thereby, the impurity concentration of the second body layer 6 can be set low irrespective of the impurity concentration of the first body layer 3, so that the electric field due to the drain voltage can be reduced in this portion. On the other hand, in the channel region CH, since the first body layer 3 and the second body layer 6 overlap, the channel impurity concentration can be set high, and punch-through between the source and drain can be prevented. Further, since the first body layer 3 is formed deep, the first body layer 3 and the N-type well are not affected by the impurity concentration of the second body layer 6 near the junction with the N-type well region 2. A high junction breakdown voltage with the region 2 can be ensured.
[0012]
Therefore, according to this structure, the operating withstand voltage of the high withstand voltage transistor can be improved, and punch-through between the source and drain can be prevented to reduce the transistor size.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a semiconductor device and a method for fabricating the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings.
[0014]
First, as shown in FIG. 1, an N-type well region 2 is formed on a surface of a P-type silicon substrate 1 by ion implantation and thermal diffusion. Here, the ion implantation is performed, for example, under the conditions of phosphorus ( 31 P + ) at an acceleration energy of 140 to 160 KeV and a dose of 5 × 10 12 / cm 2 . Thereafter, thermal diffusion is performed at 1200 ° C. for about 15 hours.
[0015]
Next, as shown in FIG. 2, a P-type first body layer 3 and an N-type first drain layer 4 are formed. The N-type first drain layer 4 is formed adjacent to the P-type first body layer 3. However, the N-type first drain layer 4 and the P-type first body layer 3 do not necessarily need to be in contact with each other as shown in the figure, and may be separated from each other.
[0016]
Here, ion implantation for the first body layer 3 formed of P-type as a mask the photoresist layer (not shown), for example, boron (11 B +) of an acceleration energy of 80 KeV, dose amount 1.5 × 10 13 / Cm 2 .
[0017]
The ion implantation for forming the first drain layer 4 of N type are an acceleration energy of 160KeV as a mask a photoresist layer (not shown), for example, arsenic (75 As +), dose amount 2 × 10 12 / cm 2 Subsequently, phosphorus ( 31 P + ) is performed under the conditions of an acceleration energy of 100 KeV and a dose of 1 × 10 12 / cm 2 . After the above ion implantation, thermal diffusion is performed at 1100 ° C. for about 4 hours.
[0018]
Next, as shown in FIG. 3, ion implantation for forming a P-type second body layer 6 is performed using the photoresist layer 5 as a mask. This ion implantation is performed, for example, under the conditions of boron ( 11 B + ) at an acceleration energy of 120 KeV and a dose of 1 × 10 13 / cm 2 to 2 × 10 13 / cm 2 . The P-type second body layer 6 is overlapped with the P-type first body layer 3, and a region from the P-type first body layer 3 to a portion below a part of the N-type first drain layer 4. Formed overhanging. The P-type second body layer 6 partially overlaps the N-type first drain layer 4, but the N-type first drain layer 4 is formed shallower than the P-type second body layer 6. Is done.
[0019]
Next, as shown in FIG. 4, the field oxide films 7A and 7B are formed by using the LOCOS (Local Oxidation Of Silicon) method. The field oxide film is generally formed for element isolation. In this semiconductor device, the field oxide film is used to improve the breakdown voltage of the high breakdown voltage transistor. The thickness varies depending on the target breakdown voltage, but is about 300 nm to 1100 nm. Further, due to the field oxidation, the P-type second body layer 6 is diffused deeper than the N-type first drain layer 4 due to a difference in diffusion coefficient. Formed in the region below the part.
[0020]
Next, as shown in FIG. 5, a predetermined region of field oxide film 7A is partially etched to expose the surface of the overlapping region of P-type first body layer 3 and second body layer 3. Then, a gate oxide film 8 is formed by thermal oxidation. The thickness varies depending on the target breakdown voltage of the gate breakdown voltage of the transistor, but is about 15 nm to 250 nm. As a matter of course, the field oxide films 7A and 7B have a considerably larger thickness than the gate oxide film 9.
[0021]
Then, a gate electrode 9 is formed by depositing a polysilicon layer on the front surface by using the LPCVD method and selectively etching the polysilicon layer. One end of the gate electrode 9 is disposed on the surface of the overlapping region of the P-type first body layer 3 and the second body layer 6. The other end of the gate electrode 9 is formed to extend from above the gate oxide film 8 to a part of the field oxide film 7A.
[0022]
Note that the P-type first body layer 3 does not need to be in contact with the N-type first drain layer 4, and may be separated to the source layer side (to the left in the drawing) described later.
[0023]
Next, as shown in FIG. 6, a photoresist layer 10 for masking a region where an N + type second drain layer is to be formed is formed, ions are implanted, and a P + layer 11 for fixing the body layer potential is formed. The ion implantation may be also used the ion implantation for source and drain formation of the P-channel transistor, for example, boron (11 B +) of an acceleration energy of 30 KeV, implanted at dose of 2 × 10 15 / cm 2 of about conditions.
[0024]
Next, as shown in FIG. 7, an N + type source layer 12 and an N + type second drain layer 13 are formed by ion implantation. The N + type source layer 12 is formed adjacent to the P + layer 11 while being aligned with one end of the gate electrode 9 using the photoresist layer 14 as a mask. The N + type second drain layer 13 is formed on the surface of the N type first drain layer 4 between the field oxide films 7A and 7B.
[0025]
In this ion implantation, for example, phosphorus ( 31 P + ) is implanted under the conditions of a dose of 1 × 10 14 / cm 2 and an acceleration energy of 70 KeV, and arsenic ( 75 As + ) is further implanted with a dose of 6 × 10 15 / cm 2. , At an acceleration energy of 80 KeV.
[0026]
Then, as shown in FIG. 8, a BPSG film 15 is deposited as an interlayer insulating film by a CVD method. Then, on the boundary region between the P + layer 11 and the N + type source layer 12,
Then, a contact hole is formed on the N + type second drain layer 13, and a source electrode 16 and a drain electrode 17 are formed.
[0027]
FIG. 9 shows the impurity concentration distribution of the semiconductor device completed in this manner. FIG. 9A shows the impurity distribution on the X-ray in FIG. 8, that is, the impurity distribution along the depth direction of the N-type well region 2 from the surface of the channel region CH. FIG. 9B shows the impurity distribution on the Y line in FIG. 8, that is, the impurity distribution along the depth direction of the N-type well region 2 from the surface of the N-type first drain layer 4.
[0028]
Since the second body layer 6 extends from the first body layer 3 to a region below the N-type first drain layer 4, the impurity concentration of this extended region is equal to the impurity concentration of the first body layer 3. Is set low regardless. (Refer to FIG. 9B.) As a result, the electric field due to the drain voltage can be reduced in this portion.
[0029]
On the other hand, as for the channel region CH defined between the N + type source layer 12 and the N type first drain layer 4, the first body layer 3 and the second body layer 6 are superimposed. The channel impurity concentration is set high, and punch-through between the source and drain can be prevented. Further, since the first body layer 3 is formed deep, the first body layer 3 and the N-type well are not affected by the impurity concentration of the second body layer 6 near the junction with the N-type well region 2. A high junction breakdown voltage with the region 2 can be ensured. (See FIG. 9 (a))
FIG. 10 is a diagram showing the relationship between the drain voltage and the operating current flowing between the source and the drain. FIG. 10A shows characteristics according to the present invention, and FIG. 10B shows characteristics according to a conventional example. In the conventional example, the operating withstand voltage is as low as 40 V, but according to the present invention, it has been experimentally confirmed that the operating voltage is improved to about 80 V.
[0030]
In the above embodiment, an N-channel MOS transistor has been described. However, the present invention can be similarly applied to a P-channel MOS transistor.
[0031]
【The invention's effect】
According to the present invention, in the transistor of the DMOS type, the body layer is formed between the first body layer 3 formed deep in the channel region CH and the first body layer 3 under the N-type first drain layer 4. And the second body layer 6 formed shallowly and protruding in the region of FIG. As a result, the operating voltage of the transistor can be improved, and punch-through between the source and drain can be prevented to reduce the size of the transistor.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device and a method for fabricating the same according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a semiconductor device and a method for fabricating the same according to an embodiment of the present invention.
FIG. 3 is a sectional view illustrating the semiconductor device and the method for fabricating the same according to the embodiment of the present invention.
FIG. 4 is a sectional view illustrating the semiconductor device and the method for fabricating the same according to the embodiment of the present invention.
FIG. 5 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 6 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 7 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 8 is a sectional view illustrating the semiconductor device and the method for fabricating the semiconductor device according to the embodiment of the present invention.
FIG. 9 is a diagram showing an impurity concentration distribution of the semiconductor device according to the embodiment of the present invention.
FIG. 10 is a diagram showing a relationship between a drain voltage and an operating current flowing between a source and a drain.
FIG. 11 is a sectional view showing a semiconductor device according to a conventional example.

Claims (4)

第１導電型の半導体基板と、この半導体基板の表面に設けられた第２導電型のウエル領域と、この第２導電型のウエル領域に表面に設けられた第１導電型のボディ層と、このボディ層の表面に配置されたゲート絶縁膜と、このゲート絶縁膜上に配置されたゲート電極と、このゲート電極の一方の端に隣接し、前記ボディ層の表面に配置された第２導電型のソース層と、前記ソース層と離れた前記ウエル領域の表面領域に配置された第２導電型の第１ドレイン層と、前記ゲート電極の他方の端から離間して前記第１ドレイン層の表面に配置された第２導電型の第２ドレイン層と、を具備する半導体装置であって、
前記ボディ層は前記ソース層と前記第１ドレイン層との間のチャネル領域を含んで深く形成された第１のボディ層と、この第１のボディ層から前記第１ドレイン層の下の領域に張り出して浅く形成された第２のボディ層と、から成ることを特徴とする半導体装置。A semiconductor substrate of the first conductivity type, a well region of the second conductivity type provided on the surface of the semiconductor substrate, a body layer of the first conductivity type provided on the surface of the well region of the second conductivity type; A gate insulating film disposed on the surface of the body layer; a gate electrode disposed on the gate insulating film; and a second conductive layer disposed on the surface of the body layer adjacent to one end of the gate electrode. A source layer of a first conductivity type, a first drain layer of a second conductivity type disposed in a surface region of the well region remote from the source layer, and a first drain layer separated from the other end of the gate electrode. A second conductivity type second drain layer disposed on a surface of the semiconductor device,
The body layer includes a first body layer formed deeply including a channel region between the source layer and the first drain layer, and a first body layer extending from the first body layer to a region below the first drain layer. And a second body layer protruding and shallowly formed. 前記第１ドレイン層の表面に前記ゲート絶縁膜よりも厚い絶縁膜が配置され、前記ゲート電極はこの厚い絶縁膜の一部上に延在することを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein an insulating film thicker than the gate insulating film is disposed on a surface of the first drain layer, and the gate electrode extends over a part of the thick insulating film. 第１導電型の半導体基板の表面に第１導電型の第１のボディ層と、この第１のボディ層に隣接して第２導電型の第１ドレイン層を形成する工程と、
前記第１のボディ層から前記第１ドレイン層の下の領域に張り出した第２のボディ層を形成する工程と、
少なくとも前記第１のボディ層の表面にゲート絶縁膜を形成する工程と、
このゲート絶縁膜上にゲート電極を形成する工程と、
ソース電極と前記ゲート電極から離れた前記第１ドレイン層の表面に第２導電型の第２ドレイン層とを形成する工程とを具備することを特徴とする半導体装置の製造方法。Forming a first body layer of the first conductivity type on the surface of the semiconductor substrate of the first conductivity type and a first drain layer of the second conductivity type adjacent to the first body layer;
Forming a second body layer extending from the first body layer to a region below the first drain layer;
Forming a gate insulating film on at least a surface of the first body layer;
Forming a gate electrode on the gate insulating film;
Forming a second conductivity type second drain layer on the surface of the first drain layer remote from the source electrode and the gate electrode. 第１導電型の半導体基板の表面に第１導電型の第１のボディ層と、この第１のボディ層に隣接して第２導電型の第１ドレイン層を形成する工程と、
前記第１のボディ層から前記第１ドレイン層の下の領域に張り出した第２のボディ層を形成する工程と、
少なくとも前記第１及び第２のボディ層の表面に厚い酸化膜を形成する工程と、
前記厚い酸化膜を部分的にエッチングした領域にゲート絶縁膜を形成する工程と、
このゲート絶縁膜及び前記厚い酸化膜の一部上に延在するゲート電極を形成する工程と、
ソース電極と前記ゲート電極から離れた前記第１ドレイン層の表面に第２導電型の第２ドレイン層とを形成する工程とを具備することを特徴とする半導体装置の製造方法。Forming a first body layer of the first conductivity type on the surface of the semiconductor substrate of the first conductivity type and a first drain layer of the second conductivity type adjacent to the first body layer;
Forming a second body layer extending from the first body layer to a region below the first drain layer;
Forming a thick oxide film on at least the surfaces of the first and second body layers;
Forming a gate insulating film in a region where the thick oxide film is partially etched;
Forming a gate electrode extending over part of the gate insulating film and the thick oxide film;
Forming a second conductivity type second drain layer on the surface of the first drain layer remote from the source electrode and the gate electrode.
JP2002192998A 2002-07-02 2002-07-02 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4171251B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002192998A JP4171251B2 (en) 2002-07-02 2002-07-02 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002192998A JP4171251B2 (en) 2002-07-02 2002-07-02 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004039774A true JP2004039774A (en) 2004-02-05
JP4171251B2 JP4171251B2 (en) 2008-10-22

Family

ID=31702074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002192998A Expired - Fee Related JP4171251B2 (en) 2002-07-02 2002-07-02 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4171251B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245517A (en) * 2005-03-07 2006-09-14 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2006261214A (en) * 2005-03-15 2006-09-28 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2009239111A (en) * 2008-03-27 2009-10-15 Sanyo Electric Co Ltd Semiconductor device
US7649224B2 (en) 2007-12-13 2010-01-19 Sanyo Electric Co., Ltd. DMOS with high source-drain breakdown voltage, small on- resistance, and high current driving capacity
US7705399B2 (en) 2006-02-24 2010-04-27 Sanyo Electric Co., Ltd. Semiconductor device with field insulation film formed therein
CN102097471A (en) * 2009-12-04 2011-06-15 美格纳半导体有限会社 Semiconductor device
US7964915B2 (en) 2006-02-24 2011-06-21 Sanyo Electric Co., Ltd. Semiconductor device having a DMOS structure
US8247295B2 (en) 2007-07-23 2012-08-21 Mitsumi Electric Co., Ltd. DMOS type semiconductor device and method for manufacturing the same
US8546877B2 (en) 2006-09-29 2013-10-01 Semiconductor Components Industries, Llc Semiconductor device
US8558307B2 (en) 2007-12-18 2013-10-15 Sanyo Semiconductor Co., Ltd. Semiconductor device with diffused MOS transistor and manufacturing method of the same
CN105390543A (en) * 2014-08-25 2016-03-09 联发科技股份有限公司 High-voltage metal-oxide-semiconductor transistor device
JP2016207830A (en) * 2015-04-22 2016-12-08 トヨタ自動車株式会社 Insulated gate type switching element and method of controlling the same
JP2016213449A (en) * 2015-05-08 2016-12-15 ローム株式会社 Semiconductor device
CN117080246A (en) * 2023-10-08 2023-11-17 希力微电子(深圳)股份有限公司 Pressure-resistant area with longitudinal super junction sub-layer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101531880B1 (en) * 2008-12-30 2015-06-26 주식회사 동부하이텍 Semiconductor device and method of manufacturing the same

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245517A (en) * 2005-03-07 2006-09-14 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2006261214A (en) * 2005-03-15 2006-09-28 Fuji Electric Device Technology Co Ltd Semiconductor device
US7964915B2 (en) 2006-02-24 2011-06-21 Sanyo Electric Co., Ltd. Semiconductor device having a DMOS structure
US7705399B2 (en) 2006-02-24 2010-04-27 Sanyo Electric Co., Ltd. Semiconductor device with field insulation film formed therein
US8546877B2 (en) 2006-09-29 2013-10-01 Semiconductor Components Industries, Llc Semiconductor device
US8247295B2 (en) 2007-07-23 2012-08-21 Mitsumi Electric Co., Ltd. DMOS type semiconductor device and method for manufacturing the same
US7649224B2 (en) 2007-12-13 2010-01-19 Sanyo Electric Co., Ltd. DMOS with high source-drain breakdown voltage, small on- resistance, and high current driving capacity
US8558307B2 (en) 2007-12-18 2013-10-15 Sanyo Semiconductor Co., Ltd. Semiconductor device with diffused MOS transistor and manufacturing method of the same
JP2009239111A (en) * 2008-03-27 2009-10-15 Sanyo Electric Co Ltd Semiconductor device
CN102097471A (en) * 2009-12-04 2011-06-15 美格纳半导体有限会社 Semiconductor device
US9099557B2 (en) 2009-12-04 2015-08-04 Magnachip Semiconductor, Ltd. Semiconductor device
CN105390543A (en) * 2014-08-25 2016-03-09 联发科技股份有限公司 High-voltage metal-oxide-semiconductor transistor device
JP2016207830A (en) * 2015-04-22 2016-12-08 トヨタ自動車株式会社 Insulated gate type switching element and method of controlling the same
JP2016213449A (en) * 2015-05-08 2016-12-15 ローム株式会社 Semiconductor device
CN117080246A (en) * 2023-10-08 2023-11-17 希力微电子(深圳)股份有限公司 Pressure-resistant area with longitudinal super junction sub-layer

Also Published As

Publication number Publication date
JP4171251B2 (en) 2008-10-22

Similar Documents

Publication Publication Date Title
US6255154B1 (en) Semiconductor device and method of manufacturing the same
JPH0897411A (en) Lateral trench mos fet having high withstanding voltage and its manufacture
US20060001122A1 (en) Semiconductor device and method for manufacturing the same
US7986004B2 (en) Semiconductor device and method of manufacture thereof
JP4171251B2 (en) Semiconductor device and manufacturing method thereof
JPH09246540A (en) Semiconductor device and its manufacture
US8735997B2 (en) Semiconductor device having drain/source surrounded by impurity layer and manufacturing method thereof
JP2001077354A (en) Vertical insulating gate semiconductor device
US7705399B2 (en) Semiconductor device with field insulation film formed therein
JP3448546B2 (en) Semiconductor device and manufacturing method thereof
JPH09213939A (en) Semiconductor device
JP2005101334A (en) Semiconductor device and its manufacturing method
JP4477309B2 (en) High breakdown voltage semiconductor device and manufacturing method thereof
JP2010118622A (en) Semiconductor device and method of manufacturing the same
JP2004158680A (en) Semiconductor device and its fabricating process
JP3436220B2 (en) Vertical semiconductor device
JP4131647B2 (en) Manufacturing method of semiconductor device
JP2004039773A (en) Semiconductor device and its manufacturing method
JP4677166B2 (en) Semiconductor device and manufacturing method thereof
JP2004022769A (en) Lateral high breakdown voltage semiconductor device
US7335549B2 (en) Semiconductor device and method for fabricating the same
JP2009302114A (en) Semiconductor device and its manufacturing method
JPH10163338A (en) Semiconductor device and its manufacturing method
JPH11204786A (en) Semiconductor device provided with high breakdown voltage insulating gate type field effect transistor and manufacture thereof
JP2001060634A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050630

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070907

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071030

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080314

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080507

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080715

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080808

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120815

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130815

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees