CN115084237B - Silicon carbide trench MOSFET transistor with dense cells and method of fabricating the same - Google Patents

Silicon carbide trench MOSFET transistor with dense cells and method of fabricating the same Download PDF

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CN115084237B
CN115084237B CN202211010354.5A CN202211010354A CN115084237B CN 115084237 B CN115084237 B CN 115084237B CN 202211010354 A CN202211010354 A CN 202211010354A CN 115084237 B CN115084237 B CN 115084237B
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doping
region
doped region
epitaxial layer
silicon carbide
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CN115084237A (en
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崔京京
章剑锋
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Ruineng Semiconductor Technology Co ltd
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Ruineng Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

The application discloses a silicon carbide groove type MOSFET transistor with dense cells and a manufacturing method thereof, and relates to the technical field of semiconductor devices. A silicon carbide trench MOSFET transistor includes: the silicon carbide substrate comprises a first surface, wherein an epitaxial layer of the first doping type is arranged on the first surface; a plurality of cell structures disposed within the epitaxial layer, the cell structures including a gate trench structure; and a clamping protection structure is arranged in the peripheral area of each cellular structure and is used for protecting the grid oxide layer at the corner of the grid groove structure. According to the transistor, the electric field intensity born by the grid oxide layer at the corner of the grid groove structure can be clamped below a safety value, so that the corner of the grid groove structure can be protected, and the reliability of the transistor is improved.

Description

Silicon carbide trench MOSFET transistor with dense cells and method of fabricating the same
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a silicon carbide trench type MOSFET transistor with dense cells and a manufacturing method thereof.
Background
A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a voltage-type control device, and has a simple driving circuit, low driving power, a fast switching speed, and a high operating frequency.
Silicon carbide MOSFETs can be classified into planar structures and trench structures according to different gate layout directions. The trench structure has a more significant advantage in the conduction performance due to the higher cell density. However, for the trench-type silicon carbide transistor, the biggest challenge is that the gate oxide layer at the corner of the trench is very vulnerable to large electric field intensity, which affects the reliability of the device.
Disclosure of Invention
Embodiments of the present application provide a silicon carbide trench MOSFET transistor with dense cells and a method for manufacturing the same, which can reduce an electric field strength at a corner of a gate trench structure, and further can protect the corner of the gate trench structure, thereby improving reliability of the transistor.
In a first aspect, an embodiment of the present application provides a silicon carbide trench MOSFET transistor having dense cells, including:
the silicon carbide substrate comprises a first surface, wherein an epitaxial layer of a first doping type is arranged on the first surface;
a plurality of cell structures disposed within the epitaxial layer, the cell structures including a gate trench structure;
and the peripheral area of each cellular structure is provided with a clamping protection structure, and the clamping protection structure is used for clamping the electric field intensity borne by the grid oxide layer at the corner of the grid groove structure below a safety value. In some alternative embodiments, the cellular structure comprises at least two subcell structures arranged in parallel;
the subcell structure includes:
a gate trench structure disposed within the epitaxial layer;
a source metal structure disposed on a surface of the epitaxial layer distal from the first surface;
the first doping region of the first doping type is arranged in a side peripheral region, close to the top, of the gate trench structure;
the well region is arranged in the peripheral region of the first doping region and is spaced from the grid groove structure and is of a second doping type; the first doping type is opposite to the second doping type.
In some optional embodiments, the clamp protection structure comprises:
a second doped region of a second doping type disposed within the epitaxial layer, the second doped region having a depth greater than a depth of the gate trench structure;
a first metal structure disposed on a surface of the second doped region;
and the third doped region is arranged in the second doped region and is in contact with the first metal structure.
In some alternative embodiments, the third doped region is of the second doping type.
In some alternative embodiments, the third doped region is of the first doping type.
In some optional embodiments, the clamp protection structure further includes:
at least one fourth doping region of the second doping type arranged on one side, close to the first surface, of the second doping region;
a fifth doped region of the first doping type disposed at a bottom of the second doped region.
In some optional embodiments, the clamp protection structure comprises:
a sixth doped region of the second doping type disposed within the epitaxial layer, a depth of the sixth doped region being greater than a depth of the gate trench structure;
a second metal structure disposed on a surface of the sixth doped region;
the PN junction structure is arranged in the sixth doped region and is close to one side of the second metal structure;
the third metal structure is arranged on one side, close to the first surface, of the PN junction structure;
and the seventh doping area of the first doping type is arranged on one side, close to the first surface, of the third metal structure.
In some optional embodiments, the PN junction structure comprises:
a first doping structure and a second doping structure disposed between the second metal structure and the third metal structure, the first doping structure being of the first doping type, the second doping structure being of the second doping type;
the contact surface between the first doping structure and the second doping structure is parallel to the first surface, the first doping structure is arranged on one side close to the third metal structure, and the second doping structure is arranged on one side close to the second metal structure.
In a second aspect, embodiments of the present application provide a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells, including:
providing a silicon carbide substrate of a first doping type, wherein the silicon carbide substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface;
forming a cellular structure in the epitaxial layer, wherein the cellular structure comprises a grid groove structure;
and forming a clamping protection structure at the peripheral region of each cellular structure, wherein the clamping protection structure is used for clamping the electric field intensity borne by the grid oxide layer at the corner of the grid groove structure below a safe value.
In some optional embodiments, the forming of the cell structure within the epitaxial layer includes:
forming a first doping region of the first doping type on the surface of the epitaxial layer far away from the first surface;
forming a well region of a second doping type arranged at an interval with the grid groove structure in the peripheral region of the first doping region;
forming a first groove structure in the epitaxial layer;
forming a gate trench structure in the first trench structure;
and forming a source metal structure on the surface of the epitaxial layer far away from the first surface.
The embodiment of the application provides a silicon carbide trench type MOSFET transistor with dense unit cells, which can comprise: the structure comprises a plurality of cell structures arranged in an epitaxial layer and a clamping protection structure arranged at the peripheral region of the cell structures. The electric field intensity borne by the gate oxide layer at the corner of the gate trench structure can be rapidly increased along with the increase of the blocking voltage borne by the transistor, and the higher the blocking voltage is, the more easily the gate oxide layer at the corner of the gate trench structure is subjected to breakdown failure. However, when the blocking voltage born by the transistor reaches the breakdown voltage of the lower clamping protection structure, the clamping protection structure is broken down, so that the transistor is broken down in advance, the electric field intensity at the corner of the grid groove structure can be clamped below a safe value, the grid oxide layer at the corner of the grid groove structure can be protected, and the reliability of the transistor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of one configuration of an embodiment of a silicon carbide trench MOSFET transistor with dense cells as provided herein;
FIG. 2 is a schematic diagram of another structure of an embodiment of a silicon carbide trench MOSFET transistor with dense cells as provided herein;
FIG. 3 is a schematic diagram of yet another structure of an embodiment of a silicon carbide trench MOSFET transistor with dense cells as provided herein;
FIG. 4 is a schematic diagram of yet another configuration of an embodiment of a silicon carbide trench MOSFET transistor with dense cells as provided herein;
FIG. 5 is a schematic flow chart diagram illustrating an embodiment of a method for fabricating a silicon carbide trench MOSFET transistor with dense cells as provided herein;
FIG. 6 is a schematic cross-sectional view of a silicon carbide substrate provided herein;
FIG. 7 is a schematic cross-sectional view of a first doped region formed according to the present disclosure;
fig. 8 is a schematic cross-sectional structure diagram of a well region formed according to the present application;
fig. 9 is a schematic cross-sectional structure diagram of a first trench structure formed as provided herein;
fig. 10 is a schematic cross-sectional structure diagram of a gate trench structure formed according to the present application;
fig. 11 is a schematic cross-sectional structure diagram of a source metal structure formed according to the present application;
fig. 12 is a schematic cross-sectional structure diagram of forming a second doped region and a third doped region as provided herein;
FIG. 13 is a cross-sectional structural schematic diagram of the formation of a first metal structure provided herein;
FIG. 14 is a schematic cross-sectional view of a fourth doped region formed according to the present application;
FIG. 15 is a schematic cross-sectional view of a fifth doped region formed according to the present application;
fig. 16 is a schematic cross-sectional structure diagram of forming a second trench structure provided in the present application;
FIG. 17 is a schematic cross-sectional view of a sixth doped region formed as provided herein;
FIG. 18 is a schematic cross-sectional view of a seventh doped region formed according to the present application;
FIG. 19 is a schematic cross-sectional structure diagram of the third trench structure provided herein;
FIG. 20 is a schematic cross-sectional structure diagram of forming a third metal structure provided herein;
fig. 21 is a schematic cross-sectional structure diagram of forming a PN junction structure provided in the present application;
fig. 22 is a schematic cross-sectional structure diagram of forming a second metal structure provided herein.
Description of reference numerals:
1: a silicon carbide substrate; 11: a first surface; 12: a second surface.
2: an epitaxial layer; 21: a cellular structure; 211: a subcellular structure; 2111: a gate trench structure; 21111: a gate structure; 21112: a gate oxide layer; 2112: a source metal structure; 2113: a first doped region; 2114: a well region; 22: a clamp protection structure; 221: a second doped region; 2211: a first metal structure; 2212: a third doped region; 2213: a fourth doped region; 2214: a fifth doped region; 222: a sixth doped region; 2221: a second metal structure; 2222: a PN junction structure; 22221: a first doped structure; 22222: a second doped structure; 2223: a third metal structure; 2224: a seventh doped region; 23: a first trench structure; 25: a second trench structure; 26: and a third trench structure.
3: and a drain structure.
In the drawings, like parts are given like reference numerals. The figures are not drawn to scale.
Detailed Description
Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
In order to solve the problems of the prior art, embodiments of the present application provide a silicon carbide trench MOSFET transistor having dense cells and a method of manufacturing the same. The following first describes a silicon carbide trench MOSFET transistor with dense cells according to an embodiment of the present application.
Fig. 1 is a schematic structural diagram of an embodiment of a silicon carbide trench MOSFET transistor with dense cells according to an embodiment of the present application.
As shown in fig. 1, a silicon carbide trench MOSFET transistor with dense cells provided in an embodiment of the present application may include:
the silicon carbide substrate comprises a silicon carbide substrate 1 of a first doping type, wherein the silicon carbide substrate 1 comprises a first surface 11, and an epitaxial layer 2 of the first doping type is arranged on the first surface 11;
a plurality of cell structures 21 disposed within the epitaxial layer 2, the cell structures 21 including gate trench structures 2111;
a clamp protection structure 22 is disposed in a peripheral region of each cell structure 21, and the clamp protection structure 22 is used to ensure that a transistor is broken down in advance, so as to clamp an electric field strength borne by the gate oxide layer 21112 at a corner of the gate trench structure 2111 to a safe value or less.
The embodiment of the application provides a silicon carbide trench type MOSFET transistor with dense unit cells, which can comprise: the structure comprises a plurality of cell structures arranged in an epitaxial layer and a clamping protection structure arranged at the peripheral region of the cell structures. The electric field intensity borne by the gate oxide layer at the corner of the gate trench structure can be rapidly increased along with the increase of the blocking voltage borne by the transistor, and the higher the blocking voltage is, the more easily the gate oxide layer at the corner of the gate trench structure is subjected to breakdown failure. However, when the blocking voltage born by the transistor reaches the breakdown voltage of the lower clamp protection structure, the clamp protection structure is broken down, so that the transistor is broken down in advance, the electric field intensity at the corner of the gate trench structure can be clamped below a safe value, the corner of the gate trench structure can be protected, and the reliability of the transistor is improved.
In this embodiment, the first doping type may be N-type, and the second doping type may be P-type. The silicon carbide substrate 1 of the first doping type may be an N-type silicon carbide substrate; the epitaxial layer 2 of the first doping type may be an epitaxial layer of the N type.
The number of the cell structures 21 included in the epitaxial layer 2 may be set according to actual requirements, and is not limited herein. For example, the number of the cell structures 21 may be 100.
The clamp protection structure 22 may be a structure capable of clamping the electric field strength borne by the gate oxide layer 21112 at the corner of the gate trench structure 2111 to a safe value or less.
In some alternative embodiments, the silicon carbide substrate 1 may further include a second surface 12 opposite the first surface 11, the second surface 12 being provided with the drain structure 3.
In some alternative embodiments, the cellular structure 21 may include at least two sub-cellular structures 211 arranged in parallel;
the subcell structure 211 may include:
a gate trench structure 2111 disposed within the epitaxial layer 2;
a source metal structure 2112 disposed on a surface of the epitaxial layer 2 remote from the first surface 11;
a first doping region 2113 of the first doping type disposed in a side peripheral region of the gate trench structure 2111 near the top;
a well region 2114 of the second doping type disposed in a peripheral region of the first doping region 2113 and spaced apart from the gate trench structure 2111; the first doping type is opposite to the second doping type.
In the present embodiment, the cellular structure 21 may include at least two sub-cellular structures 211 arranged in parallel, and it is understood that the cellular structure 21 may include at least two sub-cellular structures 211 in a direction parallel to the first surface 11.
The number of the sub-cell structures 211 in each cell structure 21 may be set according to practical situations, and is not limited herein. Alternatively, each of the cell structures 21 may include four sub-cell structures 211 arranged in parallel.
In this embodiment, the first doping region 2113 of the first doping type may be an N-type first doping region, and the well region 2114 of the second doping type may be a P-type well region 2114.
The peripheral region of the first doped region 2113 may be understood as a region of the side of the first doped region 2113 away from the gate trench structure 2111.
The first doping type is opposite to the second doping type, it being understood that the first doping type is one of an N-type and a P-type and the second doping type is the other of an N-type and a P-type. For example, when the first doping type is N-type, the second doping type is P-type.
The dimensions (pitch) of the subcell structure 211, the gate trench structure 2111, the first doped region 2113 and the well region 2114 may be set according to practical situations, and are not limited herein.
Illustratively, the length of the subcell structure 211 in the direction parallel to the silicon carbide substrate 1 may be 2.4um; the length of the gate trench structure 2111 in the direction parallel to the silicon carbide substrate 1 may be 1.0um, and the length of the gate trench structure 2111 embedded in the epitaxial layer 2 in the direction perpendicular to the silicon carbide substrate 1 may be 0.9um; the length of the first doped region 2113 in a direction parallel to the silicon carbide substrate 1 may be 0.4um; the length of the well region 2114 in the direction parallel to the silicon carbide substrate 1 may be 0.6um, and the length of the well region 2114 in the direction perpendicular to the silicon carbide substrate 1 may be 1.2um.
Alternatively, in a direction perpendicular to the first surface 11, the length of the well region 2114 may be greater than the length of the gate structure 21111 in the gate trench structure 2111; the length of the well region 2114 may also be less than or equal to the length of the gate structure 21111 in the gate trench structure 2111. That is, the depth of the well region 2114 may be greater than the depth of the gate trench structure 2111, and the depth of the well region 2114 may also be less than the depth of the gate trench structure 2111.
In this embodiment mode, when the length of the well region 2114 in the direction perpendicular to the silicon carbide substrate 1 may be longer than the length of the gate structure 21111 in the gate trench structure 2111 in the direction perpendicular to the silicon carbide substrate 1 when in the blocking mode, the well region 2114 can form a depletion region which can shield part of the electric field intensity at the corner of the gate trench structure 2111, so that the reliability of the transistor can be improved.
In the present embodiment, due to the clamp protection structure 22, the transistor does not need to design a deep P-type well region 2114 with a certain width to protect the corner of the gate trench structure 2111, so that the size of the sub-cell structure 211 can be reduced, and thus the silicon carbide trench MOSFET transistor can be formed with dense cells compared to the related art.
In some alternative embodiments, the clamp protection structure 22 may include:
a second doping region 221 of the second doping type disposed within the epitaxial layer 2, a depth of the second doping region 221 being greater than a depth of the gate trench structure 2111;
a first metal structure 2211 disposed on a surface of the second doped region 221;
a third doped region 2212 disposed within the second doped region 221 and in contact with the first metal structure 2211.
In this embodiment, the second doping region 221 of the second doping type and the epitaxial layer 2 of the first doping type may form a PN junction avalanche diode, the electric field strength borne by the corner of the gate trench structure may rapidly increase with the increase of the blocking voltage borne by the transistor, and the higher the blocking voltage, the more likely the gate oxide layer at the corner of the gate trench structure is to undergo breakdown failure. When the blocking voltage born by the transistor reaches the breakdown voltage of the PN junction avalanche diode which is lower, the PN junction avalanche diode is broken down, so that the transistor is broken down in advance, the electric field intensity at the corner of the grid groove structure can be clamped below a safety value, the corner of the grid groove structure can be protected, and the reliability of the transistor is improved.
The second doping region 221 of the second doping type may be a P-type second doping region 221.
The depth of the second doping region 221 is greater than the depth of the gate trench structure 2111, and it can be understood that the length of the second doping region 221 in the direction perpendicular to the first surface 11 is greater than the length of the gate trench structure 2111 in the direction perpendicular to the first surface 11, that is, in the direction perpendicular to the first surface 11, the length of the second doping region 221 is greater than the length of the gate trench structure 2111.
Optionally, the depth of the second doped region 221 is greater than the depth of the well region 2114. That is, in the direction perpendicular to the first surface 11, the length of the second doped region 221 is greater than the length of the well region 2114.
In some alternative embodiments, the third doped region 2212 may be of the second doping type. For example, the third doped region 2212 may be P-type.
In this embodiment, by providing the third doped region 2212 in contact with the first metal structure 2211 in the second doped region 221, a good ohmic contact can be formed with the first metal structure 2211, and contact resistance can be reduced.
As shown in fig. 2, in the case that the third doped region 2212 is of the second doping type, that is, the third doped region 2212 is of the P type, the clamp protection structure 22 may further include:
at least one fourth doping region 2213 of the second doping type disposed on a side of the second doping region 221 close to the first surface 11;
a fifth doped region 2214 of the first doping type disposed at the bottom of the second doped region 221.
The fourth doped region 2213 of the second doping type may be a fourth doped region 2213 of a P type, and the fifth doped region 2214 of the first doping type may be a fifth doped region 2214 of an N type.
The doping concentration of the fifth doping region 2214 is the same as the doping concentration of the second doping region 221. The fifth doped region 2214 can be considered as a portion of the second doped region 221.
The distance between the fourth doped region 2213 and the first surface 11 is smaller than the distance between the second doped region 221 and the first surface 11.
It will be appreciated that because the electric field strength is greatest where the curvature of the PN junction changes most, avalanche breakdown will generally occur where the curvature of the PN junction changes most, i.e., avalanche breakdown will occur at the corners a and F of the second doped region 221 near the first surface 11. Avalanche energy (ea) is a main index for evaluating the avalanche resistance of a device, wherein ea =1/2 × L × I 2 And I is the maximum current value passed by the device, and L is the size of the line inductance. The avalanche current conduction path of the device when avalanche breakdown occurs is increased, and the avalanche resistance of the device can be obviously improved.
In this embodiment, at least one fourth doping region 2213 of the second doping type is disposed on the side of the second doping region 221 close to the first surface 11, the electric field intensity of the fourth doping region 2213 at the corners C and D close to the first surface 11 is increased, and the avalanche state can be achieved at the same time as the corners of the second doping region 221 close to the first surface 11. In addition, the fifth doped region 2214 with high concentration and the first doping type is disposed at the bottom of the second doped region 221, and according to the poisson equation, the electric field intensities at the point B and the point E can be increased, so that a state of simultaneous breakdown with the point a and the point F is achieved. That is to say, in the embodiment of the present application, by increasing the number of avalanche breakdown points (such as points B, C, D, and E), the avalanche current conduction path is increased, and the avalanche resistance of the device is further improved.
Alternatively, in the case that the clamp protection structure 22 includes at least two fourth doping regions 2213 of the second doping type disposed on the side of the second doping region 221 close to the first surface 11, the fourth doping regions 2213 are disposed at intervals.
As shown in fig. 3, taking the example that the clamp protection structure 22 includes two fourth doping regions 2213 of the second doping type as an example, the clamp protection structure 22 may further include three fourth doping regions 2213 of the second doping type, or four fourth doping regions 2213 of the second doping type, and the like, which is not limited herein.
As shown in fig. 1, in some alternative embodiments, the third doped region 2212 may be of the first doping type.
The third doped region 2212 may be an N-type doped region with a high ion doping concentration. The ion doping concentration of the second doping region 221 is less than that of the third doping region 2212.
In this embodiment, when the third doped region 2212 is N-type, the clamp protection structure 22 is an NPN structure formed by the N-type third doped region 2212, the P-type second doped region 221 and the N-type epitaxial layer 2, and may be a punch-through structure. By setting the ion doping concentration of the second doping region 221 to be close to the ion doping concentration of the N-type epitaxial layer 2, under a certain blocking voltage state, the electric field lines can completely pass through the second doping region 221, and the electric field strength of the whole second doping region 221 is not zero, so that electrons can rapidly pass through the second doping region 221 under the action of the electric field. Accordingly, if the ion doping concentration of the second doping region 221 is much greater than that of the N-type epitaxial layer 2, the electric field strength in the second doping region 221 will rapidly drop to zero.
In the related technology, the punch-through breakdown has the advantages that no hole-electron pair is generated during the breakdown, the breakdown process is not violent, and the device structure is not easily damaged by heat; the disadvantage is that the punch-through voltage is less than the avalanche breakdown voltage, which is avoided in the device design in the art, but it is the clamp protection 22 that breaks down earlier that is required in this application.
In addition, by providing the high concentration N-type third doped region 2212 in contact with the first metal structure 2211 in the second doped region 221, electrons can be continuously provided during punch-through breakdown. In addition, for silicon carbide (SiC) materials, the process of forming ohmic contacts on N-type doped regions is more mature than forming ohmic contacts on P-type doped regions. In the related art, the contact resistivity of the silicon carbide N-type ohmic contact is generally 10 -6 Cm2, while the contact resistivity of silicon carbide P-type ohmic contacts is typically 10 -4 Cm2, it can be seen that the contact resistivity of the N-type ohmic contact is much smaller than that of the P-type ohmic contact, thereby reducing the resistance on the current path when breakdown occurs.
As shown in fig. 4, in some alternative embodiments, the clamp protection structure 22 may further include:
a sixth doped region 222 of the second doping type disposed within the epitaxial layer 2, a depth of the sixth doped region 222 being greater than a depth of the gate trench structure 2111;
a second metal structure 2221 disposed on a surface of the sixth doped region 222;
a PN junction structure 2222 disposed in the sixth doped region 222 and close to one side of the second metal structure 2221;
a third metal structure 2223 disposed on a side of the PN junction structure 2222 adjacent to the first surface 11;
a seventh doped region 2224 of the first doping type is disposed at a side of the third metal structure 2223 close to the first surface 11.
The depth of the sixth doped region 222 is greater than the depth of the gate trench structure 2111, and it can be understood that the length of the sixth doped region 222 is greater than the length of the gate trench structure 2111 in the direction perpendicular to the first surface 11.
In the present embodiment, the seventh doping region 2224 of the first doping type, the sixth doping region 222 of the second doping type and the epitaxial layer 2 of the first doping type constitute an NPN structure.
It can be understood that by providing the P-type sixth doped region 222 with a lower ion doping concentration, under a certain blocking voltage state, the electric field lines can completely penetrate through the sixth doped region 222, since the third metal structure 2223 connects the PN junction structure 2222 and the seventh doped region 2224, the potential of the PN junction structure 2222 is equal to the potential of the seventh doped region 2224, so that the potential of the sixth doped region 222 increases, and when the potential of the sixth doped region 222 increases to a certain value (for example, from 0V to 30V), the breakdown voltage of the PN junction structure 2222 is reached, so that the entire PN junction structure 2222 is broken down, and the voltage of the entire silicon carbide trench MOSFET transistor is clamped below a safe value, so that the electric field strength at the corner of the gate trench structure is also clamped below the safe value, so that the corner of the gate trench structure can be protected, and the reliability of the transistor can be improved.
Further, a PN junction punch-through breakdown formed by the P-type sixth doped region 222 and the N-type epitaxial layer 2 has a relatively large leakage current before the breakdown occurs, and the breakdown curve is relatively soft. By providing the PN junction structure 2222 on the side of the third metal structure 2223 away from the first surface 11, leakage current before punch-through breakdown can be reduced, and loss of the silicon carbide trench MOSFET transistor in the off state can be reduced.
Alternatively, the PN junction structure 2222 may be a polysilicon zener diode structure.
In some alternative embodiments, the PN junction structure 2222 may include:
a first doped structure 22221 and a second doped structure 22222 disposed between the second metal structure 2221 and the third metal structure 2223, the first doped structure 22221 being of a first doping type, the second doped structure 22222 being of a second doping type;
a contact surface between the first doped structure 22221 and the second doped structure 22222 is parallel to the first surface 11, and the first doped structure 22221 is disposed at a side close to the third metal structure 2223, and the second doped structure 22222 is disposed at a side close to the second metal structure 2221.
In the present embodiment, the first doping structure 22221 of the first doping type is an N-type first doping structure 22221; the second doping structure 22222 of the second doping type is a second doping structure 22222 of a P-type.
In the embodiment of the present application, the shape of each doped region is a rectangle, but not limited to this, and the shape of each doped region may be set according to actual situations.
It is noted that the first doping type is N-type and the second doping type is P-type in the present embodiment. However, in actual practice, the silicon carbide substrate 1 is not limited to N-type but may be P-type. When the silicon carbide substrate 1 is of a P-type, the conductivity types of the epitaxial layer 2, the well region 2114, the first doped region 2113, and the like are changed accordingly.
Based on the silicon carbide trench MOSFET transistor with dense cells provided in the above embodiments, the present application also provides a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells. A method of manufacturing a silicon carbide trench MOSFET transistor having dense cells will be described below.
Fig. 5 shows a schematic flow chart diagram of an embodiment of a method of fabricating a silicon carbide trench MOSFET transistor with dense cells as provided herein.
As shown in fig. 5, the method of manufacturing the silicon carbide trench MOSFET transistor having dense cells may include S501 to S503. Referring to fig. 6 to 22, fig. 6 to 22 are schematic cross-sectional views corresponding to a series of processes for manufacturing a silicon carbide trench MOSFET transistor with dense cells according to the present invention.
S501, providing a silicon carbide substrate 1 of a first doping type, wherein the silicon carbide substrate 1 comprises a first surface 11, and an epitaxial layer 2 of the first doping type is arranged on the first surface 11.
In the present embodiment, the silicon carbide substrate 1 of the first doping type is an N-type silicon carbide substrate 1.
As shown in fig. 6, in some alternative embodiments, a silicon carbide substrate 1 of N-type is first provided, and then epitaxy is performed on the silicon carbide substrate 1 to form an epitaxial layer 2 of N-type.
S502, forming a cell structure 21 in the epitaxial layer 2, where the cell structure 21 includes a gate trench structure 2111.
In some alternative embodiments, forming the cell structure 21 within the epitaxial layer 2 may include:
forming a first doped region 2113 of the first doping type on the surface of the epitaxial layer 2 remote from the first surface 11;
forming a well region 2114 of the second doping type spaced apart from the gate trench structure 2111 in a peripheral region of the first doping region 2113;
forming a first trench structure 23 within the epitaxial layer 2;
forming a gate trench structure 2111 within the first trench structure 23;
a source metal structure 2112 is formed on the surface of the epitaxial layer 2 remote from the first surface 11.
Alternatively, as shown in fig. 7, forming a first doped region 2113 of the first doping type on the surface of the epitaxial layer 2 away from the first surface 11 may include:
ion doping of the first doping type is performed on the surface of the epitaxial layer 2 remote from the first surface 11, forming first doped regions 2113 of the first doping type.
Specifically, the first doped region 2113 of the first doping type may be a first doped region 2113 of an N-type.
Illustratively, N-type ions are implanted into the surface of the epitaxial layer 2 remote from the first surface 11 through a reticle and photolithography process to form a first doped region 2113 of the first doping type
Optionally, as shown in fig. 8, forming a well region 2114 of the second doping type in a peripheral region of the first doping region 2113 and spaced apart from the gate trench structure 2111 may include:
ion doping of the second doping type is performed in a peripheral region of the first doping region 2113, and a well region 2114 of the second doping type is formed to be spaced apart from the gate trench structure 2111.
Specifically, the well region 2114 of the second doping type may be a well region 2114 of a P type.
Illustratively, P-type ions are implanted into the peripheral region of the first doped region 2113 through a mask and photolithography processes to form a P-type well region 2114 spaced apart from the gate trench structure 2111.
Optionally, as shown in fig. 9, forming the first trench structure 23 in the epitaxial layer 2 may include:
a trench etch is performed down the surface of the epitaxial layer 2 remote from the first surface 11 to form a first trench structure 23 within the epitaxial layer 2.
Specifically, a mask may be used to perform a trench etching on the surface of the epitaxial layer 2 away from the first surface 11, so as to form the first trench structure 23 in the epitaxial layer 2.
Optionally, as shown in fig. 10, forming a gate trench structure 2111 in the first trench structure 23 may include:
oxidizing the surface of the first trench structure 23 to form a gate oxide layer 21112;
a gate structure 21111 is formed on the surface of the gate oxide layer 21112.
Illustratively, the gate oxide layer 21112 is formed on the surface of the first trench structure 23 by an oxidation or deposition process.
Optionally, as shown in fig. 11, forming a source metal structure 2112 on a surface of the epitaxial layer 2 away from the first surface 11 may include:
metal is deposited on the surface of the epitaxial layer 2 remote from the first surface 11 to form a source metal structure 2112.
Illustratively, source metal structures 2112 are formed on the surface of epitaxial layer 2 remote from first surface 11 by photolithography and metallization.
S503, forming a clamp protection structure 22 in the peripheral region of each cell structure 21, wherein the clamp protection structure 22 is used for clamping the electric field strength borne by the gate oxide layer 21112 at the corner of the gate trench structure 2111 to be below a safe value.
In some alternative embodiments, as shown in fig. 12 and 13, forming the clamp protection structure 22 at the peripheral region of each cell structure 21 may include:
forming a second doping region 221 of the second doping type within the epitaxial layer 2;
forming a third doped region 2212 within the second doped region 221;
a first metal structure 2211 is formed at the surface of the third doped region 2212.
Illustratively, the second doped region 221 of P-type may be formed by a mask and photolithography process with higher implantation energy, and high dose implantation to form a third doped region 2212 within the second doped region 221, and metal may be deposited on the surface of the third doped region 2212 to form the first metal structure 2211.
In some alternative embodiments, the third doped region 2212 may be of the second doping type, i.e., the third doped region 2212 may be P-type.
As shown in fig. 14 to 15, in some alternative embodiments, forming the clamping protection structure 22 at the peripheral region of each cell structure 21 may include:
forming at least one fourth doping region 2213 of the second doping type on the side of the second doping region 221 close to the first surface 11;
a fifth doped region 2214 of the first doping type is formed at the bottom of the second doped region 221.
As an example, P-type ion doping is performed on the side of the second doping region 221 close to the first surface 11 to form a P-type fourth doping region 2213; n-type ion doping is performed at the bottom of the second doping region 221 to form a fifth doping region 2214 of N-type.
As another example, as shown in fig. 14 to 16, at least one fourth doping region 2213 of the second doping type is formed on the second doping region 221 near the first surface 11, and it is also possible to form a second trench structure 25 in the epitaxial layer 2; performing P-type ion doping on the second doping region 221 near the first surface 11 by using the second trench structure 25 to form a P-type fourth doping region 2213; n-type ion doping is performed on the second trench structure 25 to form a fifth doped region 2214 of N-type.
In other alternative embodiments, the third doped region 2212 may be of the first doping type, i.e., the third doped region 2212 may be N-type.
In some alternative embodiments, as shown in fig. 17 to 22, forming the clamp protection structure 22 in the peripheral region of each cell structure 21 may include:
forming a sixth doping region 222 of the second doping type in the epitaxial layer 2, wherein the depth of the sixth doping region 222 is greater than the depth of the gate trench structure 2111;
forming a seventh doped region 2224 of the first doping type within the sixth doped region 222;
forming a third trench structure 26 in the sixth doped region 222;
forming a third metal structure 2223 at the bottom of the third trench structure 26;
forming a PN junction structure 2222 on a side of the third metal structure 2223 away from the first surface 11;
a second metal structure 2221 is formed on a side of the PN junction structure 2222 remote from the first surface 11.
Illustratively, P-type ions are doped in the sixth doped region 222 to form a P-type sixth doped region 222; performing N-type ion doping in the sixth doped region 222 to form a seventh doped region 2224 of N-type; etching in the sixth doped region 222 to form a third trench structure 26; depositing metal at the bottom of the third trench structure 26 to form a third metal structure 2223; depositing a polysilicon material in the third trench structure 26 to form a PN junction structure 2222 on a side of the third metal structure 2223 away from the first surface 11; metal is deposited on the side of the PN junction structure 2222 away from the first surface 11 to form a second metal structure 2221.
Further, forming the PN junction structure 2222 on a side of the third metal structure 2223 away from the first surface 11 may include:
forming a first doping structure 22221 of the first doping type on a side of the third metal structure 2223 away from the first surface 11;
a second doping structure 22222 of the second doping type is formed at a side of the first doping structure 22221 remote from the first surface 11.
Illustratively, N-type ion doping is performed on a side of the third metal structure 2223 away from the first surface 11 to form a first doped structure 22221 of N-type;
p-type ions are doped on the first doping structure 22221 away from the first surface 11 to form a P-type second doping structure 22222. As shown in fig. 1, the silicon carbide substrate 1 may further include a second surface 12 opposite the first surface 11, the drain structure 3 being formed at the second surface 12.
It is noted that the first doping type is N-type and the second doping type is P-type in the present embodiment. However, in actual practice, the silicon carbide substrate 1 is not limited to N-type but may be P-type. When the silicon carbide substrate 1 is of a P-type, the conductivity types of the epitaxial layer 2, the well region 2114, the first doped region 2113, and the like are changed accordingly.
With regard to the method of manufacturing the silicon carbide trench MOSFET transistor having dense cells in the above-described embodiment, the respective structures and advantageous effects thereof have been described in detail in the embodiment related to the silicon carbide trench MOSFET transistor having dense cells, and will not be described in detail here.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims (6)

1. A silicon carbide trench MOSFET transistor having dense cells, comprising:
the silicon carbide substrate comprises a first surface, wherein an epitaxial layer of a first doping type is arranged on the first surface;
a plurality of cell structures disposed within the epitaxial layer, the cell structures including a gate trench structure;
a clamping protection structure is arranged in the peripheral area of each cellular structure and used for clamping the electric field intensity borne by the grid oxide layer at the corner of the grid groove structure below a safety value;
the clamp protection structure comprises:
a sixth doped region of the second doping type disposed within the epitaxial layer, a depth of the sixth doped region being greater than a depth of the gate trench structure;
a second metal structure disposed on a surface of the sixth doped region;
the PN junction structure is arranged in the sixth doped region and is close to one side of the second metal structure;
the third metal structure is arranged on one side, close to the first surface, of the PN junction structure;
a seventh doped region of the first doping type disposed on a side of the third metal structure near the first surface;
and the third metal structure is in direct contact with the PN junction structure and the seventh doped region.
2. The silicon carbide trench MOSFET transistor with densely packed cells of claim 1, wherein the cell structure comprises at least two sub-cell structures arranged in parallel;
the subcell structure includes:
a gate trench structure disposed within the epitaxial layer;
a source metal structure disposed on a surface of the epitaxial layer distal from the first surface;
the first doping region of the first doping type is arranged in a side peripheral region, close to the top, of the gate trench structure;
the well region is arranged in the peripheral region of the first doping region and is spaced from the grid groove structure;
the first doping type is opposite to the second doping type.
3. The silicon carbide trench MOSFET transistor with dense cells of claim 1, wherein the PN junction structure comprises:
a first doped structure and a second doped structure disposed between the second metal structure and the third metal structure, the first doped structure being the first doping type, the second doped structure being the second doping type;
the contact surface between the first doping structure and the second doping structure is parallel to the first surface, the first doping structure is arranged on one side close to the third metal structure, and the second doping structure is arranged on one side close to the second metal structure.
4. A silicon carbide trench MOSFET transistor having dense cells, comprising:
the silicon carbide substrate comprises a first surface, wherein an epitaxial layer of a first doping type is arranged on the first surface;
a plurality of cell structures disposed within the epitaxial layer, the cell structures including a gate trench structure;
a clamping protection structure is arranged in the peripheral area of each cellular structure and is used for clamping the electric field intensity borne by the grid oxide layer at the corner of the grid groove structure below a safety value;
the clamp protection structure comprises:
a second doped region of a second doping type disposed within the epitaxial layer, the second doped region having a depth greater than a depth of the gate trench structure;
a first metal structure disposed on a surface of the second doped region;
a third doped region disposed within the second doped region and in contact with the first metal structure;
the third doping region is of the second doping type;
the clamp protection structure further comprises:
at least one fourth doping region of the second doping type arranged on one side, close to the first surface, of the second doping region;
a fifth doped region of the first doping type disposed at a bottom of the second doped region.
5. A method of fabricating a silicon carbide trench MOSFET transistor having dense cells, comprising:
providing a silicon carbide substrate of a first doping type, wherein the silicon carbide substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface;
forming a cellular structure in the epitaxial layer, wherein the cellular structure comprises a grid groove structure;
forming a clamping protection structure in the peripheral area of each cell structure, wherein the clamping protection structure is used for clamping the electric field intensity borne by the grid oxide layer at the corner of the grid groove structure below a safety value;
forming a clamp protection structure at a peripheral region of each of the cell structures, including:
forming a sixth doped region of the second doping type in the epitaxial layer, wherein the depth of the sixth doped region is greater than that of the gate trench structure;
forming a seventh doped region of the first doping type in the sixth doped region;
forming a third groove structure in the sixth doping area;
forming a third metal structure at the bottom of the third trench structure;
forming a PN junction structure on one side of the third metal structure far away from the first surface;
forming a second metal structure on one side of the PN junction structure far away from the first surface;
and the third metal structure is in direct contact with the PN junction structure and the seventh doped region.
6. The method of manufacturing a silicon carbide trench MOSFET transistor having dense cells as claimed in claim 5, wherein forming the cell structure within the epitaxial layer comprises:
forming a first doping region of the first doping type on the surface of the epitaxial layer far away from the first surface;
forming a well region of a second doping type arranged at an interval with the grid groove structure in the peripheral region of the first doping region;
forming a first groove structure in the epitaxial layer;
forming a grid groove structure in the first groove structure;
and forming a source metal structure on the surface of the epitaxial layer far away from the first surface.
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