CN115084237B - Silicon carbide trench MOSFET transistor with dense cells and method of fabricating the same - Google Patents

Abstract

The present application discloses a silicon carbide trench MOSFET transistor with dense cells and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The silicon carbide trench type MOSFET transistor includes: a silicon carbide substrate of a first doping type, the silicon carbide substrate includes a first surface, and an epitaxial layer of the first doping type is provided on the first surface; A plurality of cell structures, the cell structure includes a gate trench structure; a clamping protection structure is provided in the peripheral area of each cell structure, and the clamping protection structure is used to protect the gate at the corner of the gate trench structure oxide layer. According to the present application, the electric field strength of the gate oxide layer at the corner of the gate trench structure can be clamped below a safe value, thereby protecting the corner of the gate trench structure and improving the reliability of the transistor.

Description

Silicon carbide trench MOSFET transistor with dense cells and its manufacturing method

technical field

The present application belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide trench MOSFET transistor with dense cells and a manufacturing method thereof.

Background technique

Metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) is a voltage type control device, the driving circuit is simple, the driving power is small, and the switching speed is fast, and it has a high operating frequency.

According to different gate layout directions, silicon carbide MOSFETs can be divided into planar structure and trench structure. The trench structure has a more obvious advantage in conduction performance due to the higher cell density. But for trench silicon carbide transistors, the biggest challenge is that the gate oxide layer at the corner of the trench is extremely easy to withstand huge electric field strength, which affects the reliability of the device.

Contents of the invention

Embodiments of the present application provide a silicon carbide trench MOSFET transistor with dense cells and a manufacturing method thereof, which can reduce the electric field intensity at the corners of the gate trench structure, thereby protecting the corners of the gate trench structure , improve the reliability of the transistor.

In the first aspect, the embodiment of the present application provides a silicon carbide trench MOSFET transistor with dense cells, including:

A silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;

a plurality of cellular structures disposed within the epitaxial layer, the cellular structures including gate trench structures;

The peripheral area of each of the cell structures is provided with a clamping protection structure, and the clamping protection structure is used for clamping the electric field intensity borne by the gate oxide layer at the corner of the gate trench structure below a safe value . In some optional embodiments, the cellular structure includes at least two subcellular structures arranged in parallel;

The subcellular structure includes:

a gate trench structure disposed in the epitaxial layer;

a source metal structure disposed on a surface of the epitaxial layer away from the first surface;

a first doped region of the first doping type disposed on a side peripheral region of the gate trench structure near the top;

a well region of a second doping type disposed in the peripheral region of the first doping region and spaced from the gate trench structure; the first doping type is opposite to the second doping type .

In some optional implementation manners, the clamp protection structure includes:

a second doped region of a second doping type disposed in the epitaxial layer, the depth of the second doped region being greater than the depth of the gate trench structure;

a first metal structure disposed on the surface of the second doped region;

A third doped region disposed in the second doped region and in contact with the first metal structure.

In some optional implementation manners, the third doped region is of the second doped type.

In some optional implementation manners, the third doped region is of the first doped type.

In some optional implementation manners, the clamp protection structure further includes:

at least one fourth doped region of the second doped type disposed on a side of the second doped region close to the first surface;

A fifth doped region of the first doped type is disposed at the bottom of the second doped region.

In some optional implementation manners, the clamp protection structure includes:

a sixth doped region of the second doping type disposed in the epitaxial layer, the depth of the sixth doped region is greater than the depth of the gate trench structure;

a second metal structure disposed on the surface of the sixth doped region;

a PN junction structure disposed in the sixth doped region and close to one side of the second metal structure;

a third metal structure disposed on a side of the PN junction structure close to the first surface;

A seventh doping region of the first doping type disposed on a side of the third metal structure close to the first surface.

In some optional implementation manners, the PN junction structure includes:

a first doping structure and a second doping structure disposed between the second metal structure and the third metal structure, the first doping structure is the first doping type, the second the doping structure is the second doping type;

The contact surface between the first doped structure and the second doped structure is parallel to the first surface, and the first doped structure is disposed on a side close to the third metal structure, so The second doping structure is arranged on a side close to the second metal structure.

In the second aspect, the embodiment of the present application provides a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells, including:

providing a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;

forming a cellular structure in the epitaxial layer, the cellular structure including a gate trench structure;

A clamping protection structure is formed in the peripheral region of each of the cell structures, and the clamping protection structure is used for clamping the electric field intensity borne by the gate oxide layer at the corner of the gate trench structure below a safe value .

In some optional implementation manners, the forming a cellular structure in the epitaxial layer includes:

forming a first doped region of the first doping type on a surface of the epitaxial layer away from the first surface;

forming a well region of a second doping type spaced apart from the gate trench structure in a peripheral region of the first doped region;

forming a first trench structure in the epitaxial layer;

forming a gate trench structure within the first trench structure;

A source metal structure is formed on a surface of the epitaxial layer away from the first surface.

An embodiment of the present application provides a silicon carbide trench MOSFET transistor with dense cells, the transistor may include: a plurality of cell structures embedded in the epitaxial layer and a clamping protection structure arranged in the peripheral region of the cell structure. The electric field strength of the gate oxide layer at the corner of the gate trench structure will increase rapidly with the increase of the blocking voltage of the transistor. The gate oxide layer is more prone to breakdown failure. However, when the blocking voltage of the transistor reaches the lower breakdown voltage of the clamping protection structure, the clamping protection structure is broken down, and the transistor breaks down in advance, which can reduce the electric field at the corner of the gate trench structure The strength is clamped below a safe value, thereby protecting the gate oxide layer at the corner of the gate trench structure and improving the reliability of the transistor.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the embodiments of the present application. Additional figures can be derived from these figures.

Figure 1 is a schematic structural view of an embodiment of a silicon carbide trench MOSFET transistor with dense cells provided by the present application;

FIG. 2 is another schematic structural view of an embodiment of a silicon carbide trench MOSFET transistor with dense cells provided by the present application;

FIG. 3 is another structural schematic diagram of an embodiment of a silicon carbide trench MOSFET transistor with dense cells provided by the present application;

FIG. 4 is another structural schematic diagram of an embodiment of a silicon carbide trench MOSFET transistor with dense cells provided by the present application;

5 is a schematic flow diagram of an embodiment of a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells provided by the present application;

Fig. 6 is a schematic cross-sectional structure diagram of a silicon carbide substrate provided by the present application;

FIG. 7 is a schematic diagram of a cross-sectional structure for forming a first doped region provided by the present application;

FIG. 8 is a schematic diagram of a cross-sectional structure for forming a well region provided by the present application;

FIG. 9 is a schematic diagram of a cross-sectional structure for forming a first trench structure provided by the present application;

FIG. 10 is a schematic diagram of a cross-sectional structure for forming a gate trench structure provided by the present application;

FIG. 11 is a schematic cross-sectional structure diagram of the source metal structure provided by the present application;

Fig. 12 is a schematic cross-sectional structure diagram for forming the second doped region and the third doped region provided by the present application;

Fig. 13 is a schematic cross-sectional structure diagram of forming the first metal structure provided by the present application;

FIG. 14 is a schematic cross-sectional structure diagram for forming a fourth doped region provided by the present application;

Fig. 15 is a schematic cross-sectional structure diagram for forming a fifth doped region provided by the present application;

FIG. 16 is a schematic cross-sectional structure diagram of forming a second trench structure provided by the present application;

Fig. 17 is a schematic cross-sectional structure diagram for forming the sixth doped region provided by the present application;

Fig. 18 is a schematic cross-sectional structure diagram for forming the seventh doped region provided by the present application;

Fig. 19 is a schematic cross-sectional structure diagram of forming a third trench structure provided by the present application;

Fig. 20 is a schematic cross-sectional structure diagram of forming a third metal structure provided by the present application;

Fig. 21 is a schematic cross-sectional structure diagram of forming a PN junction structure provided by the present application;

FIG. 22 is a schematic cross-sectional structure diagram of forming a second metal structure provided by the present application.

Explanation of reference signs:

1: silicon carbide substrate; 11: first surface; 12: second surface.

2: epitaxial layer; 21: cellular structure; 211: subcellular structure; 2111: gate trench structure; 21111: gate structure; 21112: gate oxide layer; 2112: source metal structure; 2113: first doped region; 2114: well region; 22: clamp protection structure; 221: second doped region; 2211: first metal structure; 2212: third doped region; 2213: fourth doped region; 2214: first Five doping regions; 222: sixth doping region; 2221: second metal structure; 2222: PN junction structure; 22221: first doping structure; 22222: second doping structure; 2223: third metal structure; 2224 : the seventh doped region; 23: the first trench structure; 25: the second trench structure; 26: the third trench structure.

3: Drain structure.

In the figures, the same parts are given the same reference numerals. The figures are not drawn to scale.

Detailed ways

The characteristics and exemplary embodiments of various aspects of the application will be described in detail below. In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only intended to explain the present application rather than limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. any such actual relationship or order exists between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising..." does not exclude the presence of additional same elements in the process, method, article or device comprising said element.

In order to solve the problems of the prior art, embodiments of the present application provide a silicon carbide trench MOSFET transistor with dense cells and a manufacturing method thereof. The silicon carbide trench MOSFET transistor with dense cells provided by the embodiment of the present application will be firstly introduced below.

FIG. 1 shows a schematic structural diagram of an embodiment of a silicon carbide trench MOSFET transistor with dense cells provided by an embodiment of the present application.

As shown in Figure 1, the silicon carbide trench MOSFET transistor with dense cells provided in the embodiment of the present application may include:

A silicon carbide substrate 1 of the first doping type. The silicon carbide substrate 1 includes a first surface 11 on which an epitaxial layer 2 of the first doping type is disposed;

A plurality of cellular structures 21 disposed in the epitaxial layer 2, the cellular structures 21 include a gate trench structure 2111;

The peripheral area of each cell structure 21 is provided with a clamp protection structure 22, and the clamp protection structure 22 is used to ensure that the breakdown of the transistor occurs in advance, so as to withstand the gate oxide layer 21112 at the corner of the gate trench structure 2111. The electric field strength clamped below the safe value.

An embodiment of the present application provides a silicon carbide trench MOSFET transistor with dense cells, the transistor may include: a plurality of cell structures embedded in the epitaxial layer and a clamping protection structure arranged in the peripheral region of the cell structure. The electric field strength of the gate oxide layer at the corner of the gate trench structure will increase rapidly with the increase of the blocking voltage of the transistor. The gate oxide layer is more prone to breakdown failure. However, when the blocking voltage of the transistor reaches the lower breakdown voltage of the clamping protection structure, the clamping protection structure is broken down, and the transistor breaks down in advance, which can reduce the electric field at the corner of the gate trench structure The strength is clamped below a safe value, thereby protecting the corners of the gate trench structure and improving the reliability of the transistor.

In this embodiment, the first doping type may be N type, and the second doping type may be P type. The silicon carbide substrate 1 of the first doping type may be an N-type silicon carbide substrate; the epitaxial layer 2 of the first doping type may be an N-type epitaxial layer.

The number of cellular structures 21 included in the epitaxial layer 2 can be set according to actual needs, and is not limited here. For example, the number of cellular structures 21 may be 100.

The clamping protection structure 22 may be a structure capable of clamping the electric field intensity borne by the gate oxide layer 21112 at the corner of the gate trench structure 2111 below a safe value.

In some optional implementation manners, silicon carbide substrate 1 may further include a second surface 12 opposite to first surface 11 , and second surface 12 is provided with drain structure 3 .

In some optional embodiments, the cellular structure 21 may include at least two sub-cellular structures 211 arranged in parallel;

Subcellular structure 211 may include:

a gate trench structure 2111 disposed in the epitaxial layer 2;

a source metal structure 2112 disposed on the surface of the epitaxial layer 2 away from the first surface 11;

A first doped region 2113 of the first doping type disposed on the peripheral region of the side of the gate trench structure 2111 near the top;

The well region 2114 of the second doping type is disposed in the peripheral region of the first doping region 2113 and spaced apart from the gate trench structure 2111 ; the first doping type is opposite to the second doping type.

In this embodiment, the cellular structure 21 may include at least two sub-cellular structures 211 arranged in parallel, it can be understood that the cellular structure 21 may include at least two sub-cellular structures 211 in a direction parallel to the first surface 11 .

The number of sub-cellular structures 211 in each cellular structure 21 can be set according to actual conditions, and is not limited here. Optionally, each cellular structure 21 may include four sub-cellular structures 211 arranged in parallel.

In this embodiment, the first doped region 2113 of the first doping type may be an N-type first doping region, and the well region 2114 of the second doping type may be a P-type well region 2114 .

The peripheral region of the first doped region 2113 can be understood as the region of the first doped region 2113 away from the gate trench structure 2111 .

The first doping type is opposite to the second doping type. It can be understood that the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. For example, when the first doping type is N type, the second doping type is P type.

The dimensions (pitch) of the subcellular structure 211 , the gate trench structure 2111 , the first doped region 2113 and the well region 2114 can be set according to the actual situation, and are not limited here.

Exemplarily, the length of the subcellular structure 211 in the direction parallel to the silicon carbide substrate 1 may be 2.4um; the length of the gate trench structure 2111 in the direction parallel to the silicon carbide substrate 1 may be 1.0um, and the gate The length of the pole trench structure 2111 in the direction perpendicular to the silicon carbide substrate 1 and embedded in the epitaxial layer 2 can be 0.9um; the length of the first doped region 2113 in the direction parallel to the silicon carbide substrate 1 can be The length of the well region 2114 in the direction parallel to the silicon carbide substrate 1 may be 0.6 um, and the length of the well region 2114 in the direction perpendicular to the silicon carbide substrate 1 may be 1.2 um.

Optionally, in the direction perpendicular to the first surface 11, the length of the well region 2114 may be greater than the length of the gate structure 21111 in the gate trench structure 2111; the length of the well region 2114 may also be less than or equal to the gate trench The length of the gate structure 21111 in the structure 2111. That is, the depth of the well region 2114 may be greater than the depth of the gate trench structure 2111 , and the depth of the well region 2114 may also be smaller than the depth of the gate trench structure 2111 .

In this embodiment, in the blocking mode, the length of the well region 2114 in the direction perpendicular to the silicon carbide substrate 1 may be greater than that of the gate structure 21111 in the gate trench structure 2111 in the direction perpendicular to the silicon carbide substrate 1 In the case of the length in the direction, the well region 2114 can form a depletion region, and the depletion region can shield part of the electric field intensity at the corner of the gate trench structure 2111, thereby improving the reliability of the transistor.

In this embodiment, due to the existence of the clamping protection structure 22, the transistor does not need to design a deep P-type well region 2114 with a certain width to protect the corners of the gate trench structure 2111, thereby reducing the number of sub-cell structures 211 Therefore, the silicon carbide trench MOSFET transistor formed can have dense cells relative to the related technology.

In some optional implementation manners, the clamp protection structure 22 may include:

A second doped region 221 of the second doping type disposed in the epitaxial layer 2, the depth of the second doped region 221 is greater than the depth of the gate trench structure 2111;

a first metal structure 2211 disposed on the surface of the second doped region 221;

The third doped region 2212 is disposed in the second doped region 221 and in contact with the first metal structure 2211 .

In this embodiment, the second doped region 221 of the second doping type and the epitaxial layer 2 of the first doping type can form a PN junction avalanche diode, and the electric field intensity at the corner of the gate trench structure will vary with As the blocking voltage of the transistor increases rapidly, the higher the blocking voltage is, the more likely the gate oxide layer at the corner of the gate trench structure is to fail due to breakdown. When the blocking voltage of the transistor reaches the breakdown voltage of the lower PN junction avalanche diode, the PN junction avalanche diode is broken down, so the transistor breaks down in advance, and the electric field strength at the corner of the gate trench structure can be reduced The clamping is below a safe value, thereby protecting the corners of the gate trench structure and improving the reliability of the transistor.

The second doped region 221 of the second doping type may be a P-type second doped region 221 .

The depth of the second doped region 221 is greater than the depth of the gate trench structure 2111. It can be understood that the length of the second doped region 221 in the direction perpendicular to the first surface 11 is greater than the length of the gate trench structure 2111 in the direction perpendicular to the first surface 11. The length in the direction of a surface 11 , that is, in the direction perpendicular to the first surface 11 , the length of the second doped region 221 is greater than the length of the gate trench structure 2111 .

Optionally, the depth of the second doped region 221 is greater than the depth of the well region 2114 . That is, in the direction perpendicular to the first surface 11 , the length of the second doped region 221 is greater than the length of the well region 2114 .

In some optional implementation manners, the third doped region 2212 may be of the second doped type. For example, the third doped region 2212 may be P-type.

In this embodiment, by setting the third doped region 2212 in contact with the first metal structure 2211 in the second doped region 221 , a good ohmic contact can be formed with the first metal structure 2211 and contact resistance can be reduced.

As shown in FIG. 2, when the third doped region 2212 is of the second doping type, that is, the third doped region 2212 is of the P type, the clamp protection structure 22 may further include:

at least one fourth doping region 2213 of the second doping type disposed on the side of the second doping region 221 close to the first surface 11;

A fifth doped region 2214 of the first doped type is disposed at the bottom of the second doped region 221 .

The fourth doped region 2213 of the second doping type may be a fourth doped region 2213 of P type, and the fifth doped region 2214 of the first doping type may be a fifth doped region 2214 of N type.

The doping concentration of the fifth doped region 2214 is the same as that of the second doped region 221 . The fifth doped region 2214 can be regarded as a part of the second doped region 221 .

The distance between the fourth doped region 2213 and the first surface 11 is smaller than the distance between the second doped region 221 and the first surface 11 .

It can be understood that, since the electric field strength is the largest at the place where the curvature of the PN junction changes the most, avalanche breakdown generally occurs at the place where the curvature of the PN junction changes the most, that is, the corners A and A of the second doped region 221 close to the first surface 11 F will have an avalanche breakdown. The avalanche energy Eas is the main index to evaluate the avalanche resistance of the device, where Eas=1/2×L×I ² , I is the maximum current value passed by the device, and L is the inductance of the line. Increasing the avalanche current conduction path of the device when avalanche breakdown occurs can significantly improve the avalanche resistance of the device.

In this embodiment, at least one fourth doping region 2213 of the second doping type is provided on the side of the second doping region 221 close to the first surface 11, and the fourth doping region 2213 is close to the corner of the first surface 11 The electric field intensity at points C and D will increase, and this point and the corner portion of the second doped region 221 close to the first surface 11 may reach an avalanche state at the same time. In addition, at the bottom of the second doped region 221, a fifth doped region 2214 with a high concentration of the first doped type is provided. According to Poisson's equation, the electric field strength at points B and E can be increased, thereby achieving the same level as A and F. The state of simultaneous breakdown of two points. That is to say, in the embodiment of the present application, by increasing the number of avalanche breakdown points (such as points B, C, D, and E), the conduction path of the avalanche current is increased, thereby improving the avalanche resistance of the device.

Optionally, in the case where the clamping protection structure 22 includes at least two fourth doped regions 2213 of the second doped type disposed on the side of the second doped region 221 close to the first surface 11, each fourth doped region Miscellaneous regions 2213 are arranged at intervals.

As shown in FIG. 3 , in FIG. 3 , the clamping protection structure 22 includes two fourth doped regions 2213 of the second doping type as an example, and the clamping protection structure 22 may also include three fourth doping regions 2213 of the second doping type. The four doped regions 2213 , or the four fourth doped regions 2213 of the second doping type are not limited here.

As shown in FIG. 1 , in some optional implementation manners, the third doped region 2212 may be of the first doped type.

The third doped region 2212 may be an N-type doped region with high ion doping concentration. The ion doping concentration of the second doping region 221 is smaller than the ion doping concentration of the third doping region 2212 .

In this embodiment, when the third doped region 2212 is N-type, the clamp protection structure 22 is composed of the N-type third doped region 2212, the P-type second doped region 221 and the N-type epitaxial layer 2. The NPN structure may be a punch-through breakdown structure. By setting the ion doping concentration of the second doping region 221 close to the ion doping concentration of the N-type epitaxial layer 2, under a certain blocking voltage state, the electric field lines can completely pass through the second doping region 221, and the entire second doping region 221 The electric field strengths of the two doped regions 221 are not zero, therefore, electrons can quickly pass through the second doped region 221 under the action of the electric field. Correspondingly, if the ion doping concentration of the second doped region 221 is much higher than the ion doping concentration of the N-type epitaxial layer 2 , the electric field intensity in the second doped region 221 will quickly drop to zero.

In related technologies, the advantage of punch-through breakdown is that no hole-electron pairs are generated during breakdown, the breakdown process is not violent, and the device structure is not easily damaged by heat; the disadvantage is that the punch-through voltage is smaller than the avalanche breakdown voltage. It needs to be avoided as much as possible, but what is required in this application is the early breakdown of the clamping protection structure 22 .

In addition, by disposing the high-concentration N-type third doped region 2212 in the second doped region 221 in contact with the first metal structure 2211 , electrons can be provided continuously during punch-through and breakdown. In addition, for silicon carbide (SiC) materials, the process of forming ohmic contacts on N-type doped regions is more mature than that on P-type doped regions. In the related art, the contact resistivity of silicon carbide N-type ohmic contact is generally 10 ^-6 Ohm.cm2, while the contact resistivity of silicon carbide P-type ohmic contact is generally 10 ^-4 Ohm.cm2. It can be seen that the N-type ohmic contact The contact resistivity of the P-type ohmic contact is much smaller than that of the P-type ohmic contact, thereby reducing the resistance on the current path when the breakdown occurs.

As shown in FIG. 4, in some optional implementation manners, the clamp protection structure 22 may further include:

A sixth doped region 222 of the second doping type disposed in the epitaxial layer 2, the depth of the sixth doped region 222 is greater than the depth of the gate trench structure 2111;

a second metal structure 2221 disposed on the surface of the sixth doped region 222;

A PN junction structure 2222 disposed in the sixth doped region 222 and close to the side of the second metal structure 2221;

A third metal structure 2223 disposed on the side of the PN junction structure 2222 close to the first surface 11;

The seventh doping region 2224 of the first doping type is disposed on the side of the third metal structure 2223 close to the first surface 11 .

The depth of the sixth doped region 222 is greater than that of the gate trench structure 2111 . It can be understood that, in the direction perpendicular to the first surface 11 , the length of the sixth doped region 222 is greater than the length of the gate trench structure 2111 .

In this embodiment, the seventh doped region 2224 of the first doping type, the sixth doped region 222 of the second doping type and the epitaxial layer 2 of the first doping type form an NPN structure.

It can be understood that, by setting the P-type sixth doped region 222 with a lower ion doping concentration, under a certain blocking voltage state, the electric field lines can completely pass through the sixth doped region 222, because the third metal structure 2223 Connect the PN junction structure 2222 and the seventh doped region 2224, the potential of the PN junction structure 2222 is equal to the potential of the seventh doped region 2224, so the potential of the sixth doped region 222 increases, when the potential of the sixth doped region 222 When it increases to a certain value (for example, when increasing from 0V to 30V), the breakdown voltage of the PN junction structure 2222 is reached, so the entire PN junction structure 2222 is broken down, and the voltage of the entire SiC trench MOSFET transistor is clamped at a safe Therefore, the electric field intensity at the corner of the gate trench structure is also clamped below a safe value, thereby protecting the corner of the gate trench structure and improving the reliability of the transistor.

Further, the punch-through breakdown of the PN junction composed of the sixth P-type doped region 222 and the N-type epitaxial layer 2 has relatively large leakage current before the breakdown occurs, and the breakdown curve is relatively soft. By arranging the PN junction structure 2222 on the side of the third metal structure 2223 away from the first surface 11, the leakage current before the punch-through breakdown can be reduced, and the loss of the SiC trench MOSFET transistor in the blocking state can be reduced.

Optionally, the PN junction structure 2222 may be a polysilicon Zener diode structure.

In some optional implementation manners, the PN junction structure 2222 may include:

The first doping structure 22221 and the second doping structure 22222 arranged between the second metal structure 2221 and the third metal structure 2223, the first doping structure 22221 is the first doping type, and the second doping structure 22222 is a second doping type;

The contact surface between the first doped structure 22221 and the second doped structure 22222 is parallel to the first surface 11, and the first doped structure 22221 is arranged on a side close to the third metal structure 2223, and the second doped structure 22222 It is arranged on the side close to the second metal structure 2221 .

In this embodiment, the first doping structure 22221 of the first doping type is an N-type first doping structure 22221; the second doping structure 22222 of the second doping type is a P-type second doping structure 22222.

In the embodiment of the present application, the shape of each doped region is a rectangle as an example, but not limited thereto, and the shape of each doped region can be set according to actual conditions.

It should be noted that in this embodiment, the first doping type is N-type and the second doping type is P-type as an example. However, in actual implementation, the silicon carbide substrate 1 is not limited to the N type, and may also be the P type. When the silicon carbide substrate 1 is of P type, correspondingly, the conductivity types of structures such as the epitaxial layer 2 , the well region 2114 and the first doped region 2113 also change.

Based on the silicon carbide trench MOSFET transistor with dense cells provided in the above embodiments, the present application also provides a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells. A method for manufacturing a silicon carbide trench MOSFET transistor with dense cells will be described below.

FIG. 5 shows a schematic flowchart of an embodiment of a method for manufacturing a silicon carbide trench MOSFET transistor with dense cells provided by the present application.

As shown in FIG. 5 , the method for manufacturing a silicon carbide trench MOSFET transistor with dense cells may include S501 to S503 . Please refer to FIG. 6 to FIG. 22 together. FIG. 6 to FIG. 22 are schematic cross-sectional structure diagrams corresponding to a series of manufacturing processes of the silicon carbide trench MOSFET transistor with dense cells provided by the present application.

S501 , providing a silicon carbide substrate 1 of a first doping type. The silicon carbide substrate 1 includes a first surface 11 , and an epitaxial layer 2 of the first doping type is disposed on the first surface 11 .

In this embodiment, the silicon carbide substrate 1 of the first doping type is an N-type silicon carbide substrate 1 .

As shown in FIG. 6 , in some optional implementation manners, an N-type silicon carbide substrate 1 is provided first, and then epitaxy is performed on the silicon carbide substrate 1 to form an N-type epitaxial layer 2 .

S502 , forming a cell structure 21 in the epitaxial layer 2 , where the cell structure 21 includes a gate trench structure 2111 .

In some optional implementation manners, forming the cellular structure 21 in the epitaxial layer 2 may include:

forming a first doped region 2113 of the first doping type on the surface of the epitaxial layer 2 away from the first surface 11;

forming a second doping type well region 2114 spaced apart from the gate trench structure 2111 in the peripheral region of the first doping region 2113;

forming a first trench structure 23 in the epitaxial layer 2;

forming a gate trench structure 2111 in the first trench structure 23;

A source metal structure 2112 is formed on the surface of the epitaxial layer 2 away from the first surface 11 .

Optionally, as shown in FIG. 7 , forming the first doped region 2113 of the first doping type on the surface of the epitaxial layer 2 away from the first surface 11 may include:

Ion doping of the first doping type is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a first doping region 2113 of the first doping type.

Specifically, the first doped region 2113 of the first doping type may be an N-type first doped region 2113 .

Exemplarily, N-type ions are implanted on the surface of the epitaxial layer 2 away from the first surface 11 through a mask and a photolithography process to form a first doped region 2113 of the first doping type

Optionally, as shown in FIG. 8 , forming a second doping type well region 2114 spaced apart from the gate trench structure 2111 in the peripheral region of the first doping region 2113 may include:

Ion doping of the second doping type is performed on the peripheral region of the first doping region 2113 to form a well region 2114 of the second doping type spaced apart from the gate trench structure 2111 .

Specifically, the well region 2114 of the second doping type may be a P-type well region 2114 .

Exemplarily, P-type ions are implanted into the peripheral region of the first doped region 2113 through a mask and photolithography process to form a P-type well region 2114 spaced apart from the gate trench structure 2111 .

Optionally, as shown in FIG. 9, forming the first trench structure 23 in the epitaxial layer 2 may include:

Groove etching is performed on the surface of the epitaxial layer 2 away from the first surface 11 , so that a first trench structure 23 is formed in the epitaxial layer 2 .

Specifically, trench etching can be performed on the surface of the epitaxial layer 2 away from the first surface 11 by using a mask, so that the first trench structure 23 is formed in the epitaxial layer 2 .

Optionally, as shown in FIG. 10 , forming a gate trench structure 2111 in the first trench structure 23 may include:

performing oxidation on the surface of the first trench structure 23 to form a gate oxide layer 21112;

A gate structure 21111 is formed on the surface of the gate oxide layer 21112 .

Exemplarily, a gate oxide layer 21112 is formed on the surface of the first trench structure 23 by an oxidation or deposition process.

Optionally, as shown in FIG. 11 , forming the source metal structure 2112 on the surface of the epitaxial layer 2 away from the first surface 11 may include:

Metal is deposited on the surface of the epitaxial layer 2 away from the first surface 11 to form a source metal structure 2112 .

Exemplarily, by photolithography and metallization, the source metal structure 2112 is formed on the surface of the epitaxial layer 2 away from the first surface 11 .

S503, forming a clamping protection structure 22 in the peripheral region of each cell structure 21, the clamping protection structure 22 is used to clamp the electric field intensity borne by the gate oxide layer 21112 at the corner of the gate trench structure 2111 at below the safe value.

In some optional implementation manners, as shown in FIG. 12 and FIG. 13 , forming a clamping protection structure 22 in the peripheral region of each cellular structure 21 may include:

forming a second doped region 221 of the second doping type in the epitaxial layer 2;

forming a third doped region 2212 in the second doped region 221;

A first metal structure 2211 is formed on the surface of the third doped region 2212 .

Exemplarily, a P-type second doped region 221 can be formed by using a higher implanter energy through a mask and a photolithography process, and high-dose implantation can be used to form a third doped region 221 in the second doped region 221. In the region 2212 , metal is deposited on the surface of the third doped region 2212 to form the first metal structure 2211 .

In some optional implementation manners, the third doping region 2212 may be of the second doping type, that is, the third doping region 2212 may be of the P type.

As shown in FIGS. 14 to 15 , in some optional implementation manners, a clamping protection structure 22 is formed in the peripheral region of each cellular structure 21, which may include:

forming at least one fourth doping region 2213 of the second doping type on the side of the second doping region 221 close to the first surface 11;

A fifth doped region 2214 of the first doping type is formed at the bottom of the second doped region 221 .

As an example, P-type ion doping is performed on the side of the second doped region 221 close to the first surface 11 to form a P-type fourth doped region 2213; N-type ion doping is performed on the bottom of the second doped region 221. doped to form an N-type fifth doped region 2214 .

As another example, as shown in FIGS. 14 to 16, at least one fourth doped region 2213 of the second doping type is formed on the side of the second doped region 221 close to the first surface 11. A second trench structure 25 is formed in the layer 2; using the second trench structure 25, the side of the second doped region 221 close to the first surface 11 is doped with P-type ions to form a P-type fourth doped region 2213 : Do N-type ion doping in the second trench structure 25 to form an N-type fifth doped region 2214 .

In other optional implementation manners, the third doping region 2212 may be of the first doping type, that is, the third doping region 2212 may be of N type.

In some optional implementation manners, as shown in FIG. 17 to FIG. 22 , forming a clamping protection structure 22 in the peripheral region of each cellular structure 21 may include:

A sixth doped region 222 of the second doping type is formed in the epitaxial layer 2, and the depth of the sixth doped region 222 is greater than the depth of the gate trench structure 2111;

forming a seventh doped region 2224 of the first doping type in the sixth doped region 222;

forming a third trench structure 26 in the sixth doped region 222;

forming a third metal structure 2223 at the bottom of the third trench structure 26;

Forming a PN junction structure 2222 on a side of the third metal structure 2223 away from the first surface 11;

A second metal structure 2221 is formed on a side of the PN junction structure 2222 away from the first surface 11 .

Exemplarily, P-type ion doping is performed in the sixth doped region 222 to form a P-type sixth doped region 222; N-type ion doping is performed in the sixth doped region 222 to form an N-type the seventh doped region 2224; etch in the sixth doped region 222 to form a third trench structure 26; deposit metal at the bottom of the third trench structure 26 to form a third metal structure 2223; Polysilicon material is deposited in the third trench structure 26, and a PN junction structure 2222 is formed on the side of the third metal structure 2223 away from the first surface 11; metal is deposited on the side of the PN junction structure 2222 away from the first surface 11 to form the first surface 11. Two metal structures 2221.

Further, forming the PN junction structure 2222 on the side of the third metal structure 2223 away from the first surface 11 may include:

forming a first doping structure 22221 of the first doping type on the side of the third metal structure 2223 away from the first surface 11;

A second doping structure 22222 of the second doping type is formed on the side of the first doping structure 22221 away from the first surface 11 .

Exemplarily, N-type ion doping is performed on the side of the third metal structure 2223 away from the first surface 11 to form an N-type first doped structure 22221;

P-type ion doping is performed on the side of the first doped structure 22221 away from the first surface 11 to form a P-type second doped structure 22222 . As shown in FIG. 1 , silicon carbide substrate 1 may further include a second surface 12 opposite to first surface 11 , and drain structure 3 is formed on second surface 12 .

It should be noted that in this embodiment, the first doping type is N-type and the second doping type is P-type as an example. However, in actual implementation, the silicon carbide substrate 1 is not limited to the N type, and may also be the P type. When the silicon carbide substrate 1 is of P type, correspondingly, the conductivity types of structures such as the epitaxial layer 2 , the well region 2114 and the first doped region 2113 also change.

Regarding the manufacturing method of the silicon carbide trench MOSFET transistor with dense cells in the above embodiment, the various structures and beneficial effects have been detailed in the embodiment of the silicon carbide trench MOSFET transistor with dense cells description, and will not be elaborated here.

The above is only a specific implementation of the present application, and those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described systems, modules and units can refer to the foregoing method embodiments The corresponding process in , will not be repeated here. It should be understood that the protection scope of the present application is not limited thereto, and any person familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the application, and these modifications or replacements should cover all Within the protection scope of this application.

Claims (6)

1. A silicon carbide trench MOSFET transistor with dense cells, characterized in that it comprises: A silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed; a plurality of cellular structures disposed within the epitaxial layer, the cellular structures including gate trench structures; The peripheral area of each of the cell structures is provided with a clamping protection structure, and the clamping protection structure is used for clamping the electric field intensity borne by the gate oxide layer at the corner of the gate trench structure below a safe value ; The clamp protection structure includes: a sixth doped region of the second doping type disposed in the epitaxial layer, the depth of the sixth doped region is greater than the depth of the gate trench structure; a second metal structure disposed on the surface of the sixth doped region; a PN junction structure disposed in the sixth doped region and close to one side of the second metal structure; a third metal structure disposed on a side of the PN junction structure close to the first surface; a seventh doped region of the first doping type disposed on a side of the third metal structure close to the first surface; Wherein, the third metal structure is in direct contact with the PN junction structure and the seventh doped region. 2. The silicon carbide trench MOSFET transistor with dense cells according to claim 1, wherein the cell structure comprises at least two sub-cell structures arranged in parallel; The subcellular structure includes: a gate trench structure disposed in the epitaxial layer; a source metal structure disposed on a surface of the epitaxial layer away from the first surface; a first doped region of the first doping type disposed on a side peripheral region of the gate trench structure near the top; a well region of a second doping type disposed in a peripheral region of the first doped region and spaced from the gate trench structure; The first doping type is opposite to the second doping type. 3. The silicon carbide trench MOSFET transistor with dense cells according to claim 1, wherein the PN junction structure comprises: a first doping structure and a second doping structure disposed between the second metal structure and the third metal structure, the first doping structure is the first doping type, the second the doping structure is the second doping type; The contact surface between the first doped structure and the second doped structure is parallel to the first surface, and the first doped structure is arranged on a side close to the third metal structure, so The second doping structure is arranged on a side close to the second metal structure. 4. A silicon carbide trench MOSFET transistor with dense cells, characterized in that it comprises: A silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed; a plurality of cellular structures disposed within the epitaxial layer, the cellular structures including gate trench structures; The peripheral area of each of the cell structures is provided with a clamping protection structure, and the clamping protection structure is used for clamping the electric field intensity borne by the gate oxide layer at the corner of the gate trench structure below a safe value ; The clamp protection structure includes: a second doped region of a second doping type disposed in the epitaxial layer, the depth of the second doped region being greater than the depth of the gate trench structure; a first metal structure disposed on the surface of the second doped region; a third doped region disposed within the second doped region and in contact with the first metal structure; the third doped region is of the second doping type; The clamp protection structure also includes: at least one fourth doped region of the second doped type disposed on a side of the second doped region close to the first surface; A fifth doped region of the first doped type is disposed at the bottom of the second doped region. 5. A method for manufacturing a silicon carbide trench MOSFET transistor with dense cells, characterized in that it comprises: providing a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed; forming a cellular structure in the epitaxial layer, the cellular structure including a gate trench structure; A clamping protection structure is formed in the peripheral region of each of the cell structures, and the clamping protection structure is used to clamp the electric field strength borne by the gate oxide layer at the corner of the gate trench structure below a safe value ; A clamping protection structure is formed in the peripheral region of each of the cellular structures, including: forming a sixth doped region of the second doping type in the epitaxial layer, the depth of the sixth doped region is greater than the depth of the gate trench structure; forming a seventh doped region of the first doping type within the sixth doped region; forming a third trench structure in the sixth doped region; forming a third metal structure at the bottom of the third trench structure; forming a PN junction structure on a side of the third metal structure away from the first surface; forming a second metal structure on a side of the PN junction structure away from the first surface; Wherein, the third metal structure is in direct contact with the PN junction structure and the seventh doped region. 6. The method for manufacturing a silicon carbide trench MOSFET transistor with dense cells according to claim 5, wherein said forming a cell structure in said epitaxial layer comprises: forming a first doped region of the first doping type on a surface of the epitaxial layer away from the first surface; forming a well region of a second doping type spaced apart from the gate trench structure in a peripheral region of the first doped region; forming a first trench structure in the epitaxial layer; forming a gate trench structure within the first trench structure; A source metal structure is formed on a surface of the epitaxial layer away from the first surface.

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