CN114937692B - Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof - Google Patents
Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof Download PDFInfo
- Publication number
- CN114937692B CN114937692B CN202210876258.2A CN202210876258A CN114937692B CN 114937692 B CN114937692 B CN 114937692B CN 202210876258 A CN202210876258 A CN 202210876258A CN 114937692 B CN114937692 B CN 114937692B
- Authority
- CN
- China
- Prior art keywords
- region
- trench
- type
- source
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000007774 longterm Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly relates to a stepped trench gate SiC MOSFET structure with a trench diode and a preparation method thereof; according to the invention, the channel diode is formed by matching the source polysilicon, the channel diode gate oxide layer, the deep P-type region and the second source region, when the SiC MOSFET device is reversely conducted, the channel diode is conducted first, so that the conduction of a parasitic body diode of the device is avoided, the system power consumption loss of the device is effectively reduced, the bipolar degradation effect is prevented from occurring, the long-term reliability of the device is ensured, the freewheeling diode is built in the device, the high frequency and miniaturization of the device are facilitated, and the cost is reduced; through the setting of source utmost point polycrystalline silicon in the second slot, can effectively shield grid signal under on-off state, reduce the miller electric capacity of device, improve the switching speed of device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a stepped trench gate SiC MOSFET structure with a trench diode and a preparation method thereof.
Background
The SiC MOSFET is often used as a switching device, and in order to prevent the SiC MOSFET device from being damaged by the excessive voltage spike generated by the sudden change of current in the switching process, a freewheeling diode is required to be connected in parallel reversely. Because the forbidden band width of the SiC material is wide (about 3.26 eV), the turn-on voltage of the body diode is high (about 2.5V to about 3V at room temperature), if the parasitic body diode of the device is directly adopted as the freewheeling diode, extra power loss of a system can be caused, and after the body diode is turned on, the long-term reliability of the device can be influenced due to the bipolar degradation effect of the SiC material. If the mode of directly adopting an external diode as a freewheeling diode, extra parasitic capacitance and stray inductance are brought to the system, the power loss of the system is increased, the high frequency and miniaturization of the SiC MOSFET device are restricted, and extra cost is increased.
In addition, the conventional trench type SiC MOSFET has large trench density and large gate capacitance, so that the switching speed of the device is limited.
Disclosure of Invention
The invention aims to solve the technical problems that in the prior art, a SiC MOSFET device adopts a parasitic body diode of the device as a freewheeling diode, which causes extra power loss of a system and influences the reliability of the device, an external freewheeling diode increases the power consumption of the system and extra cost, and the traditional SiC MOSFET device has lower switching speed, so that the stepped trench gate SiC MOSFET structure with the trench diode and the preparation method thereof are provided.
A ladder trench gate SiC MOSFET structure with a trench diode, comprising: the transistor comprises drain electrode metal, an N-type heavily doped drain region, an N-type doped drift region, a P-type region, a gate oxide layer, gate polycrystalline silicon, a channel diode gate oxide layer, source polycrystalline silicon, a first oxide layer medium, a deep P-type region, a P-type base region, a P-type heavily doped first ohmic contact region, a P-type heavily doped second ohmic contact region, an N-type heavily doped first source region, an N-type heavily doped second source region, a second oxide layer medium and source electrode metal;
the drain region is positioned above the drain metal;
the drift region is positioned above the drain region;
the base region and the deep P type region are respectively positioned on two sides above the drift region;
the trench region is positioned between the base region and the deep P-type region, a first trench is formed on one side, close to the base region, of the trench region, the gate oxide layer is formed on the side wall of the trench region, a second trench is formed on one side, close to the deep P-type region, of the trench region, and the trench diode gate oxide layer is formed on the side wall of the trench region; the second trench is deeper than the first trench; the gate polysilicon is located in the first trench, the source polysilicon is located in the second trench, and a first oxide layer dielectric is located between the gate polysilicon and the source polysilicon;
the deep P-type region surrounds part of the bottom of the second groove; the P-type area is positioned below the first groove;
a first source region is formed on one side, which is in contact with the first groove, of the upper part of the base region, and a first ohmic contact region is formed on the other side of the base region;
a second source region is formed on one side of the upper part of the deep P-type region, which is in contact with the second groove, and a second ohmic contact region is formed on the other side of the deep P-type region;
the second oxidation layer medium covers the grid polysilicon, the grid oxide layer, the channel diode grid oxide layer and the first oxidation layer medium above;
the source metal is connected with the source polycrystalline silicon, the first ohmic contact region, the second ohmic contact region, the first source region and the second source region.
Further, the depth of the first groove is 0.5um to 3um, and the width of the first groove is 0.4um to 1um.
Further, the depth of the second groove is 0.7um to 3.5um, and the width of the second groove is 0.4um to 1um.
Furthermore, the depth of the source electrode polycrystalline silicon is larger than the junction depth of a PN junction formed in the P-type region.
Further, the thickness of the gate oxide layer of the trench diode is smaller than that of the gate oxide layer.
Further, the turn-on voltage of the trench diode is 0.5V to 2V.
A preparation method of a step trench gate SiC MOSFET with a trench diode comprises the following steps:
step S1: epitaxially growing an N-type drift region on an N-type SiC substrate;
step S2: a first hard mask is adopted as a blocking layer on the drift region, a deep P-type region is formed by ion implantation, and the first hard mask is removed; forming a P-type base region by ion implantation; using a second hard mask as a barrier layer, forming a first ohmic contact region and a second ohmic contact region of P-type heavy doping by ion implantation, and removing the second hard mask; forming a first source region and a second source region of N-type heavy doping by ion implantation by using a third hard mask as a barrier layer, and removing the third hard mask;
and step S3: photoetching and etching part of the source region, the base region and the deep P-type region to form a first groove structure, and performing ion implantation to form the P-type region; annealing after ion implantation, and activating the P-type region, the deep P-type region, the base region, the first ohmic contact region, the second ohmic contact region, the first source region and the second source region; thermally growing a gate oxide layer in the first groove structure, depositing grid polysilicon and etching;
and step S4: photoetching and etching the first groove structure to form a second groove structure;
step S5: thermally growing a channel diode gate oxide layer and a first oxide layer medium in the second groove structure;
step S6: depositing and etching source electrode polycrystalline silicon in the second groove;
step S7: depositing a second oxide layer medium and etching a hole area; and depositing source metal, thinning the back surface, and metalizing the back surface to form drain metal.
Has the advantages that:
1. according to the invention, the channel diode is formed by matching the source polysilicon, the channel diode gate oxide layer, the deep P-type region and the second source region, when the SiC MOSFET device is reversely conducted, the channel diode is conducted first, so that the conduction of a parasitic body diode of the device is avoided, the system power consumption loss of the device is effectively reduced, the bipolar degradation effect is prevented from occurring, the long-term reliability of the device is ensured, the freewheeling diode is built in the device, the high frequency and miniaturization of the device are facilitated, and the cost is reduced.
2. According to the invention, the P-type area is arranged below the first trench and the deep P-type area semi-surrounds the second trench, so that the electric field in the oxide layer at the corner of the stepped trench is reduced, meanwhile, the arrangement of the second trench structure can prevent the gate oxide layer in the first trench structure from being broken down, and the reliability of the oxide layer is improved; through the setting of source polycrystalline silicon in the second slot, can effectively shield grid signal under on off state, reduce the miller electric capacity of device, improve the switching speed of device.
3. According to the invention, through the arrangement that the thickness of the gate oxide layer of the channel diode is smaller than that of the gate oxide layer, the starting voltage of the channel diode is ensured to be lower than the MOS threshold voltage of the device, and the channel diode is ensured to be conducted first when the device is conducted in the reverse direction.
Drawings
FIG. 1 is a schematic diagram of a device structure of the present invention;
FIG. 2 is a schematic view of a device structure in the manufacturing method S2 according to the present invention;
FIG. 3 is a schematic view of the device structure in the manufacturing method S3 according to the present invention;
FIG. 4 is a schematic view of a device structure in the manufacturing method S4 of the present invention;
FIG. 5 is a schematic view of a device structure in the manufacturing method S5 of the present invention;
fig. 6 is a schematic view of a device structure in the manufacturing method S6 of the present invention.
Reference numerals: 1. a drain metal; 2. a drain region; 3. a drift region; 4. a P-type region; 5. a gate oxide layer; 6. grid polysilicon; 7. a trench diode gate oxide layer; 8. source polysilicon; 9. a first oxide layer dielectric; 10. a deep P-type region; 11. a base region; 12A, a first ohmic contact region; 12B, a second ohmic contact region; 13A, a first source region; 13B, a second source region; 14. a second oxide dielectric layer; 15. and a source metal.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Referring to fig. 1, a ladder trench gate SiC MOSFET structure with a trench diode includes: the transistor comprises drain metal 1, an N-type heavily doped drain region 2, an N-type doped drift region 3, a P-type region 4, a gate oxide layer 5, gate polysilicon 6, a trench diode gate oxide layer 7, source polysilicon 8, a first oxide layer medium 9, a deep P-type region 10, a P-type base region 11, P-type heavily doped first and second ohmic contact regions 12A and 12B, N, first and second heavily doped source regions 13A and 13B, a second oxide layer medium 14 and source metal 15;
the drain region 2 is positioned above the drain metal 1;
the drift region 3 is positioned above the drain region 2;
the base region 11 and the deep P-type region 10 are respectively positioned on two sides above the drift region 3;
the groove region is positioned between the base region 11 and the deep P-type region 10, a first groove is formed on one side, close to the base region 11, of the groove region, the gate oxide layer 5 is formed on the side wall of the groove region, a second groove is formed on one side, close to the deep P-type region 10, of the groove region, and the trench diode gate oxide layer 7 is formed on the side wall of the groove region; the second trench is deeper than the first trench; the gate polysilicon 6 is located in the first trench, the source polysilicon 8 is located in the second trench, and a first oxide dielectric 9 is located between the gate polysilicon 6 and the source polysilicon 8;
the deep P-type region 10 surrounds part of the bottom of the second trench; the P-type region 4 is located below the first trench;
a first source region 13A is formed on one side of the upper part of the base region 11, which is in contact with the first groove, and a first ohmic contact region 12A is formed on the other side of the base region;
a second source region 13B is formed on one side of the upper part of the deep P-type region 10, which is in contact with the second groove, and a second ohmic contact region 12B is formed on the other side of the deep P-type region;
the second oxidation layer medium 14 covers the gate polysilicon 6, the gate oxide layer 5, the channel diode gate oxide layer 7 and the first oxidation layer medium 9 above;
the source metal 15 is connected to the source polysilicon 8, the first ohmic contact region 12A, the second ohmic contact region 12B, the first source region 13A, and the second source region 13B.
The working principle is as follows:
through the cooperation setting of source polycrystalline silicon 8, trench diode gate oxide 7, dark P type district 10 and second source region 13B, formed the trench diode, when the reverse conduction of SiC MOSFET device, the trench diode switches on earlier, thereby avoided the parasitic body diode of device self to switch on, the system power consumption loss of device has effectively been reduced, prevent that bipolar degradation effect from taking place, the long-term reliability of device has been ensured, and with built-in the device of freewheeling diode, be favorable to the high frequency and the miniaturization of device, reduce cost simultaneously.
The P-type region 4 is arranged below the first trench, and the deep P-type region 10 semi-surrounds the second trench, so that the electric field in the oxide layer at the corner of the stepped trench is reduced, meanwhile, the gate oxide layer 5 in the first trench structure can be prevented from being broken down due to the arrangement of the second trench structure, and the reliability of the oxide layer is improved; through the setting of source polycrystalline silicon 8 in the second slot, can effectively shield grid signal under on-off state, reduce the miller electric capacity of device, improve the switching speed of device.
In one embodiment of the present invention, the depth of the first trench is 0.5um to 3um, and the width is 0.4um to 1um; the depth of the second groove is 0.7 um-3.5 um, and the width is 0.4 um-1 um.
The depth of the source electrode polycrystalline silicon 8 is larger than the junction depth of the PN junction formed by the P-type region 4.
The thickness of the trench diode gate oxide layer 7 is smaller than that of the gate oxide layer 5.
The typical thickness of the trench diode gate oxide layer 7 is 5 nm-40 nm, and the starting voltage is 0.5V-2V. The starting voltage of the body diode of the device at room temperature is about 2.5V-3V, and the setting of the starting voltage of the channel diode can ensure that the device is conducted before the body diode, so that the effective work of the channel diode is ensured.
Another embodiment of the present invention further provides a method for manufacturing a step trench gate SiC MOSFET having a trench diode, including the steps of:
step S1: epitaxially growing an N-type drift region 3 on an N-type SiC substrate;
step S2: as shown with reference to FIG. 2; a first hard mask is adopted as a blocking layer on the drift region 3, AL ion implantation with the energy of 100 KeV-2 MeV is carried out for 2-5 times to form a deep P-type region 10, and the first hard mask is removed; performing Al ion implantation with energy of 80 KeV-800 KeV for 2-5 times to form a P-type base region 11; using a second hard mask as a barrier layer, performing 2-4 times of AL ion implantation with energy of 40 KeV-800 KeV to form a first ohmic contact region 12A and a second ohmic contact region 12B which are P-type heavily doped, and removing the second hard mask; using the third hard mask as a barrier layer, performing N element or P element ion implantation with energy of 40-500 KeV for 2-4 times to form a first source region 13A and a second source region 13B which are heavily doped with N type, and removing the third hard mask;
and step S3: as shown with reference to FIG. 3; photoetching and etching part of the source region, the base region 11 and the deep P-type region 10 to form a first groove structure, and performing 2-5 times of AL ion implantation with energy of 100 KeV-600 KeV to form a P-type region 4; performing high-temperature annealing after ion implantation at 1500-1800 ℃ in an argon environment, and activating the P-type region 4, the deep P-type region 10, the base region 11, the first ohmic contact region 12A, the second ohmic contact region 12B, the first source region 13A and the second source region 13B; thermally growing a gate oxide layer 5 in the first groove structure, depositing and etching gate polysilicon 6;
and step S4: as shown with reference to FIG. 4; photoetching and etching the first groove structure to form a second groove structure;
step S5: as shown with reference to FIG. 5; thermally growing a channel diode gate oxide layer 7 and a first oxide layer medium 9 in the second groove structure;
step S6: as shown with reference to FIG. 6; depositing and etching source electrode polycrystalline silicon 8 in the second groove;
step S7: depositing a second oxide layer dielectric 14 and etching the hole region; and depositing source metal 15, thinning the back surface, and metalizing the back surface to form drain metal 1.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.
Claims (7)
1. A stepped trench gate SiC MOSFET structure with a trench diode,
the method comprises the following steps: the transistor comprises drain metal (1), an N-type heavily doped drain region (2), an N-type doped drift region (3), a P-type region (4), a gate oxide layer (5), gate polysilicon (6), a channel diode gate oxide layer (7), source polysilicon (8), a first oxide layer medium (9), a deep P-type region (10), a P-type base region (11), P-type heavily doped first and second ohmic contact regions (12A, 12B), N-type heavily doped first and second source regions (13A, 13B), a second oxide layer medium (14) and source metal (15);
the drain region (2) is positioned above the drain metal (1);
the drift region (3) is positioned above the drain region (2);
the base region (11) and the deep P-type region (10) are respectively positioned on two sides above the drift region (3);
the trench region is positioned between the base region (11) and the deep P type region (10), a first trench is formed on one side, close to the base region (11), of the trench region, the gate oxide layer (5) is formed on the side wall of the trench region, a second trench is formed on one side, close to the deep P type region (10), of the trench region, and the trench diode gate oxide layer (7) is formed on the side wall of the trench region; the second trench is deeper than the first trench; the gate poly (6) is located in the first trench, the source poly (8) is located in the second trench, and a first oxide dielectric (9) is located between the gate poly (6) and the source poly (8);
the deep P-type region (10) surrounds part of the bottom of the second groove; the P-type region (4) is positioned below the first groove;
a first source region (13A) is formed on one side of the upper part of the base region (11) which is in contact with the first groove, and a first ohmic contact region (12A) is formed on the other side of the upper part of the base region;
a second source region (13B) is formed on one side of the upper part of the deep P-type region (10) which is in contact with the second groove, and a second ohmic contact region (12B) is formed on the other side of the deep P-type region;
the second oxidation layer medium (14) covers the grid polysilicon (6), the grid oxide layer (5), the channel diode grid oxide layer (7) and the first oxidation layer medium (9) above;
the source metal (15) connects the source polysilicon (8), the first ohmic contact region (12A), the second ohmic contact region (12B), the first source region (13A), and the second source region (13B).
2. The structure of claim 1, wherein the first trench has a depth of 0.5um to 3um and a width of 0.4um to 1um.
3. The SiC MOSFET structure of claim 1, wherein the second trench has a depth of 0.7-3.5 um and a width of 0.4-1 um.
4. The ladder trench gate SiC MOSFET structure with a trench diode as claimed in claim 1, wherein the depth of the source polysilicon (8) is greater than the junction depth of the P-type region (4) forming the PN junction.
5. The ladder trench gate SiC MOSFET structure with trench diode of claim 1, characterized in that the trench diode gate oxide (7) thickness is smaller than the gate oxide (5) thickness.
6. The SiC MOSFET structure of claim 1, wherein the turn-on voltage of the trench diode is 0.5V to 2V.
7. A method of fabricating the stepped trench gate SiC MOSFET structure with a trench diode as recited in claim 1,
the method comprises the following steps:
step S1: epitaxially growing an N-type drift region (3) on an N-type SiC substrate;
step S2: a first hard mask is adopted as a barrier layer on the drift region (3), a deep P-type region (10) is formed by ion implantation, and the first hard mask is removed; forming a P-type base region (11) by ion implantation; using a second hard mask as a barrier layer, forming a first ohmic contact region (12A) and a second ohmic contact region (12B) which are P-type heavily doped by ion implantation, and removing the second hard mask; using a third hard mask as a barrier layer, forming a first source region (13A) and a second source region (13B) which are heavily doped in an N type by ion implantation, and removing the third hard mask;
and step S3: photoetching and etching part of the source region, the base region (11) and the deep P-type region (10) to form a first groove structure, and performing ion implantation to form the P-type region (4); annealing after ion implantation, and activating the P-type region (4), the deep P-type region (10), the base region (11), the first ohmic contact region (12A), the second ohmic contact region (12B), the first source region (13A) and the second source region (13B); thermally growing a gate oxide layer (5) in the first groove structure, depositing and etching gate polysilicon (6);
and step S4: photoetching and etching the first groove structure to form a second groove structure;
step S5: thermally growing a channel diode gate oxide layer (7) and a first oxide layer medium (9) in the second groove structure;
step S6: depositing and etching source polysilicon (8) in the second trench;
step S7: depositing a second oxide dielectric (14) and etching the hole region; and depositing source metal (15), thinning the back surface, and metalizing the back surface to form drain metal (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210876258.2A CN114937692B (en) | 2022-07-25 | 2022-07-25 | Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210876258.2A CN114937692B (en) | 2022-07-25 | 2022-07-25 | Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114937692A CN114937692A (en) | 2022-08-23 |
| CN114937692B true CN114937692B (en) | 2022-10-28 |
Family
ID=82867748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210876258.2A Active CN114937692B (en) | 2022-07-25 | 2022-07-25 | Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114937692B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116053316B (en) * | 2023-04-03 | 2023-06-06 | 北京昕感科技有限责任公司 | Mixed gate type SiC MOSFET cell structure, device and preparation method |
| CN116190451A (en) * | 2023-04-18 | 2023-05-30 | 杭州芯迈半导体技术有限公司 | Gate-source structure and manufacturing method thereof, asymmetric trench MOSFET and manufacturing method thereof |
| CN116525681B (en) * | 2023-05-18 | 2023-11-24 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET device integrating channel diode and manufacturing method |
| CN116646381A (en) * | 2023-07-27 | 2023-08-25 | 深圳市冠禹半导体有限公司 | High-efficiency SGTMOSFET device and preparation method thereof |
| CN117410345A (en) * | 2023-12-13 | 2024-01-16 | 深圳基本半导体有限公司 | Power device integrated with channel diode and preparation method thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109221A (en) * | 2008-10-31 | 2010-05-13 | Rohm Co Ltd | Semiconductor device |
| CN103262248A (en) * | 2010-12-10 | 2013-08-21 | 三菱电机株式会社 | Semiconductor device and production method therefor |
| CN105027292A (en) * | 2013-04-11 | 2015-11-04 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JP2016163049A (en) * | 2015-03-03 | 2016-09-05 | インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ | Semiconductor device including trench structure including a gate electrode for diode region and contact structure |
| JP2018046255A (en) * | 2016-09-16 | 2018-03-22 | 株式会社東芝 | Semiconductor device |
| CN109904220A (en) * | 2019-03-18 | 2019-06-18 | 电子科技大学 | Groove gate type silicon carbide MOSFET device and preparation method |
| CN111403487A (en) * | 2020-05-07 | 2020-07-10 | 创能动力科技有限公司 | Semiconductor device integrating MOSFET and diode and manufacturing method thereof |
| WO2021254616A1 (en) * | 2020-06-18 | 2021-12-23 | Dynex Semiconductor Limited | Sic mosfet with asymmetric trench oxide and method of manufacture |
| CN113990923A (en) * | 2021-10-20 | 2022-01-28 | 电子科技大学 | Silicon carbide double-groove MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with trench diode |
| CN114784111A (en) * | 2022-05-12 | 2022-07-22 | 华东师范大学 | SBR-MOSFET composite semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011079747A1 (en) * | 2010-07-27 | 2012-02-02 | Denso Corporation | Semiconductor device with switching element and freewheeling diode, and control method therefor |
| US9620637B2 (en) * | 2013-05-24 | 2017-04-11 | Infineon Technologies Ag | Semiconductor device comprising a gate electrode connected to a source terminal |
| KR102206965B1 (en) * | 2017-11-01 | 2021-01-25 | 수 조우 오리엔탈 세미컨덕터 콤퍼니 리미티드 | Trench type power transistor |
| CN111312802B (en) * | 2020-02-27 | 2022-01-28 | 电子科技大学 | Low-starting-voltage and low-on-resistance silicon carbide diode and preparation method thereof |
-
2022
- 2022-07-25 CN CN202210876258.2A patent/CN114937692B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109221A (en) * | 2008-10-31 | 2010-05-13 | Rohm Co Ltd | Semiconductor device |
| CN103262248A (en) * | 2010-12-10 | 2013-08-21 | 三菱电机株式会社 | Semiconductor device and production method therefor |
| CN105027292A (en) * | 2013-04-11 | 2015-11-04 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JP2016163049A (en) * | 2015-03-03 | 2016-09-05 | インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ | Semiconductor device including trench structure including a gate electrode for diode region and contact structure |
| JP2018046255A (en) * | 2016-09-16 | 2018-03-22 | 株式会社東芝 | Semiconductor device |
| CN109904220A (en) * | 2019-03-18 | 2019-06-18 | 电子科技大学 | Groove gate type silicon carbide MOSFET device and preparation method |
| CN111403487A (en) * | 2020-05-07 | 2020-07-10 | 创能动力科技有限公司 | Semiconductor device integrating MOSFET and diode and manufacturing method thereof |
| WO2021254616A1 (en) * | 2020-06-18 | 2021-12-23 | Dynex Semiconductor Limited | Sic mosfet with asymmetric trench oxide and method of manufacture |
| CN113990923A (en) * | 2021-10-20 | 2022-01-28 | 电子科技大学 | Silicon carbide double-groove MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with trench diode |
| CN114784111A (en) * | 2022-05-12 | 2022-07-22 | 华东师范大学 | SBR-MOSFET composite semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114937692A (en) | 2022-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114937692B (en) | Stepped trench gate SiC MOSFET structure with trench diode and preparation method thereof | |
| TWI805991B (en) | Metal-oxide-semiconductor field-effect transistor device | |
| TWI441340B (en) | Planar srfet using no additional masks and layout method | |
| KR101396611B1 (en) | Semiconductor device | |
| CN114937693B (en) | Trench gate SiC MOSFET device with double-channel diode and preparation method thereof | |
| JP6532549B2 (en) | Semiconductor device | |
| JP5646044B2 (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| CN116387362A (en) | HJD integrated SiC UMOSFET device and preparation method thereof | |
| CN114361250A (en) | Mosfet with enhanced high frequency performance | |
| CN114792734A (en) | Double-groove silicon carbide MOSFET and preparation method thereof | |
| CN111755521A (en) | Silicon carbide UMOSFET device integrated with TJBS | |
| CN114497201A (en) | Field effect transistor of integrated body relay diode, preparation method thereof and power device | |
| WO2024026904A1 (en) | Preparation method for and structure of low-voltage super-junction trench mos device | |
| CN116314302A (en) | Manufacturing method of groove type silicon carbide MOSFET device | |
| CN115188812A (en) | MOSFET with split planar gate structure | |
| CN209981224U (en) | Silicon carbide MOSFET device with L-shaped masking layer structure | |
| CN114530504A (en) | High-threshold SiC MOSFET device and manufacturing method thereof | |
| CN107863386B (en) | Trench MOS device integrated with TMBS structure and manufacturing method thereof | |
| CN117238968B (en) | Trench gate silicon carbide MOSFET device and preparation method thereof | |
| CN115295612B (en) | Single-side channel RC-IGBT device, preparation method thereof and chip | |
| CN111755520B (en) | JBS (junction-junction | |
| CN112018162B (en) | 4H-SiC side gate integrated SBD MOSFET device and preparation method thereof | |
| CN219419037U (en) | Groove type silicon carbide MOSFET device | |
| CN115274828B (en) | RC-LIGBT device, preparation method thereof and chip | |
| CN117174757B (en) | Super-junction trench gate silicon carbide MOSFET and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |