JP2010109221A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010109221A
JP2010109221A JP2008280953A JP2008280953A JP2010109221A JP 2010109221 A JP2010109221 A JP 2010109221A JP 2008280953 A JP2008280953 A JP 2008280953A JP 2008280953 A JP2008280953 A JP 2008280953A JP 2010109221 A JP2010109221 A JP 2010109221A
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semiconductor layer
type semiconductor
trench
region
semiconductor device
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Yuuki Nakano
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench structure that allows circuit size reduction. <P>SOLUTION: The semiconductor device A includes: a first n-type semiconductor layer 11; a second n-type semiconductor layer 12; a p-type semiconductor layer 13; a trench 3 that penetrates the p-type semiconductor layer 13 and reaches the second n-type semiconductor layer 12; an n-type semiconductor region 14; a gate insulating portion 5; a gate electrode 41 which is insulated from the second n-type semiconductor layer 12, the p-type semiconductor layer 13, and the n-type semiconductor region 14 by the gate insulating portion 5, and at least a portion of which is formed in the trench 3; and a source electrode 42 that is electrically continuous with the n-type semiconductor region 14. The semiconductor device A also includes a Schottky electrode d1 that is electrically continuous with the source electrode 42 and is insulated from the p-type semiconductor layer 13, the n-type semiconductor region 14, and the gate electrode 41. The Schottky electrode d1 and the second n-type semiconductor layer 12 are joined to each other in the trench 3, thereby forming a diode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、トレンチ構造を有する半導体装置に関する。   The present invention relates to a semiconductor device having a trench structure.

図１１は、従来のトレンチ構造を有する縦型の絶縁ゲート型半導体装置の断面の一例を示している。この半導体装置９Ａは、ＭＯＳＦＥＴとして、一般にスイッチング回路に用いられる。半導体装置９Ａは、第１ｎ型半導体層９１１、第２ｎ型半導体層９１２、ｐ型半導体層９１３、ｎ型半導体領域９１４、トレンチ９３、ゲート電極９４１、ゲート絶縁層９５、ソース電極９４２およびドレイン電極９４３を備えている。   FIG. 11 shows an example of a cross section of a vertical insulated gate semiconductor device having a conventional trench structure. The semiconductor device 9A is generally used as a MOSFET in a switching circuit. The semiconductor device 9A includes a first n-type semiconductor layer 911, a second n-type semiconductor layer 912, a p-type semiconductor layer 913, an n-type semiconductor region 914, a trench 93, a gate electrode 941, a gate insulating layer 95, a source electrode 942, and a drain electrode 943. It has.

第１ｎ型半導体層９１１は、半導体装置９Ａの土台となっている。第２ｎ型半導体層９１２は、第１ｎ型半導体層９１１の上に形成されている。ｐ型半導体層９１３は、第２ｎ型半導体層９１２の上に形成されている。ｎ型半導体領域９１４は、ｐ型半導体層９１３の上に形成されている。トレンチ９３は、ｐ型半導体層９１３を貫通し、第２ｎ型半導体層９１２まで達している。ゲート絶縁層９５は、ゲート電極９４１と、第２ｎ型半導体層９１２、ｐ型半導体層９１３およびｎ型半導体領域９１４とを絶縁している。   The first n-type semiconductor layer 911 is a base of the semiconductor device 9A. The second n-type semiconductor layer 912 is formed on the first n-type semiconductor layer 911. The p-type semiconductor layer 913 is formed on the second n-type semiconductor layer 912. The n-type semiconductor region 914 is formed on the p-type semiconductor layer 913. The trench 93 penetrates the p-type semiconductor layer 913 and reaches the second n-type semiconductor layer 912. The gate insulating layer 95 insulates the gate electrode 941 from the second n-type semiconductor layer 912, the p-type semiconductor layer 913, and the n-type semiconductor region 914.

半導体装置９Ａを含む回路には、半導体装置９Ａと、この半導体装置に逆並列接続されたダイオードとが設けられている。ゲート電極９４１に一定値以上の電圧を印加した場合、トレンチ９３に沿って、ｐ型半導体層９１３内にチャネル領域が形成される。このとき、ソース電極９４２に対するドレイン電極９４３の電圧が正の値になった場合に、上記チャネル領域を電流が流れる。一方、ソース電極９４２に対するドレイン電極９４３の電圧が負の値になったとき、上記ダイオードを電流が流れ、上記チャネル領域に電流が流れないようになっている。   A circuit including the semiconductor device 9A is provided with the semiconductor device 9A and a diode connected in reverse parallel to the semiconductor device. When a voltage higher than a certain value is applied to the gate electrode 941, a channel region is formed in the p-type semiconductor layer 913 along the trench 93. At this time, when the voltage of the drain electrode 943 with respect to the source electrode 942 becomes a positive value, a current flows through the channel region. On the other hand, when the voltage of the drain electrode 943 with respect to the source electrode 942 becomes a negative value, current flows through the diode, and current does not flow through the channel region.

従来の半導体装置９Ａを含む回路においては、上記ダイオードを設けるために、半導体装置９Ａが設けられたチップの占める領域のみでなく、それ以外の領域も必要となっていた。そのため、半導体装置９Ａを含む回路を小型化したいといった要望が、十分に満たされていなかった。   In a circuit including the conventional semiconductor device 9A, in order to provide the diode, not only the region occupied by the chip provided with the semiconductor device 9A but also other regions are required. For this reason, the demand for downsizing the circuit including the semiconductor device 9A has not been sufficiently satisfied.

特開平０１−１０２１７４号公報Japanese Patent Laid-Open No. 01-102174

本発明は、上記した事情のもとで考え出されたものであって、回路の小型化を可能とする、トレンチ構造を有する半導体装置を提供することをその課題とする。   The present invention has been conceived under the circumstances described above, and an object thereof is to provide a semiconductor device having a trench structure that enables a circuit to be miniaturized.

本発明によって提供される半導体装置は、第１の導電型をもつ第１半導体層と、この第１半導体層上に設けられ、上記第１の導電型と反対の第２の導電型を持つ第２半導体層と、この第２半導体層を貫通して上記第１半導体層に達するトレンチと、上記第２半導体層上に、かつ、上記トレンチの周囲に形成された上記第１の導電型をもつ半導体領域と、上記トレンチ内部に形成された絶縁部と、この絶縁部により、上記第１半導体層、上記第２半導体層および上記半導体領域と絶縁されており、少なくとも一部が上記トレンチ内部に形成されたゲート電極と、この半導体領域と導通しているソース電極と、を備えた半導体装置であって、導電体、または、上記第２の導電型をもつ半導体から構成される追加の領域をさらに備え、この追加の領域は、上記ソース電極と導通しており、かつ、上記第２半導体層、上記半導体領域および上記ゲート電極と絶縁されており、上記追加の領域と上記第１半導体層とが上記トレンチ内で接合されることにより、ダイオードを形成していることを特徴とする。   A semiconductor device provided by the present invention includes a first semiconductor layer having a first conductivity type and a second conductivity type provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type. Two semiconductor layers, a trench that passes through the second semiconductor layer and reaches the first semiconductor layer, and has the first conductivity type formed on the second semiconductor layer and around the trench. A semiconductor region, an insulating portion formed inside the trench, and the insulating portion are insulated from the first semiconductor layer, the second semiconductor layer, and the semiconductor region, and at least a part is formed inside the trench. A semiconductor device comprising a gate electrode and a source electrode electrically connected to the semiconductor region, and further comprising an additional region made of a conductor or a semiconductor having the second conductivity type. Prepare for this additional region Is electrically connected to the source electrode and insulated from the second semiconductor layer, the semiconductor region, and the gate electrode, and the additional region and the first semiconductor layer are joined in the trench. Thus, a diode is formed.

このような構成においては、上記トレンチの外部に、上記ダイオードに相当するダイオードを設ける必要がない。そのため、上記半導体装置を用いた回路の小型化を図ることができる。   In such a configuration, it is not necessary to provide a diode corresponding to the diode outside the trench. Therefore, the size of the circuit using the semiconductor device can be reduced.

本発明の好ましい実施の形態においては、上記第１半導体層、上記第２半導体層、および、上記半導体領域は、ＳｉＣ、ＧａＮ、ダイヤモンド、ＺｎＯ、またはＡｌＧａＮから構成されており、上記追加の領域は、上記導電体からなり、上記ダイオードは、ショットキーバリヤダイオードである。   In a preferred embodiment of the present invention, the first semiconductor layer, the second semiconductor layer, and the semiconductor region are composed of SiC, GaN, diamond, ZnO, or AlGaN, and the additional region is The diode is a Schottky barrier diode.

本発明の好ましい実施の形態においては、上記導電体は、上記トレンチの底面から上記トレンチの側面にわたって接している。このような構成によれば、上記半導体装置を使用する際、上記底面から上記側面までの部分に電界集中することを抑止できる。そのため、上記半導体装置において、絶縁破壊が起こりにくくなる。   In a preferred embodiment of the present invention, the conductor is in contact from the bottom surface of the trench to the side surface of the trench. According to such a configuration, when the semiconductor device is used, it is possible to prevent the electric field from being concentrated on the portion from the bottom surface to the side surface. Therefore, dielectric breakdown is less likely to occur in the semiconductor device.

本発明の好ましい実施の形態においては、上記追加の領域と上記ソース電極とを導通させる導電部をさらに備え、この導電部は、上記トレンチの開口部から、上記トレンチの深さ方向に沿って延びており、かつ、上記ゲート電極を貫通している。このような構成によれば、上記ダイオードが上記トレンチ内部に形成されているにもかかわらず、上記第２半導体層におけるチャネルの形成が妨げられにくい。そのため、上記トレンチの内部に上記ダイオードが形成されていない場合と比べて、上記チャネルの抵抗を同程度に維持できる。   In a preferred embodiment of the present invention, the semiconductor device further includes a conductive portion that conducts the additional region and the source electrode, and the conductive portion extends from the opening of the trench along the depth direction of the trench. And penetrates through the gate electrode. According to such a configuration, although the diode is formed inside the trench, formation of a channel in the second semiconductor layer is hardly hindered. Therefore, the resistance of the channel can be maintained at the same level as compared with the case where the diode is not formed inside the trench.

本発明のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。   Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

以下、本発明の好ましい実施の形態につき、図面を参照して具体的に説明する。   Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

図１に、本発明の実施形態にかかる半導体装置Ａの要部平面図を示している。なお、図２に示すソース電極は、理解の便宜上省略している。図２には、図１のＩＩ−ＩＩ線に沿った要部断面図を示している。図３には、図１のＩＩＩ−ＩＩＩ線に沿った要部断面図を示している。   FIG. 1 shows a plan view of a main part of a semiconductor device A according to an embodiment of the present invention. Note that the source electrode shown in FIG. 2 is omitted for the sake of understanding. FIG. 2 shows a cross-sectional view of the main part along the line II-II in FIG. FIG. 3 shows a cross-sectional view of the main part along the line III-III in FIG.

図２に示すように、半導体装置Ａは、第１ｎ型半導体層１１、第２ｎ型半導体層１２、ｐ型半導体層１３、高濃度ｐ型半導体領域１３ａ、ｎ型半導体領域１４、トレンチ３、ゲート電極４１、ゲート絶縁部５、ショットキー電極ｄ１、接続導電部ｄ２、ソース電極４２、ドレイン電極４３および層間絶縁膜６を備えている。   As shown in FIG. 2, the semiconductor device A includes a first n-type semiconductor layer 11, a second n-type semiconductor layer 12, a p-type semiconductor layer 13, a high-concentration p-type semiconductor region 13a, an n-type semiconductor region 14, a trench 3, and a gate. The electrode 41, the gate insulating part 5, the Schottky electrode d1, the connection conductive part d2, the source electrode 42, the drain electrode 43, and the interlayer insulating film 6 are provided.

第１ｎ型半導体層１１は、ＳｉＣに高濃度の不純物が添加された材質からなる基板であり、半導体装置Ａの土台となっている。第２ｎ型半導体層１２は、第１ｎ型半導体層１１の上に形成されている。第２ｎ型半導体層１２は、ＳｉＣに低濃度の不純物が添加された材質からなる。第２ｎ型半導体層１２の深さ方向ｘにおける大きさは、約１０μｍである。ｐ型半導体層１３は、第２ｎ型半導体層１２の上に形成されている。ｐ型半導体層１３の深さ方向ｘの大きさは、約０．７μｍである。ｎ型半導体領域１４は、ｐ型半導体層１３の上に形成されている。ｎ型半導体領域１４の深さ方向ｘの大きさは、約０．３μｍである。高濃度ｐ型半導体領域１３ａは、ｐ型半導体層１３の上に形成されている。   The first n-type semiconductor layer 11 is a substrate made of a material obtained by adding a high-concentration impurity to SiC, and serves as a base for the semiconductor device A. The second n-type semiconductor layer 12 is formed on the first n-type semiconductor layer 11. The second n-type semiconductor layer 12 is made of a material obtained by adding a low concentration impurity to SiC. The size of the second n-type semiconductor layer 12 in the depth direction x is about 10 μm. The p-type semiconductor layer 13 is formed on the second n-type semiconductor layer 12. The size of the p-type semiconductor layer 13 in the depth direction x is about 0.7 μm. The n-type semiconductor region 14 is formed on the p-type semiconductor layer 13. The size of the n-type semiconductor region 14 in the depth direction x is about 0.3 μm. The high concentration p-type semiconductor region 13 a is formed on the p-type semiconductor layer 13.

トレンチ３は、ｐ型半導体層１３およびｎ型半導体領域１４を貫通して、第２ｎ型半導体層１２に達するように形成されている。トレンチ３の内部には、ゲート電極４１、ゲート絶縁部５、ショットキー電極ｄ１および接続導電部ｄ２が形成されている。ゲート電極４１は、たとえばポリシリコンからなっている。ゲート絶縁部５は、ショットキー電極ｄ１の上に形成されている。ゲート絶縁部５は、本実施形態においては、ＳｉＯ2より構成されている。ゲート絶縁部５は、ゲート電極４１を、第２ｎ型半導体層１２、ｐ型半導体層１３、ｎ型半導体領域１４、ショットキー電極ｄ１および接続導電部ｄ２から絶縁している。さらに、ゲート絶縁部５は、ショットキー電極ｄ１および接続導電部ｄ２を、ｐ型半導体層１３およびｎ型半導体領域１４から絶縁している。 The trench 3 is formed so as to penetrate the p-type semiconductor layer 13 and the n-type semiconductor region 14 and reach the second n-type semiconductor layer 12. Inside the trench 3, a gate electrode 41, a gate insulating portion 5, a Schottky electrode d1, and a connection conductive portion d2 are formed. The gate electrode 41 is made of, for example, polysilicon. The gate insulating portion 5 is formed on the Schottky electrode d1. The gate insulating portion 5 is made of SiO 2 in the present embodiment. The gate insulating portion 5 insulates the gate electrode 41 from the second n-type semiconductor layer 12, the p-type semiconductor layer 13, the n-type semiconductor region 14, the Schottky electrode d1, and the connection conductive portion d2. Furthermore, the gate insulating part 5 insulates the Schottky electrode d1 and the connection conductive part d2 from the p-type semiconductor layer 13 and the n-type semiconductor region 14.

ショットキー電極ｄ１は、トレンチ３の底部３ａからトレンチ３の側部３ｂにわたって、トレンチ３に接するように形成されている。ショットキー電極ｄ１は、第２ｎ型半導体層１２と接合している。これにより、ショットキーバリヤダイオードが形成されている。ショットキー電極ｄ１は、ポリシリコンにより構成されていることが好ましい。また、ショットキー電極ｄ１の材料に、ポリシリコン以外の導電体である、Ｎｉ、Ｔｉ、ＴｉＮ、Ｍｏなどの金属を用いてもよい。   The Schottky electrode d <b> 1 is formed so as to be in contact with the trench 3 from the bottom 3 a of the trench 3 to the side 3 b of the trench 3. The Schottky electrode d1 is joined to the second n-type semiconductor layer 12. Thereby, a Schottky barrier diode is formed. The Schottky electrode d1 is preferably made of polysilicon. Further, a metal such as Ni, Ti, TiN, or Mo, which is a conductor other than polysilicon, may be used for the material of the Schottky electrode d1.

接続導電部ｄ２は、ショットキー電極ｄ１とソース電極４２とを導電させるためのものである。接続導電部ｄ２は、トレンチ３のほぼ中央に形成され、ソース電極４２から深さ方向ｘに沿って延びている。また、接続導電部ｄ２は、ゲート絶縁部５を介して２つのゲート電極４１に挟まれている。すなわち、接続導電部ｄ２は、ゲート電極４１を貫通している。   The connection conductive portion d2 is for conducting the Schottky electrode d1 and the source electrode 42. The connection conductive portion d2 is formed at substantially the center of the trench 3 and extends from the source electrode 42 along the depth direction x. The connection conductive portion d2 is sandwiched between the two gate electrodes 41 with the gate insulating portion 5 interposed therebetween. In other words, the connection conductive portion d2 passes through the gate electrode 41.

ソース電極４２は、たとえばＡｌからなり、ｎ型半導体領域１４および高濃度ｐ型半導体領域１３ａと接している。ドレイン電極４３も、たとえばＡｌからなり、第１ｎ型半導体層１１と接している。ドレイン電極４３は、第２ｎ型半導体層１２が形成された側と、第１ｎ型半導体層１１を挟んで反対側に形成されている。層間絶縁膜６は、ゲート電極４１を覆うように形成されている。   The source electrode 42 is made of, for example, Al and is in contact with the n-type semiconductor region 14 and the high-concentration p-type semiconductor region 13a. The drain electrode 43 is also made of, for example, Al and is in contact with the first n-type semiconductor layer 11. The drain electrode 43 is formed on the side where the second n-type semiconductor layer 12 is formed and on the opposite side across the first n-type semiconductor layer 11. The interlayer insulating film 6 is formed so as to cover the gate electrode 41.

図３には、図１のＩＩＩ−ＩＩＩ線に沿った要部断面図を示している。図３において、図２に記載した接続導電部ｄ２は記載されていない。だが、図３に示した半導体装置Ａにおけるショットキー電極ｄ１は、図２に示した接続導電部ｄ２によりソース電極４２と導通している。   FIG. 3 shows a cross-sectional view of the main part along the line III-III in FIG. In FIG. 3, the connection conductive portion d2 shown in FIG. 2 is not shown. However, the Schottky electrode d1 in the semiconductor device A shown in FIG. 3 is electrically connected to the source electrode 42 by the connection conductive portion d2 shown in FIG.

次に、半導体装置Ａの製造方法の一例について、図４〜図１０を参照しつつ以下に説明する。なお、図３に示した断面部分の製造工程は、図２に示した接続導電部ｄ２およびその周囲のゲート絶縁部５を形成する工程を除き、図２に示した断面部分の製造工程と同一である。そのため、図３に示した断面部分の製造工程の記載は省略する。   Next, an example of a method for manufacturing the semiconductor device A will be described below with reference to FIGS. 3 is the same as the manufacturing process of the cross-sectional portion shown in FIG. 2 except the step of forming the connection conductive portion d2 and the surrounding gate insulating portion 5 shown in FIG. It is. Therefore, description of the manufacturing process of the cross-sectional part shown in FIG. 3 is abbreviate | omitted.

まず、図４のように、第１ｎ型半導体層１１となる半導体基板を準備する。次に、この基板の表面側に、エピタキシャル結晶成長法により、第２ｎ型半導体層１２を形成する。次に、第２ｎ型半導体層１２の上面に所定形状のマスクを施すなどして、不純物イオン（ｎ型またはｐ型）を注入し、ｐ型半導体層１３、ｎ型半導体領域１４および高濃度ｐ型半導体領域１３ａを形成する。そして、トレンチ３を形成する。   First, as shown in FIG. 4, a semiconductor substrate to be the first n-type semiconductor layer 11 is prepared. Next, the second n-type semiconductor layer 12 is formed on the surface side of the substrate by an epitaxial crystal growth method. Next, impurity ions (n-type or p-type) are implanted, for example, by applying a mask having a predetermined shape on the upper surface of the second n-type semiconductor layer 12, and the p-type semiconductor layer 13, the n-type semiconductor region 14, and the high-concentration p. A type semiconductor region 13a is formed. Then, the trench 3 is formed.

次に、図５のように、ポリシリコンからなるショットキー電極ｄ１を、トレンチ３の底部３ａに形成する。次に、図６に示すように、ｎ型半導体領域１４の露出面、トレンチ３の側部３ｂおよびショットキー電極ｄ１の上面を熱酸化し、ゲート絶縁部５を形成する。なお、ショットキー電極ｄ１がＴｉなどの金属である場合、プラズマＣＶＤ法により、ゲート絶縁部５を形成する。   Next, a Schottky electrode d1 made of polysilicon is formed on the bottom 3a of the trench 3 as shown in FIG. Next, as shown in FIG. 6, the exposed surface of the n-type semiconductor region 14, the side portion 3 b of the trench 3, and the upper surface of the Schottky electrode d <b> 1 are thermally oxidized to form the gate insulating portion 5. When the Schottky electrode d1 is a metal such as Ti, the gate insulating portion 5 is formed by plasma CVD.

次に、図７のように、トレンチ３内部に形成されたゲート絶縁部５上に、ゲート電極４１を形成する。そして、ゲート電極４１およびゲート絶縁部５の上面を平らにした後、層間絶縁膜６を積層させる。   Next, as shown in FIG. 7, the gate electrode 41 is formed on the gate insulating portion 5 formed inside the trench 3. Then, after flattening the upper surfaces of the gate electrode 41 and the gate insulating portion 5, the interlayer insulating film 6 is laminated.

次に、図８のように、図７に示した層間絶縁膜６およびゲート絶縁部５のうちトレンチ３上部以外に積層されているものを、取り除く。次に、図９のように、層間絶縁膜６における頂部の中央近傍から、ゲート絶縁部５まで、溝ｍを形成する。   Next, as shown in FIG. 8, the interlayer insulating film 6 and the gate insulating portion 5 shown in FIG. Next, as shown in FIG. 9, a groove m is formed from the vicinity of the center of the top of the interlayer insulating film 6 to the gate insulating portion 5.

次に、図１０に示すように、ゲート電極４１のうち、溝ｍ内部で露出している部分を熱酸化する。次に、ゲート絶縁部５のうち溝ｍの底の部分５ｍを取り除く。次に、溝ｍに、図２に示した接続導電部ｄ２を形成する。その後、ソース電極４２、ドレイン電極４３などを形成する。これにより、半導体装置Ａの製造が完成する。   Next, as shown in FIG. 10, a portion of the gate electrode 41 exposed inside the groove m is thermally oxidized. Next, the bottom portion 5m of the groove m in the gate insulating portion 5 is removed. Next, the connection conductive portion d2 shown in FIG. 2 is formed in the groove m. Thereafter, the source electrode 42, the drain electrode 43, and the like are formed. Thereby, the manufacture of the semiconductor device A is completed.

次に、本実施形態にかかる半導体装置Ａの作用について説明する。   Next, the operation of the semiconductor device A according to the present embodiment will be described.

本実施形態においては、トレンチ３の外部に、第２ｎ型半導体層１２とショットキー電極ｄ１により形成されるダイオードに相当するダイオードを設ける必要がない。そのため、半導体装置Ａを用いた回路の小型化を図ることができる。   In the present embodiment, it is not necessary to provide a diode corresponding to the diode formed by the second n-type semiconductor layer 12 and the Schottky electrode d1 outside the trench 3. Therefore, the circuit using the semiconductor device A can be reduced in size.

半導体装置Ａを使用する際、トレンチ３の底部３ａから側部３ｂまでの部分に電界集中することを抑止できる。そのため、半導体装置Ａにおいて、絶縁破壊が起こりにくくなる。   When the semiconductor device A is used, it is possible to prevent the electric field from being concentrated on the portion from the bottom 3a to the side 3b of the trench 3. Therefore, dielectric breakdown is less likely to occur in the semiconductor device A.

上記ダイオードがトレンチ３の内部に形成されているにもかかわらず、ｐ型半導体層１３におけるチャネルの形成が妨げられにくい。そのため、トレンチ３の内部に上記ダイオードが形成されていない場合と比べて、上記チャネルの抵抗を同程度に維持できる。   Despite the formation of the diode in the trench 3, the formation of the channel in the p-type semiconductor layer 13 is difficult to be hindered. Therefore, compared with the case where the diode is not formed inside the trench 3, the resistance of the channel can be maintained at the same level.

本発明に係る半導体装置は、上述した実施形態に限定されるものではない。本発明に係る半導体装置の各部の具体的な構成は、種々に設計変更自在である。たとえば、ショットキー電極ｄ１が、トレンチ３の底部３ａの全体を覆っていなくても良い。ショットキー電極ｄ１と第２ｎ型半導体層１２との接する幅方向ｙの大きさが、接続導電部ｄ２の幅方向ｙの大きさと同程度でもよい。   The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways. For example, the Schottky electrode d1 does not have to cover the entire bottom 3a of the trench 3. The size in the width direction y between the Schottky electrode d1 and the second n-type semiconductor layer 12 may be approximately the same as the size in the width direction y of the connection conductive portion d2.

上記実施形態では、第１半導体層、第２半導体層、および半導体領域がＳｉＣにより構成されている例を示したが、本発明の範囲はこれに限られない。また、本発明にかかるダイオードがショットキーバリヤダイオードである場合に、上記第１半導体層、上記第２半導体層、および上記半導体領域は、ＳｉＣ以外のワイドバンドギャップ半導体から構成されていてもよい。たとえば、ＧａＮ、ダイヤモンド、ＺｎＯ、または、ＡｌＧａＮなどが挙げられる。   In the said embodiment, although the 1st semiconductor layer, the 2nd semiconductor layer, and the semiconductor region showed the example comprised by SiC, the range of this invention is not restricted to this. When the diode according to the present invention is a Schottky barrier diode, the first semiconductor layer, the second semiconductor layer, and the semiconductor region may be made of a wide band gap semiconductor other than SiC. For example, GaN, diamond, ZnO, AlGaN, etc. are mentioned.

また、実施形態におけるショットキー電極ｄ１をｐ型の半導体とすることにより、ｐｎ接合のダイオードを形成してもよい。   In addition, a pn junction diode may be formed by using a Schottky electrode d1 in the embodiment as a p-type semiconductor.

本発明の実施形態にかかる半導体装置Ａの要部平面図である。It is a principal part top view of the semiconductor device A concerning embodiment of this invention. 図１のＩＩ−ＩＩ線に沿った要部断面図である。It is principal part sectional drawing along the II-II line of FIG. 図１のＩＩＩ−ＩＩＩ線に沿った要部断面図である。It is principal part sectional drawing along the III-III line of FIG. 本発明に係る半導体装置Ａの製造工程の一工程を示す図である。It is a figure which shows 1 process of the manufacturing process of the semiconductor device A which concerns on this invention. 図４に続く製造工程の一工程を示す図である。FIG. 5 is a diagram showing a step in the manufacturing process subsequent to FIG. 4. 図５に続く製造工程の一工程を示す図である。FIG. 6 is a diagram illustrating one process of the manufacturing process subsequent to FIG. 5. 図６に続く製造工程の一工程を示す図である。FIG. 7 is a diagram showing one step in the manufacturing process following FIG. 6. 図７に続く製造工程の一工程を示す図である。FIG. 8 is a diagram showing one process of the manufacturing process following FIG. 7. 図８に続く製造工程の一工程を示す図である。FIG. 9 is a diagram showing one step in the manufacturing process following FIG. 8. 図９に続く製造工程の一工程を示す図である。FIG. 10 is a diagram showing one step in the manufacturing process following FIG. 9. 従来の半導体装置の一例を示す要部断面図である。It is principal part sectional drawing which shows an example of the conventional semiconductor device.

符号の説明Explanation of symbols

Ａ 半導体装置
１１ 第１ｎ型半導体層
１２ 第２ｎ型半導体層
１３ ｐ型半導体層
１４ ｎ型半導体領域
３ トレンチ
４１ ゲート電極
４２ ソース電極
４３ ドレイン電極
５ ゲート絶縁部
６ 層間絶縁膜
ｘ 深さ方向
ｙ 幅方向
ｍ 溝
ｄ１ ショットキー電極
ｄ２ 接続導電部 A semiconductor device 11 first n-type semiconductor layer 12 second n-type semiconductor layer 13 p-type semiconductor layer 14 n-type semiconductor region 3 trench 41 gate electrode 42 source electrode 43 drain electrode 5 gate insulating portion 6 interlayer insulating film x depth direction y width Direction m Groove d1 Schottky electrode d2 Connection conductive part

Claims (4)

第１の導電型をもつ第１半導体層と、
この第１半導体層上に設けられ、上記第１の導電型と反対の第２の導電型を持つ第２半導体層と、
この第２半導体層を貫通して上記第１半導体層に達するトレンチと、
上記第２半導体層上に、かつ、上記トレンチの周囲に形成された上記第１の導電型をもつ半導体領域と、
上記トレンチ内部に形成された絶縁部と、
この絶縁部により、上記第１半導体層、上記第２半導体層および上記半導体領域と絶縁されており、少なくとも一部が上記トレンチ内部に形成されたゲート電極と、
この半導体領域と導通しているソース電極と、
を備えた半導体装置であって、
導電体、または、上記第２の導電型をもつ半導体から構成される追加の領域をさらに備え、
この追加の領域は、上記ソース電極と導通しており、かつ、上記第２半導体層、上記半導体領域および上記ゲート電極と絶縁されており、
上記追加の領域と上記第１半導体層とが上記トレンチ内で接合されることにより、ダイオードを形成していることを特徴とする、半導体装置。 A first semiconductor layer having a first conductivity type;
A second semiconductor layer provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;
A trench that penetrates through the second semiconductor layer and reaches the first semiconductor layer;
A semiconductor region having the first conductivity type formed on the second semiconductor layer and around the trench;
An insulating part formed inside the trench;
A gate electrode which is insulated from the first semiconductor layer, the second semiconductor layer, and the semiconductor region by the insulating portion, and at least a part of which is formed inside the trench;
A source electrode in conduction with the semiconductor region;
A semiconductor device comprising:
An additional region composed of a conductor or a semiconductor having the second conductivity type;
The additional region is electrically connected to the source electrode, and is insulated from the second semiconductor layer, the semiconductor region, and the gate electrode.
The semiconductor device, wherein the additional region and the first semiconductor layer are joined in the trench to form a diode. 上記第１半導体層、上記第２半導体層、および、上記半導体領域は、ＳｉＣ、ＧａＮ、ダイヤモンド、ＺｎＯ、または、ＡｌＧａＮから構成されており、
上記追加の領域は、上記導電体からなり、
上記ダイオードは、ショットキーバリヤダイオードである、請求項１に記載の半導体装置。 The first semiconductor layer, the second semiconductor layer, and the semiconductor region are composed of SiC, GaN, diamond, ZnO, or AlGaN,
The additional region is made of the conductor,
The semiconductor device according to claim 1, wherein the diode is a Schottky barrier diode. 上記導電体は、上記トレンチの底面から上記トレンチの側面にわたって接している、請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor is in contact with a side surface of the trench from a bottom surface of the trench. 上記追加の領域と上記ソース電極とを導通させる導電部をさらに備え、
この導電部は、上記トレンチの開口部から、上記トレンチの深さ方向に沿って延びており、かつ、上記ゲート電極を貫通している、請求項１ないし３のいずれかに記載の半導体装置。 A conductive portion for electrically connecting the additional region and the source electrode;
4. The semiconductor device according to claim 1, wherein the conductive portion extends from the opening of the trench along the depth direction of the trench and penetrates the gate electrode. 5.
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