JPH057002A - Insulated gate type transistor - Google Patents
Insulated gate type transistorInfo
- Publication number
- JPH057002A JPH057002A JP3156370A JP15637091A JPH057002A JP H057002 A JPH057002 A JP H057002A JP 3156370 A JP3156370 A JP 3156370A JP 15637091 A JP15637091 A JP 15637091A JP H057002 A JPH057002 A JP H057002A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- trench
- insulating film
- semiconductor
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims abstract description 295
- 239000011229 interlayer Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims description 269
- 238000009413 insulation Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 68
- 230000015556 catabolic process Effects 0.000 abstract description 41
- 230000003071 parasitic effect Effects 0.000 abstract description 31
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000006378 damage Effects 0.000 abstract 2
- 230000005684 electric field Effects 0.000 description 14
- 239000008186 active pharmaceutical agent Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
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- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、絶縁ゲート型トラン
ジスタに関し、さらに詳しくは、トレンチ絶縁効果型ト
ランジスタにおける特性向上のための改良構造に係るも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor, and more particularly to an improved structure for improving the characteristics of a trench insulation effect transistor.
【０００２】[0002]
【従来の技術】一般に、絶縁ゲート型トランジスタのう
ち，シリコン層の表面に形成された凹部（いわゆる，ト
レンチ凹部）の内側壁面に対して、ゲート電極を設けた
構成のものを、通常，ＵＭＯＳと称しており、このＵＭ
ＯＳは、多数のユニットセルが並列された構造を有して
いる。2. Description of the Related Art Generally, among insulated gate transistors, one having a gate electrode provided on the inner wall surface of a recess (so-called trench recess) formed in the surface of a silicon layer is generally called UMOS. I'm calling this UM
The OS has a structure in which many unit cells are arranged in parallel.
【０００３】図１１には、従来の一例によるこの種のＵ
ＭＯＳ構造をもつ絶縁ゲート型トランジスタの概要構成
を模式的に示してある。この従来例は、３個のユニット
セルを並列配置させた場合である。FIG. 11 shows a U of this kind according to a conventional example.
1 schematically shows a schematic structure of an insulated gate transistor having a MOS structure. In this conventional example, three unit cells are arranged in parallel.
【０００４】すなわち、図１１に示す装置構成におい
て、従来例によるＵＭＯＳ構造の絶縁ゲート型トランジ
スタは、第１の半導体層としてのn+型ドレイン層１と、
当該n+型ドレイン層１の主面上に形成された第２の半導
体層としてのn-型ドレイン層２と、第２の半導体層とし
てのn-型ドレイン層２の表面上に p型の不純物を拡散し
て形成された p型ベース層３とを有しており、かつ当該
p型ベース層３の表面上からは、所定のパターンに従い
選択的にシリコンをエッチングして、n-型ドレイン層２
に達するトレンチ凹部（以下，トレンチと呼ぶ）４を掘
り込んである。That is, in the device configuration shown in FIG. 11, an insulated gate transistor having a UMOS structure according to a conventional example has an n + type drain layer 1 as a first semiconductor layer,
The n + -type drain layer 1 of n as a second semiconductor layer formed on the main surface - -type drain layer 2, n as the second semiconductor layer - the p-type on the type drain layer 2 of the surface And a p-type base layer 3 formed by diffusing impurities, and
From the surface of the p-type base layer 3, silicon is selectively etched according to a predetermined pattern to form the n − -type drain layer 2
A trench recess 4 (hereinafter, referred to as a trench) 4 reaching the above is dug.
【０００５】そして、前記 p型ベース層３のトレンチ４
に接する表面部には、n+型ソース層５を選択的に形成さ
せると共に、当該トレンチ４の内側壁面間にあって、底
部４ａの位置までゲート絶縁膜６を介してゲート電極７
を設けることにより、トレンチ４の各側壁面側での p型
ベース層３の表面がチャネル領域８となる。Then, the trench 4 of the p-type base layer 3 is formed.
The n + type source layer 5 is selectively formed on the surface portion in contact with the gate electrode 7 between the inner wall surfaces of the trench 4 and the bottom portion 4a via the gate insulating film 6.
By providing, the surface of the p-type base layer 3 on each side wall surface side of the trench 4 becomes the channel region 8.
【０００６】また、各ユニットセル間に共通して、前記
p型ベース層３の表面とn+型ソース層５の表面とを短絡
するようにソース電極９を形成させ、かつ当該ソース電
極９と前記ゲート電極７間を層間絶縁膜１０によって絶
縁させてあり、さらに、前記n+型ドレイン層１の裏面に
ドレイン電極１１を設けてある。なお、こゝでは図示省
略したが、このＵＭＯＳ構造の場合、通常，前記トレン
チ４がストライプ状に形成されており、これらの各トレ
ンチ４内でのゲート電極７の相互は、ストライプの端部
で短絡されている。Further, in common between the unit cells,
A source electrode 9 is formed so as to short-circuit the surface of the p-type base layer 3 and the surface of the n + -type source layer 5, and the source electrode 9 and the gate electrode 7 are insulated by an interlayer insulating film 10. Further, a drain electrode 11 is provided on the back surface of the n + type drain layer 1. Although not shown here, in the case of this UMOS structure, the trenches 4 are usually formed in a stripe shape, and the gate electrodes 7 in each of these trenches 4 are located at the ends of the stripes. It is short-circuited.
【０００７】続いて、上記従来例装置の動作について述
べる。Next, the operation of the above conventional device will be described.
【０００８】上記構成において、ドレイン電極１１とソ
ース電極９間に所定のドレイン電圧ＶDSを印加し、かつ
ゲート電極７とソース電極９間にゲート電圧ＶGSを印加
すると、チャネル領域８が n型に反転してチャネルを形
成し、このチャネルを通してドレイン電極１１とソース
電極９との間にドレイン電流ＩD が流れ、このドレイン
電流ＩD はゲート電圧ＶGSによって制御される。In the above structure, when a predetermined drain voltage V DS is applied between the drain electrode 11 and the source electrode 9 and a gate voltage V GS is applied between the gate electrode 7 and the source electrode 9, the channel region 8 becomes n-type. To form a channel, a drain current I D flows between the drain electrode 11 and the source electrode 9 through the channel, and the drain current I D is controlled by the gate voltage V GS .
【０００９】また、このＵＭＯＳに印加できるドレイン
電圧ＶDS（逆電圧）は、 p型ベース層３とn-型ドレイン
層２の降伏電圧によって制限される。そして、一般に逆
電圧は、n-型ドレイン層２の不純物濃度，厚さと、 p型
ベース層３の形状とによって決定される。The drain voltage V DS (reverse voltage) that can be applied to this UMOS is limited by the breakdown voltage of the p-type base layer 3 and the n − -type drain layer 2. The reverse voltage is generally determined by the impurity concentration and thickness of the n − type drain layer 2 and the shape of the p type base layer 3.
【００１０】次に、図１２には、このＵＭＯＳにドレイ
ン電圧ＶDSを印加したときの空乏層の延びを示してあ
る。Next, FIG. 12 shows the extension of the depletion layer when the drain voltage V DS is applied to this UMOS.
【００１１】前記したように、ドレイン電極１１とソー
ス電極９間にドレイン電圧ＶDSを印加すると、 p型ベー
ス層３から空乏層が延び始め、やがて、各 p型ベース層
３から延びる空乏層がつながる。このとき，空乏層は、
トレンチ４のコーナー部４ｂにおいて不連続になり易
く、当該コーナー部４ｂに電界集中を生ずる。そして、
一般にpn接合における降伏電圧は、当該pn接合表面の電
界強度によって決まるため、このように電界集中を生ず
ることにより、pn接合の降伏電圧が低下する。As described above, when the drain voltage V DS is applied between the drain electrode 11 and the source electrode 9, the depletion layer starts to extend from the p-type base layer 3, and eventually the depletion layer extending from each p-type base layer 3 is formed. Connect At this time, the depletion layer is
Discontinuity easily occurs at the corner portion 4b of the trench 4, and electric field concentration occurs at the corner portion 4b. And
Generally, the breakdown voltage of the pn junction is determined by the electric field strength on the surface of the pn junction, and thus the concentration of the electric field causes the breakdown voltage of the pn junction to decrease.
【００１２】一方、前記図１１に示す構成では、n+型ソ
ース層５， p型ベース層３，およびn-型ドレイン層２に
よって形成される寄生トランジスタが存在する。こゝ
で、一般にＵＭＯＳの等価回路は、図１３(a) のように
表わされるが、実質的には、図１３(b) のようになる。
同図において、Ｒa は p型ベース層３の縦方向の抵抗で
ある。そして、ＵＭＯＳが降伏した場合、そのときの降
伏電流Ｊc は、寄生トランジスタのベース電流となり、
この降伏電流Ｊc が、当該寄生トランジスタをオンさせ
るベース電流（ｉR ＝0.6 を越える値）以上になると、
この寄生トランジスタを制御できなくなるために、素子
破壊をきたすことになる。On the other hand, in the structure shown in FIG. 11, there is a parasitic transistor formed by the n + type source layer 5, the p type base layer 3, and the n − type drain layer 2. Here, the UMOS equivalent circuit is generally represented as shown in FIG. 13 (a), but substantially becomes as shown in FIG. 13 (b).
In the figure, Ra is the vertical resistance of the p-type base layer 3. When the UMOS breaks down, the breakdown current Jc at that time becomes the base current of the parasitic transistor,
When this breakdown current Jc becomes the base current (value exceeding i R = 0.6) for turning on the parasitic transistor,
Since this parasitic transistor cannot be controlled, the device will be destroyed.
【００１３】さらに、 p型ベース層３，およびn-型ドレ
イン層２によって形成されるダイオードが順方向に通電
されていて、急激に逆方向電圧を加える（モータ制御な
どにおいてよく発生する）と、当該ダイオードにリカバ
リー電流が流れ、これが寄生トランジスタのベース電流
となって、同様に素子破壊をきたすことになる。Furthermore, when the diode formed by the p-type base layer 3 and the n - type drain layer 2 is energized in the forward direction and a reverse voltage is suddenly applied (which often occurs in motor control, etc.), A recovery current flows through the diode, and this becomes a base current of the parasitic transistor, which also causes element breakdown.
【００１４】[0014]
【発明が解決しようとする課題】上記のように、従来の
トレンチ構造によるＵＭＯＳでは、トレンチのコーナー
部に電界集中が発生するために、このようなトレンチ構
造をもたないＵＭＯＳに比較するとき、低い電圧で p型
ベース層３，およびn-型ドレイン層２が降伏したり、寄
生トランジスタのベース電流を制御できずに、素子破壊
を生ずるという問題点があった。As described above, in the conventional UMOS having the trench structure, electric field concentration occurs at the corners of the trench. Therefore, when compared to the UMOS having no such trench structure, There are problems that the p-type base layer 3 and the n − -type drain layer 2 break down at a low voltage, or the base current of the parasitic transistor cannot be controlled, resulting in device breakdown.
【００１５】この発明は、このような従来の問題点を解
消するためになされたもので、その目的とするところ
は、ＵＭＯＳにおいて、トレンチ構造の改良により、降
伏電圧に対する耐圧の低下を防止すると共に、寄生トラ
ンジスタによる素子破壊を生じ難くした，この種の絶縁
ゲート型トランジスタを提供することである。The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to prevent the breakdown voltage against breakdown voltage from being lowered by improving the trench structure in the UMOS. It is an object of the present invention to provide an insulated gate transistor of this kind in which element breakdown due to a parasitic transistor is hard to occur.
【００１６】[0016]
【課題を解決するための手段】前記目的を達成するため
に、次のように構成したものである。[Means for Solving the Problems] In order to achieve the above object, the present invention is configured as follows.
【００１７】この発明の第１の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成させた第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記第２の半導体層の各トレ
ンチ凹部に接する表面部に選択的に形成させた第１導電
型の第１の半導体領域と、前記各トレンチ凹部内の底部
に選択的に形成させた第２導電型の第２の半導体領域
と、前記各トレンチ凹部内の両内側壁面に対して、それ
ぞれにゲート絶縁膜を介して接し、かつ層間絶縁膜によ
り被覆させて、前記第２の半導体領域の端部に重なるよ
うに形成させた個々の各ゲート電極と、前記第２の半導
体層，第１の半導体領域，および第２の半導体領域の相
互間を短絡して形成させたソース電極と、前記第１の半
導体層の裏面側対応に形成させたドレイン電極とを、少
なくとも備えることを特徴とするものである。An insulated gate transistor according to a first aspect of the present invention is a first conductive type first semiconductor layer and a second conductive type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer and a first conductivity type first recess that is selectively formed on a surface portion that contacts each trench recess of the second semiconductor layer. No. 1 semiconductor region, a second semiconductor region of the second conductivity type selectively formed at the bottom of each trench recess, and both inner wall surfaces of each trench recess. Individual gate electrodes formed so as to be in contact with each other and covered with an interlayer insulating film so as to overlap with an end portion of the second semiconductor region, the second semiconductor layer, the first semiconductor region, And a source electrode formed by short-circuiting the second semiconductor region to each other and a drain electrode formed corresponding to the back surface side of the first semiconductor layer.
【００１８】この発明の第２の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成させた第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記第２の半導体層の各トレ
ンチ凹部に接する表面部に選択的に形成させた第１導電
型の第１の半導体領域と、前記各トレンチ凹部内の両内
側壁面に対して、それぞれにゲート絶縁膜を介して接
し、かつ層間絶縁膜により被覆して形成させた個々の各
ゲート電極と、前記各ゲート電極を被覆する層間絶縁膜
間でのトレンチ凹部内の底部に設けたショットキーダイ
オードと、前記第２の半導体層，第１の半導体領域，お
よびショットキーダイオードの相互間を短絡して形成さ
せたソース電極と、前記第１の半導体層の裏面側対応に
形成させたドレイン電極とを、少なくとも備えることを
特徴とするものである。An insulated gate transistor according to a second aspect of the present invention is a first conductive type first semiconductor layer and a second conductive type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer and a first conductivity type first recess that is selectively formed on a surface portion that contacts each trench recess of the second semiconductor layer. 1 semiconductor region and each of the inner wall surfaces in each of the trench recesses are in contact with each other via a gate insulating film, and each gate electrode formed by being covered with an interlayer insulating film, and each of the gates. The Schottky diode provided at the bottom of the trench recess between the interlayer insulating films covering the electrodes, and the second semiconductor layer, the first semiconductor region, and the Schottky diode are short-circuited to each other. At least a source electrode and a drain electrode formed on the back surface side of the first semiconductor layer are provided.
【００１９】この発明の第３の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成させた第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記各トレンチ凹部間での第
２の半導体層上に形成させた第１導電型の第３の半導体
領域と、前記各トレンチ凹部内の底部に選択的に形成さ
せた第２導電型の第２の半導体領域と、前記各トレンチ
凹部内の両内側壁面に対して、それぞれにゲート絶縁膜
を介して接し、かつ層間絶縁膜により被覆させて、前記
第２の半導体領域の端部に重なるように形成させた個々
の各ゲート電極と、前記第３の半導体領域，および第２
の半導体領域の相互間を短絡して形成させたソース電極
と、前記第１の半導体層の裏面側対応に形成させたドレ
イン電極とを、少なくとも備えることを特徴とするもの
である。An insulated gate transistor according to a third aspect of the present invention is a first conductive type first semiconductor layer, and a second conductive type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer, and a third semiconductor region of the first conductivity type formed on the second semiconductor layer between the trench recesses. A second semiconductor region of the second conductivity type selectively formed at the bottom of each of the trench recesses, and both inner wall surfaces of each of the trench recesses are in contact with each other via a gate insulating film. And each gate electrode formed so as to be covered with an interlayer insulating film so as to overlap with an end of the second semiconductor region, the third semiconductor region, and the second semiconductor region.
And a drain electrode formed corresponding to the back surface side of the first semiconductor layer.
【００２０】この発明の第４の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成させた第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記各トレンチ凹部間での第
２の半導体層上に形成させた第１導電型の第３の半導体
領域と、前記各トレンチ凹部内の両内側壁面に対して、
それぞれにゲート絶縁膜を介して接し、かつ層間絶縁膜
により被覆して形成させた個々の各ゲート電極と、前記
各ゲート電極を被覆する層間絶縁膜間でのトレンチ凹部
内の底部に設けたショットキーダイオードと、前記第３
の半導体領域，およびショットキーダイオードの相互間
を短絡して形成させたソース電極と、前記第１の半導体
層の裏面側対応に形成させたドレイン電極とを、少なく
とも備えることを特徴とするものである。An insulated gate transistor according to a fourth aspect of the present invention is a first conductive type first semiconductor layer and a second conductive type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer, and a third semiconductor region of the first conductivity type formed on the second semiconductor layer between the trench recesses. With respect to both inner wall surfaces in each of the trench recesses,
A shot provided at the bottom of the trench recess between each gate electrode formed in contact with each other through the gate insulating film and covered with the interlayer insulating film and the interlayer insulating film covering each gate electrode. Key diode, and the third
A semiconductor electrode and a source electrode formed by short-circuiting the Schottky diode with each other, and a drain electrode formed corresponding to the back surface side of the first semiconductor layer. is there.
【００２１】この発明の第５の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成された第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込むと
共に、掘り込んだ底部に選択的に第２の半導体領域を形
成させた複数の各トレンチ凹部と、前記第２の半導体層
の各トレンチ凹部に接する表面部に選択的に形成された
第１導電型の第１の半導体領域と、前記各トレンチ凹部
内の両内側壁面に対して、それぞれにゲート絶縁膜を介
して接し、かつ上部，下部を層間絶縁膜により被覆して
形成させたゲート電極と、前記第２の半導体層，および
第１の半導体領域の相互間を短絡して形成させたソース
電極と、前記第１の半導体層の裏面側対応に形成させた
ドレイン電極とを、少なくとも備えることを特徴とする
ものである。An insulated gate transistor according to a fifth aspect of the present invention is a first-conductivity-type first semiconductor layer and a second-conductivity-type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses in which a second semiconductor region is selectively formed in the dug bottom while selectively digging into the first semiconductor layer, and trenches in the second semiconductor layer A first semiconductor region of the first conductivity type selectively formed on a surface portion in contact with the recess and both inner wall surfaces in each of the recesses of the trench are in contact with each other through a gate insulating film, and an upper portion, A gate electrode formed by covering the lower portion with an interlayer insulating film, a source electrode formed by short-circuiting the second semiconductor layer and the first semiconductor region, and a first semiconductor layer At least a drain electrode formed corresponding to the back surface side is provided.
【００２２】この発明の第６の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成された第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層に達して選択的に掘り込まれた複数
の各トレンチ凹部と、前記第２の半導体層の各トレンチ
凹部に接する表面部に選択的に形成された第１導電型の
第１の半導体領域と、前記隣接する一方のトレンチ凹部
内の両内側壁面に対して、それぞれにゲート絶縁膜を介
して接し、かつ上部，下部を層間絶縁膜により被覆して
形成させたゲート電極，および他方のトレンチ凹部内の
底部に第２導電型の第２の半導体領域を選択的に形成さ
せると共に、当該他方のトレンチ凹部内の両内側壁面に
対して、それぞれにゲート絶縁膜を介して接し、かつ層
間絶縁膜により被覆させて、前記第２の半導体領域の端
部に重なるように形成させた個々の各ゲート電極と、前
記第２の半導体層，第１の半導体領域，および第２の半
導体領域の相互間を短絡して形成させたソース電極と、
前記第１の半導体層の裏面側対応に形成させたドレイン
電極とを、少なくとも備えることを特徴とするものであ
る。An insulated gate transistor according to a sixth aspect of the present invention is a first-conductivity-type first semiconductor layer and a second-conductivity-type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that reach the first semiconductor layer and are selectively dug therein, and a first conductivity type first recess that is selectively formed on a surface portion that contacts the trench recesses of the second semiconductor layer. A gate electrode formed in contact with the semiconductor region of No. 1 and both inner wall surfaces in the adjacent one of the trench recesses via a gate insulating film and by covering the upper and lower portions with an interlayer insulating film; And a second semiconductor region of the second conductivity type is selectively formed on the bottom of the other trench recess, and both inner wall surfaces of the other trench recess are in contact with each other via a gate insulating film. And each gate electrode formed by being covered with an interlayer insulating film so as to overlap with an end portion of the second semiconductor region, the second semiconductor layer, the first semiconductor region, and the second semiconductor layer. Between semiconductor regions A source electrode is formed by a short circuit,
At least a drain electrode formed corresponding to the back surface side of the first semiconductor layer is provided.
【００２３】この発明の第７の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成された第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層に達して選択的に掘り込まれた複数
の各トレンチ凹部と、前記第２の半導体層の各トレンチ
凹部に接する表面部に選択的に形成された第１導電型の
第１の半導体領域と、前記隣接する一方のトレンチ凹部
内の両内側壁面に対して、それぞれにゲート絶縁膜を介
して接し、かつ上部，下部を層間絶縁膜により被覆して
形成させたゲート電極，および他方のトレンチ凹部内の
両内側壁面に対して、それぞれにゲート絶縁膜を介して
接し、かつ層間絶縁膜により被覆して形成させた個々の
各ゲート電極と、前記他方のトレンチ凹部内の各ゲート
電極を被覆する層間絶縁膜間でのトレンチ凹部内の底部
に設けたショットキーダイオードと、前記第２の半導体
層，第１の半導体領域，およびショットキーダイオード
の相互間を短絡して形成させたソース電極と、前記第１
の半導体層の裏面側対応に形成させたドレイン電極と
を、少なくとも備えることを特徴とするものである。An insulated gate transistor according to a seventh aspect of the present invention is a first-conductivity-type first semiconductor layer and a second-conductivity-type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that reach the first semiconductor layer and are selectively dug therein, and a first conductivity type first recess that is selectively formed on a surface portion that contacts the trench recesses of the second semiconductor layer. A gate electrode formed in contact with the semiconductor region of No. 1 and both inner wall surfaces in the adjacent one of the trench recesses via a gate insulating film and by covering the upper and lower portions with an interlayer insulating film; And each inner wall surface in the other trench recess and each gate electrode formed in contact with each other via the gate insulating film and covered with the interlayer insulating film, and each in the other trench recess. The Schottky diode provided at the bottom of the trench recess between the interlayer insulating films covering the gate electrode is short-circuited with the second semiconductor layer, the first semiconductor region, and the Schottky diode. A source electrode is formed, the first
And a drain electrode formed corresponding to the back surface side of the semiconductor layer.
【００２４】この発明の第８の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成された第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記各トレンチ凹部間での第
２の半導体層上に形成させた第１導電型の第３の半導体
領域と、前記隣接する一方のトレンチ凹部内の両内側壁
面に対して、それぞれにゲート絶縁膜を介して接し、か
つ上部，下部を層間絶縁膜により被覆して形成させたゲ
ート電極，および他方のトレンチ凹部内の底部に第２導
電型の第２の半導体領域を選択的に形成させると共に、
当該他方のトレンチ凹部内の両内側壁面に対して、それ
ぞれにゲート絶縁膜を介して接し、かつ層間絶縁膜によ
り被覆して第２の半導体領域の端部に重なるように形成
させた個々の各ゲート電極と、前記第３の半導体領域，
および第２の半導体領域の相互間を短絡して形成させた
ソース電極と、前記第１の半導体層の裏面側対応に形成
させたドレイン電極とを、少なくとも備えることを特徴
とするものである。An insulated gate transistor according to an eighth aspect of the present invention is a first-conductivity-type first semiconductor layer, and a second-conductivity-type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer, and a third semiconductor region of the first conductivity type formed on the second semiconductor layer between the trench recesses. A gate electrode formed in such a manner that it is in contact with both inner wall surfaces in the adjacent one of the trench recesses via a gate insulating film, and the upper and lower portions are covered with an interlayer insulating film, and the other trench. A second semiconductor region of the second conductivity type is selectively formed on the bottom of the recess, and
Each of the inner wall surfaces in the other trench recess is in contact with each other through the gate insulating film and is covered with the interlayer insulating film to be formed so as to overlap the end portion of the second semiconductor region. A gate electrode, the third semiconductor region,
And a source electrode formed by short-circuiting the second semiconductor region to each other and a drain electrode formed corresponding to the back surface side of the first semiconductor layer.
【００２５】この発明の第９の発明に係る絶縁ゲート型
トランジスタは、第１導電型の第１の半導体層，および
当該第１の半導体層の表面上に形成された第２導電型の
第２の半導体層と、前記第２の半導体層の表面上から、
前記第１の半導体層内に達するまで選択的に掘り込んだ
複数の各トレンチ凹部と、前記各トレンチ凹部間での第
２の半導体層上に形成させた第１導電型の第３の半導体
領域と、前記隣接する一方のトレンチ凹部内の両内側壁
面に対して、それぞれにゲート絶縁膜を介して接し、か
つ上部，下部を層間絶縁膜により被覆して形成させたゲ
ート電極，および他方のトレンチ凹部内の両内側壁面に
対して、それぞれにゲート絶縁膜を介して接し、かつ層
間絶縁膜により被覆して形成させた個々の各ゲート電極
と、前記他方のトレンチ凹部内の各ゲート電極を被覆す
る層間絶縁膜間でのトレンチ凹部内の底部に設けたショ
ットキーダイオードと、前記第３の半導体領域，および
ショットキーダイオードの相互間を短絡して形成させた
ソース電極と、前記第１の半導体層の裏面側対応に形成
させたドレイン電極とを、少なくとも備えることを特徴
とするものである。An insulated gate transistor according to a ninth aspect of the present invention is a first-conductivity-type first semiconductor layer and a second-conductivity-type second semiconductor layer formed on the surface of the first semiconductor layer. From the surface of the semiconductor layer and the second semiconductor layer,
A plurality of trench recesses that are selectively dug to reach the inside of the first semiconductor layer, and a third semiconductor region of the first conductivity type formed on the second semiconductor layer between the trench recesses. A gate electrode formed in such a manner that it is in contact with both inner wall surfaces in the adjacent one of the trench recesses via a gate insulating film, and the upper and lower portions are covered with an interlayer insulating film, and the other trench. Each gate electrode formed by being in contact with both inner wall surfaces in the recess via the gate insulating film and being covered with the interlayer insulating film and each gate electrode in the other trench recess A Schottky diode provided at the bottom of the trench recess between the interlayer insulating films, and a source electrode formed by short-circuiting the third semiconductor region and the Schottky diode. And a drain electrode were formed on the back side corresponding to the first semiconductor layer, and is characterized in that at least provided.
【００２６】[0026]
【作用】この発明の各発明における絶縁ゲート型トラン
ジスタでは、コレクタ電流が、ドレイン電極からトレン
チ凹部の底部に形成された第２導電型の第２の半導体領
域，またはショットキーダイオードを通り、当該トレン
チ凹部内のソース電極を経て表面部のソース電極に流
れ、また一方で、ドレイン電極から第１導電型の第１の
半導体層を通り、かつ第２導電型の第２の半導体層を経
て表面部のソース電極に流れる。In the insulated gate type transistor according to each aspect of the present invention, the collector current passes from the drain electrode to the second conductivity type second semiconductor region formed at the bottom of the trench recess or the Schottky diode, and the trench It flows through the source electrode in the concave portion to the source electrode on the surface portion, and on the other hand, it passes from the drain electrode through the first semiconductor layer of the first conductivity type and through the second semiconductor layer of the second conductivity type to the surface portion. Flows to the source electrode of.
【００２７】[0027]
【実施例】以下，この発明に係る絶縁ゲート型トランジ
スタの各別の実施例につき、図１ないし図１０を参照し
て詳細に説明する。なお、これらの図１ないし図１０に
示す各別の実施例構成において、上記図１１ないし図１
３に示す従来例構成と同一符号は、同一または相当部分
を表わしている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, different embodiments of the insulated gate transistor according to the present invention will be described in detail with reference to FIGS. It should be noted that in each of the configurations of the other embodiments shown in FIGS.
The same reference numerals as those in the configuration of the conventional example shown in 3 represent the same or corresponding portions.
【００２８】まず、図１はこの発明の第１の発明の一実
施例（説明の便宜上、以下，第１実施例と呼ぶ、他の発
明の場合も同様である）を適用したＵＭＯＳ構造をもつ
絶縁ゲート型トランジスタの概要構成を模式的に示す断
面図であり、また、図２は同上第１実施例構成の要部を
破断して模式的に示す平面図である。First, FIG. 1 has a UMOS structure to which an embodiment of the first invention of the present invention (for convenience of explanation, hereinafter referred to as the first embodiment, the same applies to other inventions). FIG. 3 is a cross-sectional view schematically showing a schematic structure of an insulated gate transistor, and FIG. 2 is a plan view schematically showing a main part of the same structure as the first embodiment of the present invention in a broken manner.
【００２９】すなわち、これらの図１，図２に示す第１
実施例装置の構成において、このＵＭＯＳ構造の絶縁ゲ
ート型トランジスタは、上記の従来例構成の場合と同様
に、n+型ドレイン層１と、当該n+型ドレイン層１の主面
上に形成された第１の半導体層としてのn-型ドレイン層
２と、当該n-型ドレイン層２の表面上に p型の不純物を
拡散して形成された第２の半導体層としての p型ベース
層３とを有しており、かつ前記 p型ベース層３の表面上
からは、所定のパターン，こゝでは、各ユニットセルを
形成させるべくストライプ状のパターンに従い、選択的
に該当面のシリコンをエッチングして、n-型ドレイン層
２に達する複数条の各トレンチ４をそれぞれに掘り込む
と共に、前記 p型ベース層３の各トレンチ４に接する表
面部にあって、第１の半導体領域としてのn+型ソース層
５をそれぞれ選択的に拡散形成させてある。That is, the first shown in FIGS. 1 and 2
In the configuration of Example device, an insulated gate transistor of this UMOS structure, as in the case of conventional construction described above, the n + -type drain layer 1 is formed on the main surface of the n + -type drain layer 1 n as a first semiconductor layer - -type drain layer 2, the n - -type drain layer 2 on the surface of a second semiconductor layer formed by diffusing p-type impurity p-type base layer 3 And has a predetermined pattern from the surface of the p-type base layer 3 and, in this case, selectively etches the silicon on the corresponding surface in accordance with a stripe pattern to form each unit cell. Then, a plurality of trenches 4 reaching the n − type drain layer 2 are dug into each of the trenches 4, and at the surface portion of the p type base layer 3 in contact with each trench 4, an n each selective + -type source layer 5 It is then formed by diffusion.
【００３０】また、前記各トレンチ４の底部４ａの中間
部には、第２の半導体領域としてのp型ベース領域１２
を拡散形成させた上で、当該各トレンチ４の左，右内側
壁面に接して底部４ａの位置まで、それぞれにゲート絶
縁膜６を介してゲート電極１４を形成させることによ
り、トレンチ４の各側壁面側での p型ベース層３の表面
がそれぞれにチャネル領域８となる。In the middle of the bottom 4a of each trench 4, a p-type base region 12 as a second semiconductor region is formed.
On the respective sides of the trench 4 by diffusing and forming the gate electrode 14 through the gate insulating film 6 to the position of the bottom portion 4a in contact with the left and right inner wall surfaces of the trench 4 respectively. The surface of the p-type base layer 3 on the wall surface side becomes the channel region 8 respectively.
【００３１】そして、各ユニットセル間に共通するよう
にして、前記トレンチ４における各ゲート電極１４での
表面の層間絶縁膜１０間の内部を含んで、前記p型ベー
ス層３の表面とn+型ソース層５の表面とを短絡するよう
にソース電極１３，１３ａを形成させてあり、これによ
って、これらの p型ベース層３，n+型ソース層５，およ
び p型ベース領域１２の相互が短絡される。こゝで、ソ
ース電極１３は、 p型ベース層３とn+型ソース層５との
表面間の電極部分を、ソース電極１３ａは、トレンチ４
内に対応して p型ベース領域１２の表面に接する電極部
分をそれぞれに示している。Then, in common with each unit cell, including the inside of the interlayer insulating film 10 on the surface of each gate electrode 14 in the trench 4 and the surface of the p-type base layer 3 and n +. The source electrodes 13 and 13a are formed so as to short-circuit the surface of the type source layer 5, so that the p-type base layer 3, the n + -type source layer 5, and the p-type base region 12 are mutually connected. Short circuited. Here, the source electrode 13 is the electrode portion between the surfaces of the p-type base layer 3 and the n + -type source layer 5, and the source electrode 13a is the trench 4
Corresponding to the inside, electrode portions in contact with the surface of the p-type base region 12 are shown.
【００３２】さらに、前記n+型ドレイン層１の裏面に
は、ドレイン電極１１を設けてあり、かつ各ゲート電極
１４については、図２によって明らかなように、それぞ
れの端面が並列に共通電極１５によって短絡されると共
に、当該共通電極１５に接続されるゲートパッド１６を
介して外部へ配線される。Further, a drain electrode 11 is provided on the back surface of the n + type drain layer 1, and each gate electrode 14 has its end faces arranged in parallel with each other as shown in FIG. Is short-circuited and is wired to the outside through the gate pad 16 connected to the common electrode 15.
【００３３】続いて、上記第１実施例装置の動作につい
て述べる。Next, the operation of the first embodiment device will be described.
【００３４】上記構成において、ドレイン電極１１とソ
ース電極１３間に所定のドレイン電圧ＶDSを印加し、か
つゲート電極１４とソース電極１３間にゲート電圧ＶGS
を印加すると、チャネル領域８が n型に反転してチャネ
ルを形成し、このチャネルを通してドレイン電極１１と
ソース電極１３との間にドレイン電流ＩD が流れ、この
ドレイン電流ＩD はゲート電圧ＶGSによって制御され
る。In the above structure, a predetermined drain voltage V DS is applied between the drain electrode 11 and the source electrode 13, and the gate voltage V GS is applied between the gate electrode 14 and the source electrode 13.
Is applied, the channel region 8 is inverted into an n-type to form a channel, and a drain current I D flows between the drain electrode 11 and the source electrode 13 through this channel, and the drain current I D becomes the gate voltage V GS. Controlled by.
【００３５】こゝで、この第１実施例による装置構成で
のＵＭＯＳにおける逆電圧について考えてみる。まず、
前記ドレイン電圧ＶDSを印加した場合の空乏層（電界強
度分布）の状態を図３に示す。Now, let us consider the reverse voltage in the UMOS in the device configuration according to the first embodiment. First,
FIG. 3 shows the state of the depletion layer (electric field strength distribution) when the drain voltage V DS is applied.
【００３６】この第１実施例による構成の場合、ドレイ
ン電極１１とソース電極１３間にドレイン電圧ＶDSが印
加されると、空乏層は、 p型ベース層３と、トレンチ４
の底部での p型ベース領域１２との双方から延び始める
ために、従来例での図１２に示したトレンチ４のコーナ
ー部４ｂにおける電界集中が、当該 p型ベース領域１２
からの空乏層の延びによって緩和されることになる。In the structure according to the first embodiment, when the drain voltage V DS is applied between the drain electrode 11 and the source electrode 13, the depletion layer becomes the p-type base layer 3 and the trench 4.
Since it starts to extend from both the p-type base region 12 at the bottom of the p-type base region 12 and the p-type base region 12 at the corner 4b of the trench 4 shown in FIG.
Will be alleviated by the extension of the depletion layer.
【００３７】従って、この第１実施例構成でのＵＭＯＳ
における逆電圧は、本来の p型ベース層３（ p型ベース
領域１２）とn-型ドレイン層２で決定される電圧に近付
くことになり、これによって従来例構造ほどは耐圧低下
を生ずることがない。Therefore, the UMOS in the configuration of the first embodiment is
Therefore, the reverse voltage at the voltage approaches the voltage determined by the original p-type base layer 3 (p-type base region 12) and the n − -type drain layer 2, which may cause a breakdown voltage lower than that of the conventional structure. Absent.
【００３８】続いて、この第１実施例構成での等価回路
を図４に示す。Next, FIG. 4 shows an equivalent circuit in the configuration of the first embodiment.
【００３９】この第１実施例構成においては、従来例の
構成に対して、トレンチ４の底部４ａでの p型ベース領
域１２によって形成されるダイオードが並列に加えられ
ており、かつ図１からも明らかなように、 p型ベース層
３よりも、当該 p型ベース領域１２の方が場合、n+型ド
レイン層１に近くなっている。In the structure of the first embodiment, the diode formed by the p-type base region 12 at the bottom 4a of the trench 4 is added in parallel to the structure of the conventional example, and also from FIG. As is apparent, the p type base region 12 is closer to the n + type drain layer 1 than the p type base layer 3 in some cases.
【００４０】そして、この場合，一般的には、降伏現象
が p型ベース領域１２で発生する筈であるが、このとき
の降伏電流Ｊc は、当該 p型ベース領域１２からソース
電極１３へ直接，流れるために、寄生トランジスタのベ
ース電流とはなり得ず、従って、こゝでは、寄生トラン
ジスタのオンによる素子破壊を防止できる。In this case, generally, the breakdown phenomenon should occur in the p-type base region 12, but the breakdown current Jc at this time is directly generated from the p-type base region 12 to the source electrode 13. Since it flows, it cannot serve as the base current of the parasitic transistor. Therefore, here, it is possible to prevent element breakdown due to the parasitic transistor being turned on.
【００４１】また、この第１実施例構成でのダイオード
のリカバリーについて考えると、このリカバリー電流
は、前記図４に示す寄生トランジスタ（ＴＲ）と、トレ
ンチ４の底部４ａでの p型ベース領域１２によるダイオ
ード（ＤＩ）とに分割されることになり、これを従来例
構成の場合に比較するとき、当該寄生トランジスタ（Ｔ
Ｒ）に流れるリカバリー電流が少なくなるために、こゝ
でも、寄生トランジスタ（ＴＲ）のオンによる素子破壊
を防止できる。Considering the recovery of the diode in the structure of the first embodiment, this recovery current is caused by the parasitic transistor (TR) shown in FIG. 4 and the p-type base region 12 at the bottom 4a of the trench 4. It will be divided into a diode (DI), and when comparing this with the conventional configuration, the parasitic transistor (T
Since the recovery current flowing in R) is reduced, even in this case, it is possible to prevent the element breakdown due to the turning on of the parasitic transistor (TR).
【００４２】さらに、この第１実施例構成において、図
１でのトレンチ４の底部４ａと p型ベース領域１２との
関係寸法ｌと、トレンチ４の深さｈとの関係について述
べると、次の通りである。Further, in the structure of the first embodiment, the relationship between the relational dimension 1 between the bottom 4a of the trench 4 and the p-type base region 12 in FIG. 1 and the depth h of the trench 4 will be described below. On the street.
【００４３】まず、前記深さｈについては、こゝでのＵ
ＭＯＳの装置構成上，可能な限り小さい方が、耐圧を高
くでき、かつオン抵抗が小さくなる。但し、少なくとも
ゲート電極１４の縦方向の幅以内でなければならない。
なお、この場合，オン抵抗とは、このＵＭＯＳに電圧が
印加されてオンし、ドレイン電極１１からソース電極１
３にコレクタ電流が流れ始めるときのpn接合間の抵抗で
ある。First, regarding the depth h, U at this point
Due to the MOS device structure, the smaller the device structure is, the higher the breakdown voltage can be and the smaller the on-resistance is. However, it must be at least within the vertical width of the gate electrode 14.
In this case, the on-resistance means that a voltage is applied to this UMOS to turn it on, and the drain electrode 11 to the source electrode 1 are turned on.
3 is the resistance between the pn junctions when the collector current starts to flow.
【００４４】また、前記寸法ｌについては、可能な限り
小さい方が、耐圧を高くし得るが、逆にオン抵抗が増加
する。この関係を図５に示す。つまり、当該図５におい
て、例えば、ｌ方向の寸法がｌ1 のとき、耐圧値は、Ｖ
1 ボルト，オン抵抗値は、破線で結ばれる点のＲ1 オー
ムである。従って、この図５からも判るように、耐圧
値，およびオン抵抗値の双方を満足させる最適値は、ｌ
寸法がｌ2 のとき，つまり、ｌ2 ＝ｌ／２のときであ
る。Further, with respect to the dimension l, if the dimension l is as small as possible, the breakdown voltage can be increased, but conversely the on-resistance increases. This relationship is shown in FIG. That is, in FIG. 5, for example, when the dimension in the l direction is l 1 , the withstand voltage value is V
The 1 volt, on-resistance value is R 1 ohm at the point connected by the broken line. Therefore, as can be seen from FIG. 5, the optimum value that satisfies both the withstand voltage value and the on-resistance value is l
When the dimension is l 2 , that is, when l 2 = l / 2.
【００４５】次に、図６はこの発明の第２の発明を適用
した第２実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 6 is a sectional view schematically showing a schematic structure of an insulated gate type transistor having a UMOS structure according to a second embodiment to which the second invention of the present invention is applied.
【００４６】この第２実施例装置は、前記第１実施例装
置の構成において、トレンチ４の底部４ａに形成される
p型ベース領域１２に代え、ショットキーダイオード１
７を形成させたものであり、他の各部の構成は全く同一
である。The device of the second embodiment is formed on the bottom portion 4a of the trench 4 in the structure of the device of the first embodiment.
Instead of the p-type base region 12, the Schottky diode 1
7 is formed, and the configurations of the other parts are exactly the same.
【００４７】この第２実施例構成でのＵＭＯＳにおける
逆電圧は、この場合にあっても、空乏層が、ショットキ
ーダイオード１７からも延びるために、従来例でのトレ
ンチ４のコーナー部４ｂにおける電界集中が起り難くな
る。但し、当該ショットキーダイオード１７によって逆
電圧が決定されることになるので、前記第１実施例構成
の場合に比較して耐圧が低くなる。また、この場合に
も、降伏現象が当該ショットキーダイオード１７におい
て起るので、降伏電流Ｊc による素子破壊を防止でき
る。さらに、ダイオードのリカバリー電流は、このショ
ットキーダイオード１７の場合、通常のpn接合ダイオー
ドに比較して格段に少なく、このために、当該リカバリ
ー電流による素子破壊は、第１実施例の場合よりも一
層，起り難くなる。Even in this case, the reverse voltage in the UMOS in the configuration of the second embodiment is the electric field in the corner portion 4b of the trench 4 in the conventional example because the depletion layer also extends from the Schottky diode 17. Concentration is hard to occur. However, since the reverse voltage is determined by the Schottky diode 17, the breakdown voltage is lower than that in the case of the configuration of the first embodiment. Also in this case, since the breakdown phenomenon occurs in the Schottky diode 17, the device breakdown due to the breakdown current Jc can be prevented. Further, the recovery current of the diode is much smaller in the case of the Schottky diode 17 than in the case of the normal pn junction diode, and therefore the element breakdown due to the recovery current is more than in the case of the first embodiment. ， It becomes difficult to occur.
【００４８】次に、図７はこの発明の第３の発明を適用
した第３実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 7 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a third embodiment to which the third invention of the present invention is applied.
【００４９】前記第１実施例装置の場合、 p型ベース層
３の表面部に選択的にn+型ソース層５が形成され、かつ
これらの p型ベース層３，およびn+型ソース層５の各表
面部をソース電極１３に短絡させているが、この第３実
施例装置では、これに代えてp型ベース層１８の表面部
にn+型ソース層１９を形成させると共に、当該 p型ベー
ス層１８については、n+型ソース層１９を介してソース
電極１３に短絡させるようにしたものであり、他の各部
の構成は全く同一である。In the case of the device of the first embodiment, the n + type source layer 5 is selectively formed on the surface of the p type base layer 3, and the p type base layer 3 and the n + type source layer 5 are formed. The respective surface portions of the n-type source layer 19 are short-circuited to the source electrode 13, but in the device of the third embodiment, instead of this, the n + -type source layer 19 is formed on the surface portion of the p-type base layer 18 and The base layer 18 is configured to be short-circuited to the source electrode 13 via the n + type source layer 19, and the configurations of other parts are exactly the same.
【００５０】こゝで、一般的には、このような構造にし
た方が、各トレンチ４間の間隔を狭めることが可能で、
同一寸法内におけるトレンチ４の数を増加でき、かつ各
チャネル８を流れる電流が小さくなって、オン時の抵抗
を低減し得るのであるが、一方，このような構造の場合
は、チャネル８の長さが短くなって、寄生トランジスタ
が簡単にオンして了うことから、前記図１１の従来例構
造では、p型ベース層３をソース電極１３に短絡させる
必要がある。Here, in general, with such a structure, it is possible to narrow the interval between the trenches 4,
The number of trenches 4 in the same size can be increased, and the current flowing through each channel 8 can be reduced to reduce the on-state resistance. On the other hand, in the case of such a structure, the length of the channel 8 can be reduced. Becomes shorter and the parasitic transistor is easily turned on. Therefore, in the conventional structure shown in FIG. 11, it is necessary to short the p-type base layer 3 to the source electrode 13.
【００５１】しかし、図７の第３実施例構造のように、
トレンチ４の底部４ａに p型ベース領域１２を形成させ
た構造では、先に述べた如く、寄生トランジスタによる
素子破壊が極めて起り難いために、n+型ソース層１９を
介して p型ベース層１８をソース電極１３に短絡させる
ことができる。なお、この第３実施例装置においては、
第２実施例装置の場合と同様に、トレンチ４の底部４ａ
に形成される p型ベース領域１２に代えて、ショットキ
ーダイオード１７を形成させてもよく、同様な作用，効
果が得られるもので、この発明の第４の発明を構成す
る。However, as in the structure of the third embodiment of FIG.
In the structure in which the p-type base region 12 is formed on the bottom portion 4a of the trench 4, as described above, the element breakdown due to the parasitic transistor is extremely unlikely to occur, so that the p-type base layer 18 is interposed via the n + -type source layer 19. Can be short-circuited to the source electrode 13. In the device of the third embodiment,
As in the case of the device of the second embodiment, the bottom portion 4a of the trench 4 is
The Schottky diode 17 may be formed in place of the p-type base region 12 formed in 1., and the same action and effect can be obtained, which constitutes the fourth invention of the present invention.
【００５２】次に、図８はこの発明の第５の発明を適用
した第４実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 8 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a fourth embodiment to which the fifth invention of the present invention is applied.
【００５３】この第４実施例装置は、前記図１１の従来
例装置の構成において、前記図１の第１実施例による構
成，つまり、トレンチ４の底部４ａに p型ベース領域２
３を形成させたものであり、他の各部の構成は全く同一
である。こゝで、図８中，２０は前記ゲート電極７に対
応するゲート電極、２１は前記層間絶縁膜１０に対応す
る層間絶縁膜、２２は前記ソース電極９に対応するソー
ス電極である。The device of the fourth embodiment has the same structure as that of the device of the prior art shown in FIG. 11 according to the first embodiment shown in FIG. 1, that is, the p-type base region 2 is formed on the bottom 4a of the trench 4.
3 is formed, and the configurations of the other parts are exactly the same. Here, in FIG. 8, 20 is a gate electrode corresponding to the gate electrode 7, 21 is an interlayer insulating film corresponding to the interlayer insulating film 10, and 22 is a source electrode corresponding to the source electrode 9.
【００５４】そして、この第４実施例の構成でも、第１
実施例構成の場合と同様に、トレンチ４のコーナー部４
ｂでの電界集中を効果的に緩和できて、逆電圧の低下を
少なくし得るのであるが、この場合には、寄生トランジ
スタによる素子破壊を防止する点において難がある。こ
ゝでは、この発明の第６の発明を構成する。In the structure of the fourth embodiment as well, the first
As in the case of the configuration of the embodiment, the corner portion 4 of the trench 4
Although it is possible to effectively alleviate the electric field concentration at b and reduce the decrease in reverse voltage, in this case, there is a difficulty in preventing element breakdown due to a parasitic transistor. This constitutes the sixth invention of the present invention.
【００５５】次に、図９はこの発明の第６の発明を適用
した第５実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 9 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a fifth embodiment to which the sixth invention of the present invention is applied.
【００５６】この第５実施例装置は、前記図１１の従来
例の構成の一部に、前記図１の第１実施例でのトレンチ
４の底部４ａに p型ベース領域１２を形成させた構成を
取り入れたものであり、他の各部の構成は全く同一であ
る。こゝで、図９中，２４は前記ソース電極９に対応す
るソース電極である。The device of the fifth embodiment has a structure in which a p-type base region 12 is formed in the bottom portion 4a of the trench 4 in the first embodiment of FIG. 1 in a part of the structure of the conventional example of FIG. The configuration of other parts is exactly the same. Here, 24 in FIG. 9 is a source electrode corresponding to the source electrode 9.
【００５７】そして、この第５実施例の構成では、耐圧
の点に難があるが、第１実施例構成の場合と同様に、寄
生トランジスタによる素子破壊の防止が可能である。ま
た、この場合、底部４ａに p型ベース領域１２を形成し
たトレンチ４については、必ずしもゲート電極１４を形
成しなくともよい。なお、この第５実施例装置において
も、第２実施例装置の場合と同様に、トレンチ４の底部
４ａに形成される p型ベース領域１２に代えて、ショッ
トキーダイオード１７を形成させてもよいことは勿論で
あり、こゝでは、この発明の第７の発明を構成する。In the structure of the fifth embodiment, the breakdown voltage is difficult, but like the structure of the first embodiment, it is possible to prevent the element breakdown due to the parasitic transistor. In this case, the gate electrode 14 does not necessarily have to be formed in the trench 4 having the p-type base region 12 formed in the bottom portion 4a. Note that, also in the device of the fifth embodiment, the Schottky diode 17 may be formed instead of the p-type base region 12 formed in the bottom portion 4a of the trench 4 as in the device of the second embodiment. Of course, this constitutes the seventh aspect of the present invention.
【００５８】次に、図１０はこの発明の第８の発明を適
用した第６実施例によるＵＭＯＳ構造をもつ絶縁ゲート
型トランジスタの概要構成を模式的に示す断面図であ
る。Next, FIG. 10 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a sixth embodiment to which the eighth invention of the present invention is applied.
【００５９】この第６実施例装置は、前記図１１の従来
例の構成の一部に、前記図１の第１実施例でのトレンチ
４の底部４ａに p型ベース領域１２を形成させた構成，
および前記図７の第３実施例の構成をそれぞれに取り入
れたものであり、他の各部の構成は全く同一である。This sixth embodiment device has a structure in which a p-type base region 12 is formed in the bottom portion 4a of the trench 4 in the first embodiment of FIG. 1 in a part of the structure of the conventional example of FIG. ，
Further, the configuration of the third embodiment of FIG. 7 is incorporated into each, and the configurations of the other parts are exactly the same.
【００６０】そして、この第６実施例の構成では、前記
第５実施例構成の場合と同様に、耐圧の点に難がある
が、寄生トランジスタによる素子破壊の防止が可能であ
る。なお、この第６実施例装置においても、第２実施例
装置の場合と同様に、トレンチ４の底部４ａに形成され
る p型ベース領域１２に代えて、ショットキーダイオー
ド１７を形成させてもよいことは勿論であり、こゝで
は、この発明の第９の発明を構成する。In the structure of the sixth embodiment, as in the case of the structure of the fifth embodiment, the breakdown voltage is difficult, but the element breakdown due to the parasitic transistor can be prevented. Note that, also in the device of the sixth embodiment, the Schottky diode 17 may be formed instead of the p-type base region 12 formed in the bottom portion 4a of the trench 4 as in the device of the second embodiment. Of course, this constitutes the ninth aspect of the present invention.
【００６１】こゝで、前記各実施例においては、この発
明をトレンチ構造をもつＭＯＳＦＥＴに適用する場合に
ついて述べたが、他のＭＯＳゲートのトランジスタ（Ｉ
ＧＢＴ，ＭＣＴなど）にも同様に適用できるものであ
り、また、各実施例では、 nチャネルのものについて述
べたが、 pチャネルのものにも同様に適用できて、それ
ぞれに同等の作用，効果を奏し得るのである。In each of the above embodiments, the case where the present invention is applied to the MOSFET having the trench structure has been described. However, other MOS gate transistors (I
The present invention is also applicable to the GBT, MCT, etc.), and in each embodiment, the n-channel one is described. Can be played.
【００６２】[0062]
【発明の効果】以上、各実施例によって詳述したよう
に、この発明によれば、第１導電型の第１の半導体層，
および当該第１の半導体層の表面上に形成させた第２導
電型の第２の半導体層を用い、第２の半導体層の表面側
から第１の半導体層内に達するまで複数の各トレンチ凹
部を選択的に掘り込み、かつ第２の半導体層の各トレン
チ凹部に接する表面部に第１導電型の第１の半導体領域
を選択的に形成させると共に、各トレンチ凹部内の底部
に第２導電型の第２の半導体領域を選択的に形成させる
か、あるいはショットキーダイオードを形成させ、ま
た、各トレンチ凹部内の両内側壁面にゲート絶縁膜を介
して個々の各ゲート電極を形成した上で、ソース電極に
より、これらの第２の半導体層，第１の半導体領域，お
よび第２の半導体領域の相互間，あるいはこれらの第２
の半導体層，第１の半導体領域，およびショットキーダ
イオードの相互間を短絡して構成させたので、コレクタ
電流が、ドレイン電極からトレンチ凹部の底部に形成さ
れた第２導電型の第２の半導体領域，あるいはショット
キーダイオードを通って、トレンチ凹部内のソース電極
を経た後に表面部のソース電極に流れ、また一方では、
ドレイン電極から第１導電型の第１の半導体層を通り、
かつ第２導電型の第２の半導体層を経て表面部のソース
電極に流れることになり、この結果，降伏電圧に対する
素子の耐圧の低下，ならびに寄生トランジスタのオンに
よる素子の破壊などをそれぞれ良好かつ効果的に防止し
得るという優れた特長がある。As described above in detail for each embodiment, according to the present invention, the first semiconductor layer of the first conductivity type,
And using the second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, a plurality of trench recesses are formed from the surface side of the second semiconductor layer to the inside of the first semiconductor layer. And selectively forming a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer in contact with each trench recess, and at the bottom of each trench recess the second conductivity. A second semiconductor region of the mold is selectively formed or a Schottky diode is formed, and individual gate electrodes are formed on both inner wall surfaces in each trench recess via gate insulating films. A source electrode, between the second semiconductor layer, the first semiconductor region, and the second semiconductor region, or between the second semiconductor layer and the second semiconductor region.
Since the semiconductor layer, the first semiconductor region, and the Schottky diode are short-circuited to each other, the collector current is formed from the drain electrode to the bottom of the trench recess to form the second conductivity type second semiconductor. Through the region or Schottky diode, through the source electrode in the trench recess and then to the surface source electrode, and on the other hand,
Passing through the first conductive type first semiconductor layer from the drain electrode,
In addition, the current flows through the second conductive type second semiconductor layer to the source electrode on the surface portion. As a result, the breakdown voltage of the device against the breakdown voltage is lowered, and the device is destroyed due to the parasitic transistor being turned on. It has an excellent feature that it can be effectively prevented.
【図面の簡単な説明】[Brief description of drawings]
【図１】この発明の第１の発明を適用した第１実施例に
よるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの概
要構成を模式的に示す断面図である。FIG. 1 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a first embodiment to which the first invention of the present invention is applied.
【図２】同上第１実施例構成の要部を破断して模式的に
示す平面図である。FIG. 2 is a plan view schematically showing a main part of the configuration of the first embodiment, broken away.
【図３】同上第１実施例装置にドレイン電圧を印加した
ときの空乏層（電界強度分布）の状態を模式的に示す断
面説明図である。FIG. 3 is a sectional explanatory view schematically showing a state of a depletion layer (electric field strength distribution) when a drain voltage is applied to the device of the first embodiment.
【図４】同上第１実施例装置の等価回路図である。FIG. 4 is an equivalent circuit diagram of the device according to the first embodiment.
【図５】同上第１実施例装置における耐圧とオン抵抗と
の関係を示すグラフである。FIG. 5 is a graph showing the relationship between the withstand voltage and the on-resistance in the device according to the first embodiment.
【図６】この発明の第２の発明を適用した第２実施例に
よるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの概
要構成を模式的に示す断面図である。FIG. 6 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a second embodiment to which the second invention of the present invention is applied.
【図７】この発明の第３（第４）の発明を適用した第３
実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トランジ
スタの概要構成を模式的に示す断面図である。FIG. 7 is a third example to which the third (fourth) invention of the present invention is applied;
FIG. 3 is a cross-sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to an example.
【図８】この発明のの第５の発明を適用した第４実施例
によるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの
概要構成を模式的に示す断面図である。FIG. 8 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a fourth embodiment to which the fifth invention of the present invention is applied.
【図９】この発明のの第６（第７）の発明を適用した第
５実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トラン
ジスタの概要構成を模式的に示す断面図である。FIG. 9 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a fifth embodiment to which the sixth (seventh) invention of the present invention is applied.
【図１０】この発明のの第８（第９）の発明を適用した
第６実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トラ
ンジスタの概要構成を模式的に示す断面図である。FIG. 10 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a sixth embodiment to which the eighth (ninth) invention of the present invention is applied.
【図１１】従来例によるＵＭＯＳ構造をもつ絶縁ゲート
型トランジスタの概要構成を模式的に示す断面図であ
る。FIG. 11 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a conventional example.
【図１２】同上従来例装置にドレイン電圧を印加したと
きの空乏層（電界強度分布）の状態を模式的に示す断面
説明図である。FIG. 12 is a cross-sectional explanatory view schematically showing a state of a depletion layer (electric field strength distribution) when a drain voltage is applied to the conventional example device.
【図１３】同上従来例装置の等価回路図である。FIG. 13 is an equivalent circuit diagram of the above conventional device.
１ n+型ドレイン層 ２ n-型ドレイン層（第１の半導体層） ３，１８ p型ベース層（第２の半導体層） ４ トレンチ（トレンチ凹部） ４ａ 底部 ４ｂ コーナー部 ５ n+型ソース層（第１の半導体領域） ６ ゲート絶縁膜 ７，１４，２０ ゲート電極 ８ チャネル領域 ９，１３，１３ａ，２２，２４ ソース電極 １０，２１ 層間絶縁膜 １１ ドレイン電極 １２，２３ p型ベース領域（第２の半導体領域） １５ 共通電極 １６ ゲートパッド １７ ショットキーダイオード １９ n+型ソース領域（第３の半導体領域）1 n + type drain layer 2 n − type drain layer (first semiconductor layer) 3,18 p type base layer (second semiconductor layer) 4 trench (trench recess) 4a bottom 4b corner 5n + type source layer (First semiconductor region) 6 gate insulating film 7, 14, 20 gate electrode 8 channel region 9, 13, 13a, 22, 24 source electrode 10, 21 interlayer insulating film 11 drain electrode 12, 23 p-type base region (first 2 semiconductor region) 15 common electrode 16 gate pad 17 Schottky diode 19 n + type source region (third semiconductor region)
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年９月２２日[Submission date] September 22, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００３[Name of item to be corrected] 0003
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００３】図１０には、従来の一例によるこの種のＵ
ＭＯＳ構造をもつ絶縁ゲート型トランジスタの概要構成
を模式的に示してある。この従来例は、３個のユニット
セルを並列配置させた場合である。FIG . 10 shows a U of this type according to a conventional example.
1 schematically shows a schematic structure of an insulated gate transistor having a MOS structure. In this conventional example, three unit cells are arranged in parallel.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００４[Correction target item name] 0004
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００４】すなわち、図１０に示す装置構成におい
て、従来例によるＵＭＯＳ構造の絶縁ゲート型トランジ
スタは、第１の半導体層としてのn+型ドレイン層１と、
当該n+型ドレイン層１の主面上に形成された第２の半導
体層としてのn-型ドレイン層２と、第２の半導体層とし
てのn-型ドレイン層２の表面上に p型の不純物を拡散し
て形成された p型ベース層３とを有しており、かつ当該
p型ベース層３の表面上からは、所定のパターンに従い
選択的にシリコンをエッチングして、n-型ドレイン層２
に達するトレンチ凹部（以下、トレンチと呼ぶ）４を掘
り込んである。That is, in the device structure shown in FIG. 10 , an insulated gate transistor having a UMOS structure according to the conventional example has an n + type drain layer 1 as a first semiconductor layer,
The n + -type drain layer 1 of n as a second semiconductor layer formed on the main surface - -type drain layer 2, n as the second semiconductor layer - the p-type on the type drain layer 2 of the surface And a p-type base layer 3 formed by diffusing impurities, and
From the surface of the p-type base layer 3, silicon is selectively etched according to a predetermined pattern to form the n − -type drain layer 2
A trench recess 4 (hereinafter, referred to as a trench) 4 reaching to is dug.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Name of item to be corrected] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００５】そして、前記 p型ベース層３のトレンチ４
に接する表面部には、n+型ソース層５を選択的に形成さ
せると共に、当該トレンチ４の内側壁面間にあって、底
部４a の位置までゲート絶縁膜６を介してゲート電極７
を設けることにより、トレンチ４の各側壁面側での p型
ベース層３のトレンチ面がチャネル領域８となる。Then, the trench 4 of the p-type base layer 3 is formed.
The n + type source layer 5 is selectively formed on the surface portion in contact with the gate electrode 7 between the inner wall surfaces of the trench 4 and the bottom portion 4a via the gate insulating film 6.
By providing the trench surface of p-type base layer 3 on each side wall surface side of the trench 4 becomes a channel region 8.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１０】次に、図１１には、このＵＭＯＳにドレイ
ン電圧ＶDSを印加したときの空乏層の延びを示してあ
る。Next, FIG. 11 shows the extension of the depletion layer when the drain voltage V DS is applied to this UMOS.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１２[Correction target item name] 0012
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１２】一方、前記図１０に示す構成では、n+型ソ
ース層５， p型ベース層３，およびn-型ドレイン層２に
よって形成される寄生トランジスタが存在する。こゝ
で、一般にＵＭＯＳの等価回路は、図１２(a) のように
表わされるが、実質的には、図１２(b) のようになる。
同図において、Ｒa は p型ベース層３の縦方向の抵抗で
ある。そして、ＵＭＯＳが降伏した場合、そのときの降
伏電流Ｊc は、寄生トランジスタのベース電流となり、
この降伏電流Ｊcが、当該寄生トランジスタをオンさせ
るベース電流以上になると、この寄生トランジスタを制
御できなくなるために、素子破壊をきたすことになる。On the other hand, in the structure shown in FIG. 10 , there is a parasitic transistor formed by the n + type source layer 5, the p type base layer 3, and the n − type drain layer 2. Here, a UMOS equivalent circuit is generally represented as shown in FIG. 12 (a) , but substantially becomes as shown in FIG. 12 (b) .
In the figure, Ra is the vertical resistance of the p-type base layer 3. When the UMOS breaks down, the breakdown current Jc at that time becomes the base current of the parasitic transistor,
The breakdown current Jc is equal to or on the base conductive Nagare以 turning on the parasitic transistor, in order to lose control of the parasitic transistors, thereby causing a device breakdown.
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１４[Correction target item name] 0014
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１４】[0014]
【発明が解決しようとする課題】上記のように、従来の
トレンチ構造によるＵＭＯＳでは、トレンチのコーナー
部に電界集中が発生するために、このようなトレンチ構
造をもたないパワーＭＯＳに比較するとき、低い電圧で
p型ベース層３，およびn-型ドレイン層２が降伏する。
また、寄生トランジスタが存在するために、寄生トラン
ジスタのベース電流を制御できずに、素子破壊を生ずる
という問題点があった。As described above, in the conventional UMOS having the trench structure, electric field concentration occurs in the corner portion of the trench, and therefore, when compared with the power MOS having no such trench structure. At low voltage
The p-type base layer 3 and the n − -type drain layer 2 break down.
Further, since the parasitic transistor exists, the base current of the parasitic transistor cannot be controlled, which causes a problem that the device is destroyed.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２６[Correction target item name] 0026
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２６】[0026]
【作用】この発明の各発明における絶縁ゲート型トラン
ジスタでは、トレンチ凹部の底部に第２導電型の第２の
半導体領域，またはショットキーダイオードが形成さ
れ、ソース電極に接続されているので、トレンチコーナ
ーでの電界集中が起こりにくく、また寄生トランジスタ
のベース電流が第２導電型の第２の半導体領域，または
ショットキーダイオードを通って流れる。 In the insulated gate transistor according to each of the inventions, the second semiconductor region of the second conductivity type or the Schottky diode is formed at the bottom of the trench recess.
Since it is connected to the source electrode, the trench corner
Is less likely to concentrate in the electric field, and is a parasitic transistor
A second semiconductor region having a base current of the second conductivity type, or
It flows through a Schottky diode.
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２７[Name of item to be corrected] 0027
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２７】[0027]
【実施例】以下、この発明に係る絶縁ゲート型トランジ
スタの各別の実施例につき、図１ないし図９を参照して
詳細に説明する。なお、これらの図１ないし図９に示す
各別の実施例構成において、上記図１０ないし図１２に
示す従来例構成と同一符号は、同一または相当部分を表
している。EXAMPLES Hereinafter, the another embodiment of the insulated gate transistor according to this invention will, Figures 1 with reference to FIG. 9 will be described in detail. In each of the configurations of the embodiments shown in FIGS . 1 to 9 , the same reference numerals as those in the configurations of the conventional examples shown in FIGS . 10 to 12 represent the same or corresponding parts.
【手続補正９】[Procedure Amendment 9]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３０[Name of item to be corrected] 0030
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３０】また、前記各トレンチ４の底部４a の中間
部には、第２の半導体領域としてのp型ベース領域１２
を拡散形成させた上で、当該各トレンチ４の左，右内側
壁面に接して底部４a の位置まで、それぞれにゲート絶
縁膜６を介してゲート電極１４を形成させることによ
り、トレンチ４の各側壁面側での p型ベース層３のトレ
ンチ面がそれぞれにチャネル領域８となる。In the middle of the bottom 4a of each trench 4, a p-type base region 12 serving as a second semiconductor region is formed.
On the respective sides of the trench 4 by forming a gate electrode 14 through the gate insulating film 6 on each of the left and right inner wall surfaces of the trench 4 up to the position of the bottom 4a. Tray of p-type base layer 3 on the wall side
The punch planes become the channel regions 8 respectively.
【手続補正１０】[Procedure Amendment 10]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３６[Correction target item name] 0036
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３６】この第１実施例による構成の場合、ドレイ
ン電極１１とソース電極１３間にドレイン電圧ＶDSが印
加されると、空乏層は、 p型ベース層３と、トレンチ４
の底部での p型ベース領域１２との双方から延び始める
ために、従来例での図１１に示したトレンチ４のコーナ
ー部４ｂにおける電界集中が、当該 p型ベース領域１２
からの空乏層の延びによって緩和されることになる。In the structure according to the first embodiment, when the drain voltage V DS is applied between the drain electrode 11 and the source electrode 13, the depletion layer becomes the p-type base layer 3 and the trench 4.
Since it starts to extend from both the p-type base region 12 at the bottom of the p-type base region 12 and the p-type base region 12 at the corner 4b of the trench 4 shown in FIG.
Will be alleviated by the extension of the depletion layer.
【手続補正１１】[Procedure Amendment 11]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００４３[Correction target item name] 0043
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００４３】まず、前記深さｈについては、こゝでのＵ
ＭＯＳの装置構成上、可能な限り小さい方が、耐圧を高
くでき、かつオン抵抗が小さくなる。但し、少なくとも
ゲート電極１４の縦方向の幅以内でなければならない。
なお、この場合、オン抵抗とは、このＵＭＯＳに電圧が
印加されてオンし、ドレイン電極１１からソース電極１
３にドレイン電流が流れるときの両電極間の抵抗であ
る。First, regarding the depth h, U at this point
Due to the device structure of the MOS device, the smaller the device voltage is, the higher the breakdown voltage can be and the smaller the on-resistance is. However, it must be at least within the vertical width of the gate electrode 14.
In this case, the on-resistance means that the UMOS is turned on when a voltage is applied to the UMOS and the drain electrode 11 changes to the source electrode
3 is a resistance between the electrodes when the drain current is flow to.
【手続補正１２】[Procedure Amendment 12]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００４４[Correction target item name] 0044
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００４４】また、前記寸法ｌについては、可能な限り
小さい方が、耐圧を高くし得るが、逆にオン抵抗が増加
する。従って、寸法ｌは耐圧とオン抵抗の関係を考慮し
て決定する必要がある。 [0044] Further, the Dimension l is the smaller as possible, but may increase the breakdown voltage, reverse the ON resistance you increase <br/>. It follows, dimension l In view of the relationship between the breakdown voltage and the on-resistance
Need to decide.
【手続補正１３】[Procedure Amendment 13]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００４５[Name of item to be corrected] 0045
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００４５】次に、図５はこの発明の第２の発明を適用
した第２実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 5 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a second embodiment to which the second invention of the present invention is applied.
【手続補正１４】[Procedure Amendment 14]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００４８[Correction target item name] 0048
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００４８】次に、図６はこの発明の第３の発明を適用
した第３実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 6 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a third embodiment to which the third invention of the present invention is applied.
【手続補正１５】[Procedure Amendment 15]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５０[Correction target item name] 0050
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５０】こゝで、一般的には、このような構造にし
た方が、単一面積でのチャネル領域８の割合が増えるの
で、オン時の抵抗を低減し得るのであるが、一方、この
ような構造の場合は、寄生トランジスタが簡単にオンし
て了うことから、前記図１０の従来例構造では、 p型ベ
ース層３をソース電極１３に短絡させる必要がある。Here, in general, the ratio of the channel region 8 in a single area increases with such a structure .
In, but as it can reduce the resistance of the ON state, on the other hand, in the case of such a structure, since Ryou parasitic transistor is easily turned on, in the conventional example structure of FIG. 10, p type base It is necessary to short the layer 3 to the source electrode 13.
【手続補正１６】[Procedure Amendment 16]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５１[Correction target item name] 0051
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５１】しかし、図６の第３実施例構造のように、
トレンチ４の底部４a に p型ベース領域１２を形成させ
た構造では、先に述べた如く、寄生トランジスタによる
素子破壊が極めて起り難いために、n+型ソース層１９を
介して p型ベース層１８をソース電極１３に短絡させる
ことができる。なお、この第３実施例装置においては、
第２実施例装置の場合と同様に、トレンチ４の底部４a
に形成される p型ベース領域１２に代えて、ショットキ
ーダイオード１７を形成させてもよく、同様な作用、効
果が得られるもので、この発明の第４発明を構成する。However, as in the structure of the third embodiment of FIG.
In the structure in which the p-type base region 12 is formed in the bottom portion 4a of the trench 4, as described above, the element breakdown due to the parasitic transistor is extremely unlikely to occur, so that the p-type base layer 18 is interposed via the n + -type source layer 19. Can be short-circuited to the source electrode 13. In the device of the third embodiment,
As in the case of the device of the second embodiment, the bottom portion 4a of the trench 4 is
The Schottky diode 17 may be formed in place of the p-type base region 12 formed in 1., and the same action and effect can be obtained, which constitutes the fourth invention of the present invention.
【手続補正１７】[Procedure Amendment 17]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５２[Correction target item name] 0052
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５２】次に、図７はこの発明の第５の発明を適用
した第４実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 7 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a fourth embodiment to which the fifth invention of the present invention is applied.
【手続補正１８】[Procedure 18]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５３[Correction target item name] 0053
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５３】この第４実施例装置は、前記図１０の従来
例装値の構成において、前記図１の第１実施例による構
成、つまり、トレンチ４の底部４a に p型ベース領域２
３を形成させたものであり、他の各部の構成は全く同一
である。こゝで、図７中，２０は前記ゲート電極７に対
応するゲート電極、２１は前記層間絶縁膜１０に対応す
る層間絶縁膜、２２は前記ソース電極９に対応するソー
ス電極である。The device of the fourth embodiment is the same as the device of the first embodiment shown in FIG. 1 in the structure of the conventional example shown in FIG. 10 , that is, the p-type base region 2 is formed at the bottom 4a of the trench 4.
3 is formed, and the configurations of the other parts are exactly the same. Here, in FIG. 7 , 20 is a gate electrode corresponding to the gate electrode 7, 21 is an interlayer insulating film corresponding to the interlayer insulating film 10, and 22 is a source electrode corresponding to the source electrode 9.
【手続補正１９】[Procedure Amendment 19]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５５[Correction target item name] 0055
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５５】次に、図８はこの発明の第６の発明を適用
した第５実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 8 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a fifth embodiment to which the sixth invention of the present invention is applied.
【手続補正２０】[Procedure amendment 20]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５６[Correction target item name] 0056
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５６】この第５実施例装置は、前記図１０の従来
例の構成の一部に、前記図１の第１実施例でのトレンチ
４の底部４a に p型ベース領域１２を形成させた構造を
取り入れたものであり、他の各部の構成は全く同一であ
る。こゝで、図８中，２４は前記ソース電極９に対応す
るソース電極である。[0056] The fifth embodiment apparatus, a part of the conventional configuration of FIG. 10, to form a p-type base region 12 at the bottom 4a of the trench 4 in the first embodiment of FIG. 1 structure The configuration of other parts is exactly the same. Here, in FIG. 8 , 24 is a source electrode corresponding to the source electrode 9.
【手続補正２１】[Procedure correction 21]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５８[Name of item to be corrected] 0058
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５８】次に、図９はこの発明の第８の発明を適用
した第６実施例によるＵＭＯＳ構造をもつ絶縁ゲート型
トランジスタの概要構成を模式的に示す断面図である。Next, FIG. 9 is a sectional view schematically showing a schematic structure of an insulated gate transistor having a UMOS structure according to a sixth embodiment to which the eighth invention of the present invention is applied.
【手続補正２２】[Procedure correction 22]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５９[Correction target item name] 0059
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５９】この第６実施例装置は、前記図１０の従来
例の構成の一部に、前記図１の第１実施例でのトレンチ
４の底部４a に p型ベース領域１２を形成させた構成、
および前記図６の第３実施例の構成をそれぞれ取り入れ
たものであり、他の各部の構成は全く同一である。[0059] The sixth embodiment apparatus, a part of the conventional configuration of FIG. 10, a configuration to form a p-type base region 12 at the bottom 4a of the trench 4 in the first embodiment of FIG. 1 ,
The configuration of the third embodiment shown in FIG. 6 is incorporated, and the configuration of the other parts is exactly the same.
【手続補正２３】[Procedure amendment 23]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００６２[Correction target item name] 0062
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００６２】[0062]
【発明の効果】以上、各実施例によって詳述したよう
に、この発明によれば、第１導電型の第１の半導体層，
および当該第１の半導体層の表面上に形成させた第２導
電型の第２の半導体層を用い、第２の半導体層の表面側
から第１の半導体層内に達するまで複数の各トレンチ凹
部を選択的に堀り込み、かつ第２の半導体層の各トレン
チ凹部に接する表面部に第１導電型の第１の半導体領域
を選択的に形成させると共に、各トレンチ凹部内の底部
に第２導電型の第２の半導体領域を選択的に形成させる
か、あるいはショットキーダイオードを形成させ、ま
た、各トレンチ凹部内の両内側壁面にゲート絶縁膜を介
して個々の各ゲート電極を形成した上で、ソース電極に
より、これらの第２の半導体層，第１の半導体領域，お
よび第２の半導体領域の相互間，あるいはこれらの第２
の半導体層，第１の半導体領域，およびショットキーダ
イオードの相互間を短絡して構成させたので、トレンチ
コーナーでの電界集中が起こりにくく、また寄生トラン
ジスタのベース電流が第２の半導体領域あるいはショッ
トキーダイオードを通って流れることになり、この結
果、降伏電圧に対する素子の耐圧の低下，ならびに寄生
トランジスタのオンによる素子の破壊などをそれぞれ良
好かつ効果的に防止し得るという優れた特長がある。As described above in detail for each embodiment, according to the present invention, the first semiconductor layer of the first conductivity type,
And using the second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, a plurality of trench recesses are formed from the surface side of the second semiconductor layer to the inside of the first semiconductor layer. And selectively forming a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer in contact with each trench recess, and forming a second semiconductor on the bottom of each trench recess. A second semiconductor region of conductivity type is selectively formed or a Schottky diode is formed, and each gate electrode is formed on both inner wall surfaces in each trench recess via a gate insulating film. At the source electrode, between the second semiconductor layer, the first semiconductor region, and the second semiconductor region, or these second semiconductor layers.
Since the semiconductor layer, the first semiconductor region, and the Schottky diode are short-circuited to each other, the trench
Electric field concentration is less likely to occur at corners, and parasitic
The base current of the transistor is the second semiconductor region or
Since it flows through the Toky diode, as a result, it is possible to satisfactorily and effectively prevent the reduction of the breakdown voltage of the element against the breakdown voltage and the breakdown of the element due to the turning on of the parasitic transistor.
【手続補正２４】[Procedure correction 24]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図１】この発明の第１の発明を適用した第１実施例に
よるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの概
要構成を模式的に示す断面図である。FIG. 1 is a sectional view schematically showing a schematic configuration of an insulated gate transistor having a UMOS structure according to a first embodiment to which the first invention of the present invention is applied.
【図２】同上第１実施例構成の要部を破断して模式的に
示す平面図である。FIG. 2 is a plan view schematically showing a main part of the configuration of the first embodiment, broken away.
【図３】同上第１実施例装置にドレイン電圧を印加した
ときの空乏層（電界強度分布）の状態を模式的に示す断
面説明図である。FIG. 3 is a sectional explanatory view schematically showing a state of a depletion layer (electric field strength distribution) when a drain voltage is applied to the device of the first embodiment.
【図４】同上第１実施例装置の等価回路図である。FIG. 4 is an equivalent circuit diagram of the device according to the first embodiment.
【図５】この発明の第２の発明を適用した第２実施例に
よるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの概
要構成を模式的に示す断面図である。 FIG. 5 shows a second embodiment to which the second invention of the present invention is applied.
Outline of Insulated Gate Transistor with UMOS Structure
It is sectional drawing which shows a required structure typically.
【図６】この発明の第３（第４）の発明を適用した第３
実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トランジ
スタの概要構成を模式的に示す断面図である。 FIG. 6 is a third view to which the third (fourth) invention of the present invention is applied;
Insulated gate type transistor having UMOS structure according to an embodiment
It is sectional drawing which shows the schematic structure of a star typically.
【図７】この発明のの第５の発明を適用した第４実施例
によるＵＭＯＳ構造をもつ絶縁ゲート型トランジスタの
概要構成を模式的に示す断面図である。 FIG. 7 is a fourth embodiment to which the fifth invention of the present invention is applied.
Of an insulated gate transistor having a UMOS structure according to
It is sectional drawing which shows a schematic structure typically.
【図８】この発明のの第６（第７）の発明を適用した第
５実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トラン
ジスタの概要構成を模式的に示す断面図である。 FIG. 8 is a diagram showing the sixth (seventh) invention of the present invention;
Insulated gate type transistor having UMOS structure according to Example 5
It is sectional drawing which shows the schematic structure of a transistor.
【図９】この発明のの第８（第９）の発明を適用した第
６実施例によるＵＭＯＳ構造をもつ絶縁ゲート型トラン
ジスタの概要構成を模式的に示す断面図である。 FIG. 9 is a diagram showing an eighth (9th) aspect of the invention;
Insulated Gate Transistor Having UMOS Structure According to Sixth Embodiment
It is sectional drawing which shows the schematic structure of a transistor.
【図１０】従来例によるＵＭＯＳ構造をもつ絶縁ゲート
型トランジスタの概要構成を模式的に示す断面図であ
る。 FIG. 10 is an insulated gate having a UMOS structure according to a conventional example .
FIG. 3 is a cross-sectional view schematically showing a schematic configuration of a transistor
It
【図１１】同上従来例装置にドレイン電圧を印加したと
きの空乏層（電界強度分布）の状態を模式的に示す断面
説明図である。 FIG. 11 is the same as above when a drain voltage is applied to the conventional device .
Cross section that schematically shows the state of the mushroom depletion layer (electric field strength distribution)
FIG.
【図１２】同上従来例装置の等価回路図である。 FIG. 12 is an equivalent circuit diagram of the above conventional device.
【符号の説明】 １ n+型ドレイン層 ２ n-型ドレイン層（第１の半導体層） ３，１８ p型ベース層（第２の半導体層） ４ トレンチ（トレンチ凹部） ４ａ 底部 ４ｂ コーナー部 ５ n+型ソース層（第１の半導体領域） ６ ゲート絶縁膜 ７，１４，２０ ゲート電極 ８ チャネル領域 ９，１３，１３ａ，２２，２４ ソース電極 １０，２１ 層間絶縁膜 １１ ドレイン電極 １２，２３ p型ベース領域（第２の半導体領域） １５ 共通電極 １６ ゲートパッド １７ ショットキーダイオード １９ n+型ソース領域（第３の半導体領域）[Description of Reference Signs] 1 n + type drain layer 2 n − type drain layer (first semiconductor layer) 3,18 p type base layer (second semiconductor layer) 4 trench (trench recess) 4a bottom 4b corner 5 n + type source layer (first semiconductor region) 6 gate insulating film 7, 14, 20 gate electrode 8 channel region 9, 13, 13a, 22, 24 source electrode 10, 21 interlayer insulating film 11 drain electrode 12, 23 p Type base region (second semiconductor region) 15 Common electrode 16 Gate pad 17 Schottky diode 19 n + type source region (third semiconductor region)
【手続補正２５】[Procedure correction 25]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図２[Name of item to be corrected] Figure 2
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図２】 [Fig. 2]
【手続補正２６】[Procedure Amendment 26]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図５[Name of item to be corrected] Figure 5
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図５】 [Figure 5]
【手続補正２７】[Procedure Amendment 27]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図６[Name of item to be corrected] Figure 6
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図６】 [Figure 6]
【手続補正２８】[Procedure correction 28]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図７[Name of item to be corrected] Figure 7
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図７】 [Figure 7]
【手続補正２９】[Procedure correction 29]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図８[Correction target item name] Figure 8
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図８】 [Figure 8]
【手続補正３０】[Procedure amendment 30]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図９[Correction target item name] Figure 9
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図９】 [Figure 9]
【手続補正３１】[Procedure correction 31]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図１０[Name of item to be corrected] Fig. 10
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１０】 [Figure 10]
【手続補正３２】[Procedure correction 32]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図１１[Name of item to be corrected] Fig. 11
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１１】 FIG. 11
【手続補正３３】[Procedure amendment 33]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図１２[Name of item to be corrected] Fig. 12
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１２】 [Fig. 12]
Claims (9)
該第１の半導体層の表面上に形成させた第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記第２の半導体層の各トレン
チ凹部に接する表面部に選択的に形成させた第１導電型
の第１の半導体領域と、前記各トレンチ凹部内の底部に
選択的に形成させた第２導電型の第２の半導体領域と、
前記各トレンチ凹部内の両内側壁面に対して、それぞれ
にゲート絶縁膜を介して接し、かつ層間絶縁膜により被
覆させて、前記第２の半導体領域の端部に重なるように
形成させた個々の各ゲート電極と、前記第２の半導体
層，第１の半導体領域，および第２の半導体領域の相互
間を短絡して形成させたソース電極と、前記第１の半導
体層の裏面側対応に形成させたドレイン電極とを、少な
くとも備えることを特徴とする絶縁ゲート型トランジス
タ。1. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. From above, a plurality of trench recesses selectively dug into the first semiconductor layer and a first conductive layer selectively formed on a surface portion of the second semiconductor layer in contact with the trench recesses. A first semiconductor region of the second conductivity type, and a second semiconductor region of the second conductivity type selectively formed at the bottom of each of the trench recesses,
Each of the inner wall surfaces in each of the trench recesses is formed so as to be in contact with each other via a gate insulating film and covered with an interlayer insulating film so as to overlap the end portion of the second semiconductor region. A source electrode formed by short-circuiting each gate electrode, the second semiconductor layer, the first semiconductor region, and the second semiconductor region, and a back electrode side of the first semiconductor layer. An insulated gate transistor comprising at least the drain electrode thus formed.
該第１の半導体層の表面上に形成させた第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記第２の半導体層の各トレン
チ凹部に接する表面部に選択的に形成させた第１導電型
の第１の半導体領域と、前記各トレンチ凹部内の両内側
壁面に対して、それぞれにゲート絶縁膜を介して接し、
かつ層間絶縁膜により被覆して形成させた個々の各ゲー
ト電極と、前記各ゲート電極を被覆する層間絶縁膜間で
のトレンチ凹部内の底部に設けたショットキーダイオー
ドと、前記第２の半導体層，第１の半導体領域，および
ショットキーダイオードの相互間を短絡して形成させた
ソース電極と、前記第１の半導体層の裏面側対応に形成
させたドレイン電極とを、少なくとも備えることを特徴
とする絶縁ゲート型トランジスタ。2. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. From above, a plurality of trench recesses selectively dug into the first semiconductor layer and a first conductive layer selectively formed on a surface portion of the second semiconductor layer in contact with the trench recesses. The first semiconductor region of the mold and both inner wall surfaces in the trench recesses are in contact with each other through a gate insulating film,
In addition, each gate electrode formed by being covered with an interlayer insulating film, a Schottky diode provided at the bottom in the trench recess between the interlayer insulating films covering each gate electrode, and the second semiconductor layer At least a source electrode formed by short-circuiting the first semiconductor region and the Schottky diode, and a drain electrode formed corresponding to the back surface side of the first semiconductor layer. Insulated gate transistor.
該第１の半導体層の表面上に形成させた第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記各トレンチ凹部間での第２
の半導体層上に形成させた第１導電型の第３の半導体領
域と、前記各トレンチ凹部内の底部に選択的に形成させ
た第２導電型の第２の半導体領域と、前記各トレンチ凹
部内の両内側壁面に対して、それぞれにゲート絶縁膜を
介して接し、かつ層間絶縁膜により被覆させて、前記第
２の半導体領域の端部に重なるように形成させた個々の
各ゲート電極と、前記第３の半導体領域，および第２の
半導体領域の相互間を短絡して形成させたソース電極
と、前記第１の半導体層の裏面側対応に形成させたドレ
イン電極とを、少なくとも備えることを特徴とする絶縁
ゲート型トランジスタ。3. A first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. A plurality of trench recesses that are selectively dug from the top to the inside of the first semiconductor layer, and a second trench between the trench recesses.
Second conductive type third semiconductor region formed on the semiconductor layer, second conductive type second semiconductor region selectively formed at the bottom of each trench recess, and each trench recess The respective inner side wall surfaces of the inner side wall surface and the inner wall surfaces of the inner side wall surface of the second semiconductor region, which are in contact with each other through the gate insulating film and are covered with the interlayer insulating film so as to overlap the end portions of the second semiconductor region. A source electrode formed by short-circuiting the third semiconductor region and the second semiconductor region, and a drain electrode formed corresponding to the back surface side of the first semiconductor layer. Insulated gate type transistor.
該第１の半導体層の表面上に形成させた第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記各トレンチ凹部間での第２
の半導体層上に形成させた第１導電型の第３の半導体領
域と、前記各トレンチ凹部内の両内側壁面に対して、そ
れぞれにゲート絶縁膜を介して接し、かつ層間絶縁膜に
より被覆して形成させた個々の各ゲート電極と、前記各
ゲート電極を被覆する層間絶縁膜間でのトレンチ凹部内
の底部に設けたショットキーダイオードと、前記第３の
半導体領域，およびショットキーダイオードの相互間を
短絡して形成させたソース電極と、前記第１の半導体層
の裏面側対応に形成させたドレイン電極とを、少なくと
も備えることを特徴とする絶縁ゲート型トランジスタ。4. A first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. A plurality of trench recesses that are selectively dug from the top to the inside of the first semiconductor layer, and a second trench between the trench recesses.
The third semiconductor region of the first conductivity type formed on the semiconductor layer and both inner wall surfaces in each of the trench recesses are in contact with each other through the gate insulating film and are covered with the interlayer insulating film. The individual Schottky diodes provided at the bottom of the trench recess between the respective gate electrodes formed as described above, the interlayer insulating films covering the respective gate electrodes, the third semiconductor region, and the Schottky diode. An insulated gate transistor comprising at least a source electrode formed by short-circuiting between the two and a drain electrode formed corresponding to the back surface side of the first semiconductor layer.
該第１の半導体層の表面上に形成された第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込むと共
に、掘り込んだ底部に選択的に第２の半導体領域を形成
させた複数の各トレンチ凹部と、前記第２の半導体層の
各トレンチ凹部に接する表面部に選択的に形成された第
１導電型の第１の半導体領域と、前記各トレンチ凹部内
の両内側壁面に対して、それぞれにゲート絶縁膜を介し
て接し、かつ上部，下部を層間絶縁膜により被覆して形
成させたゲート電極と、前記第２の半導体層，および第
１の半導体領域の相互間を短絡して形成させたソース電
極と、前記第１の半導体層の裏面側対応に形成させたド
レイン電極とを、少なくとも備えることを特徴とする絶
縁ゲート型トランジスタ。5. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. A plurality of trench recesses in which the second semiconductor region is selectively formed from the top until reaching the inside of the first semiconductor layer, and a second semiconductor region is selectively formed in the dug bottom, and the second semiconductor layer. A first semiconductor region of the first conductivity type selectively formed on the surface portion in contact with each trench recess, and both inner wall surfaces in each trench recess are in contact with each other via a gate insulating film, A gate electrode formed by covering the upper and lower portions with an interlayer insulating film; a source electrode formed by short-circuiting the second semiconductor layer and the first semiconductor region; and the first electrode. The drain electrode formed on the back side of the semiconductor layer An insulated gate transistor characterized in that it is provided at least.
該第１の半導体層の表面上に形成された第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層に達して選択的に掘り込まれた複数の
各トレンチ凹部と、前記第２の半導体層の各トレンチ凹
部に接する表面部に選択的に形成された第１導電型の第
１の半導体領域と、前記隣接する一方のトレンチ凹部内
の両内側壁面に対して、それぞれにゲート絶縁膜を介し
て接し、かつ上部，下部を層間絶縁膜により被覆して形
成させたゲート電極，および他方のトレンチ凹部内の底
部に第２導電型の第２の半導体領域を選択的に形成させ
ると共に、当該他方のトレンチ凹部内の両内側壁面に対
して、それぞれにゲート絶縁膜を介して接し、かつ層間
絶縁膜により被覆させて、前記第２の半導体領域の端部
に重なるように形成させた個々の各ゲート電極と、前記
第２の半導体層，第１の半導体領域，および第２の半導
体領域の相互間を短絡して形成させたソース電極と、前
記第１の半導体層の裏面側対応に形成させたドレイン電
極とを、少なくとも備えることを特徴とする絶縁ゲート
型トランジスタ。6. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. From above, a plurality of trench recesses that reach the first semiconductor layer and are selectively dug therein, and a first conductive layer that is selectively formed on a surface portion of the second semiconductor layer that is in contact with the trench recesses. The first semiconductor region of the mold and the inner wall surfaces in both of the adjacent trench recesses are in contact with each other through the gate insulating film, and the upper and lower portions are covered with the interlayer insulating film. A second semiconductor region of the second conductivity type is selectively formed at the bottom of the gate electrode and the other trench recess, and a gate insulating film is formed on both inner wall surfaces of the other trench recess. And is covered with an interlayer insulating film. The individual gate electrodes formed so as to overlap the end portions of the second semiconductor region and the second semiconductor layer, the first semiconductor region, and the second semiconductor region are short-circuited with each other. An insulated gate transistor, comprising at least a source electrode formed as described above and a drain electrode formed so as to correspond to the back surface side of the first semiconductor layer.
該第１の半導体層の表面上に形成された第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層に達して選択的に掘り込まれた複数の
各トレンチ凹部と、前記第２の半導体層の各トレンチ凹
部に接する表面部に選択的に形成された第１導電型の第
１の半導体領域と、前記隣接する一方のトレンチ凹部内
の両内側壁面に対して、それぞれにゲート絶縁膜を介し
て接し、かつ上部，下部を層間絶縁膜により被覆して形
成させたゲート電極，および他方のトレンチ凹部内の両
内側壁面に対して、それぞれにゲート絶縁膜を介して接
し、かつ層間絶縁膜により被覆して形成させた個々の各
ゲート電極と、前記他方のトレンチ凹部内の各ゲート電
極を被覆する層間絶縁膜間でのトレンチ凹部内の底部に
設けたショットキーダイオードと、前記第２の半導体
層，第１の半導体領域，およびショットキーダイオード
の相互間を短絡して形成させたソース電極と、前記第１
の半導体層の裏面側対応に形成させたドレイン電極と
を、少なくとも備えることを特徴とする絶縁ゲート型ト
ランジスタ。7. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. From above, a plurality of trench recesses that reach the first semiconductor layer and are selectively dug therein, and a first conductive layer that is selectively formed on a surface portion of the second semiconductor layer in contact with the trench recesses. The first semiconductor region of the mold and the inner wall surfaces in both of the adjacent trench recesses are in contact with each other through the gate insulating film, and the upper and lower portions are covered with the interlayer insulating film. Each gate electrode formed by being in contact with the gate electrode and both inner wall surfaces in the other trench recess via the gate insulating film and being covered with the interlayer insulating film, and the other trench recess Insulation covering each gate electrode inside A Schottky diode provided at the bottom of the trench recess between the edge films, a source electrode formed by short-circuiting the second semiconductor layer, the first semiconductor region, and the Schottky diode; First
And a drain electrode formed so as to correspond to the back surface side of the semiconductor layer.
該第１の半導体層の表面上に形成された第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記各トレンチ凹部間での第２
の半導体層上に形成させた第１導電型の第３の半導体領
域と、前記隣接する一方のトレンチ凹部内の両内側壁面
に対して、それぞれにゲート絶縁膜を介して接し、かつ
上部，下部を層間絶縁膜により被覆して形成させたゲー
ト電極，および他方のトレンチ凹部内の底部に第２導電
型の第２の半導体領域を選択的に形成させると共に、当
該他方のトレンチ凹部内の両内側壁面に対して、それぞ
れにゲート絶縁膜を介して接し、かつ層間絶縁膜により
被覆して第２の半導体領域の端部に重なるように形成さ
せた個々の各ゲート電極と、前記第３の半導体領域，お
よび第２の半導体領域の相互間を短絡して形成させたソ
ース電極と、前記第１の半導体層の裏面側対応に形成さ
せたドレイン電極とを、少なくとも備えることを特徴と
する絶縁ゲート型トランジスタ。8. A first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. A plurality of trench recesses that are selectively dug from the top to the inside of the first semiconductor layer, and a second trench between the trench recesses.
The third semiconductor region of the first conductivity type formed on the semiconductor layer and both inner wall surfaces in the adjacent one of the trench recesses through the gate insulating film, and the upper and lower portions. And a gate electrode formed by covering with an interlayer insulating film, and a second semiconductor region of the second conductivity type is selectively formed at the bottom of the other trench recess, and both inner sides of the other trench recess are formed. The respective gate electrodes, which are in contact with the wall surface through the gate insulating film and are covered with the interlayer insulating film so as to overlap the end portions of the second semiconductor region, and the third semiconductor. An insulated gate, comprising at least a source electrode formed by short-circuiting a region and a second semiconductor region, and a drain electrode formed corresponding to a back surface side of the first semiconductor layer. Type Transistor.
該第１の半導体層の表面上に形成された第２導電型の第
２の半導体層と、前記第２の半導体層の表面上から、前
記第１の半導体層内に達するまで選択的に掘り込んだ複
数の各トレンチ凹部と、前記各トレンチ凹部間での第２
の半導体層上に形成させた第１導電型の第３の半導体領
域と、前記隣接する一方のトレンチ凹部内の両内側壁面
に対して、それぞれにゲート絶縁膜を介して接し、かつ
上部，下部を層間絶縁膜により被覆して形成させたゲー
ト電極，および他方のトレンチ凹部内の両内側壁面に対
して、それぞれにゲート絶縁膜を介して接し、かつ層間
絶縁膜により被覆して形成させた個々の各ゲート電極
と、前記他方のトレンチ凹部内の各ゲート電極を被覆す
る層間絶縁膜間でのトレンチ凹部内の底部に設けたショ
ットキーダイオードと、前記第３の半導体領域，および
ショットキーダイオードの相互間を短絡して形成させた
ソース電極と、前記第１の半導体層の裏面側対応に形成
させたドレイン電極とを、少なくとも備えることを特徴
とする絶縁ゲート型トランジスタ。9. A first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, and a surface of the second semiconductor layer. A plurality of trench recesses that are selectively dug from the top to the inside of the first semiconductor layer, and a second trench between the trench recesses.
The third semiconductor region of the first conductivity type formed on the semiconductor layer and the inner wall surfaces in the adjacent one of the trench recesses through the gate insulating film, and the upper and lower portions. A gate electrode formed by being covered with an interlayer insulating film, and both inner wall surfaces in the other trench recess, which are in contact with each other through the gate insulating film and are formed by being covered with an interlayer insulating film. Of the gate electrode and the Schottky diode provided at the bottom of the trench recess between the interlayer insulating films covering the gate electrodes of the other trench recess, the third semiconductor region, and the Schottky diode. At least a source electrode formed by short-circuiting each other and a drain electrode formed corresponding to the back surface side of the first semiconductor layer are provided. Transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3156370A JP2682272B2 (en) | 1991-06-27 | 1991-06-27 | Insulated gate transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3156370A JP2682272B2 (en) | 1991-06-27 | 1991-06-27 | Insulated gate transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH057002A true JPH057002A (en) | 1993-01-14 |
| JP2682272B2 JP2682272B2 (en) | 1997-11-26 |
Family
ID=15626271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3156370A Expired - Fee Related JP2682272B2 (en) | 1991-06-27 | 1991-06-27 | Insulated gate transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2682272B2 (en) |
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