JP2008505480A - Trench type MOSFET with clamp diode in deep position - Google Patents

Abstract

In a trench gate type MOSFET, an avalanche current is clamped without excessively increasing an on-resistance, and field plate induction (FPI) impact ionization is minimized.
A trench gate type MOSFET is provided with a body region 843 having a conductivity opposite to that of an epitaxial layer 842 and shallower than a gate 844, and a clamp region 853 deeper than the body region and heavily doped and shallower than the trench. The Zener PN junction clamps the drain-source voltage below the FPI breakdown voltage of the body PN junction near the trench, but is shallower than the trench and does not cause an excessive decrease in the maximum DS voltage. In the manufacture of this structure, the junction depth and the dopant concentration can be accurately controlled by using the continuous implantation method, but it may be formed by implantation before forming the gate bus or implantation through the gate bus after the formation.
[Selection] Figure 13A

Description

  Vertical intra-trench gate power MOSFETs rapidly take over all other forms of low voltage power MOSFETs due to their off-state voltage blocking capability, high cell density, high current capacity, and their inherent low on-resistance. Replaced. 1A, which is a cross-sectional view of the prior art, has an array of trenches formed by etching, covered with a thin gate oxide layer 104 and embedded with a polysilicon gate 105 therein. . The entire device is formed on an epitaxial layer 102 of the same conductivity type grown on a heavily doped substrate 101. The epitaxial layer 102 functioning as the drain of the trench gate type MOSFET 100 has its thickness and dopant concentration adjusted to adjust the optimum trade-off between the off-state breakdown voltage and the on-state conductivity.

  MOSFET 100 is often referred to as a trench-gate DMOS device, where “D” is used to form the channel region of the device by double diffusion (ie, two successive diffusion processes, one being formed inside the other). It is an acronym for Double. The body region 103, which is deeper in the double diffusion portion, has a conductivity type different from that of the epitaxial layer 102, and forms a body-drain junction of the MOSFET 100. The shallower region 106 (including regions 106A, 106B, 106C, 106D, etc.) forms a junction with a body region 108 of a different conductivity type that serves as the source of MOSFET 100 contained therein. Therefore, the channel region of this MOSFET is provided vertically along the side surface of the gate 105 embedded in the body region 103.

  In the drawing, the source region 106 (labeled N + to indicate high concentration) is N-type, and the body region 103 (labeled PB) is P-type. Reference numeral 106 (labeled by Nepi) is an N type. A MOSFET having an N-type source and drain is referred to as an N-channel device. The manufacturing process of MOSFET 100 can integrally form from one to a maximum of millions of transistors connected in parallel, but each transistor is a modification of an N-channel device. Alternatively, the substrate, epitaxial layer, and source may be formed P-type (and the body region N-type), all forming a parallel array of P-channel devices. The net result is a device that has only three terminals, source, drain, and gate, despite the fact that millions of devices are integrated, as shown schematically in FIG. 1B. . Unlike conventional CMOS integrated circuits, there is currently no method for integrating the N-channel and P-channel types of trench MOSFET devices into a single silicon.

  Quite unlike conventional surface MOSFETs used in ICs, an important feature of DMOS devices is that their channel length depends on the source-body and body-drain depths, not the photolithography dimensions of their polysilicon gates. This is the point determined by the difference. Since the gate and channel of the in-trench gate MOSFET are oriented perpendicular to the surface of the die, current flows vertically through the bulk of silicon and escapes to the back side of the wafer. Such devices are therefore referred to as vertical conduction devices. By using a thick metal 109 (generally, aluminum containing a small amount of copper and silicon), the connection to the source region 106 is facilitated, and the body region 103 and the source region 106 are connected to the shallow P + contact region 107 ( (Including regions 107A, 107B, etc.). Electrical connection to the body region 103 is necessary to bias the body region 103 for proper threshold voltage and suppress parasitic bipolar junction transistors. The existence and significance of this parasitic transistor will be described in detail later. Electrical connection to the drain is typically facilitated through the backside of the substrate 101 by a titanium, nickel, and silver sandwich structure formed after wafer thinning (ie, after completion of the wafer fabrication process).

  When using a diffusion process to form the MOSFET 100, the concentration of the source region 106 needs to be higher than the body region 103, and the body region 103 is doped to a higher concentration than the epitaxial 102. Since the concentration of the body region is higher than that of the epitaxial 102, most of the depletion region that expands in the MOSFET 100 during reverse bias operation occurs not in the body region 103 but in the lightly doped epitaxial drain 102. Accordingly, MOSFET 100 having a short channel length can support a large reverse bias voltage without the risk of “punch-through” of the depletion region to source region 106. Typical channel lengths are even less than 1.5 microns even in 30V or 100V rated devices. In conventional surface MOSFETs, a 0.5 micron channel length can only support about 5V to 10V.

  Recent inventions, such as those described in US Pat. No. 6,413,822 (Williams et al.), Use a method that does not double diffusion, but does all that is substantially unnecessary by injection. The short channel length obtained in an as-implanted (ie, dopant profile is not redispersed by diffusion) DMOS junction is similar to that using double diffusion, but the implant-only dopant profile is The difference is that it can include continuous implants with varying doses and energies, and therefore does not have to follow dopant profile characteristics based on the Gaussian distribution of the diffused junction. Such a device is referred to as a DMOS, where “D” refers to a double junction (source in the body in the drain) and not “D”, which means a double diffusion process. .

  Referring again to FIG. 1B, the equivalent circuit of the trench type DMOS 120 includes an idealized MOSFET 121 and a gated diode 122. The diode 122 represents a body-drain PN junction formed by the body region 103 and the drain region 102. Since the gate 105 overlaps the drain 102 and only the thin gate oxide underlayer 104 divides the two elements, the gate represents the field plate effect of the polysilicon gate 105 on this junction. Although the thin gate oxide layer 104 is protected from sharing a depletion layer with the adjacent body region 103 in its off state, the presence of the gate 105 is dependent on the breakdown voltage rating and avalanche of the trench DMOS 120. The joint avalanche can be adversely affected both in terms of where the process occurs.

This principle is illustrated in FIG. 1C, where a trench MOSFET 130 is shown without the source region to illustrate the principle of breakdown induced by a field plate. By applying a reverse bias _VDS to the junction between the body 103 and the epitaxial drain 102, carriers increase as shown by the impact ionization contour 131 located in the vicinity of the trench gate 105. The ionization rate is very high compared to the case where the trench gate 105 is not present, and has a different shape. The graph of the relationship between gated diode breakdown BV _DSS and gate oxide thickness shown in FIG. 1D shows that the oxide thickness can affect the avalanche value of a reverse-biased PN junction. Yes. In the case of the example shown in the figure, when the gate-source voltage V _GS is zero, ie when the gate 105 is tied to a P-type body, a thick gate oxide layer is an oxide layer as indicated by the region 140 of the graph. The effect of the thickness is avoided. However, if the oxide layer is thinner, the breakdown decreases in direct proportion to the oxide layer thickness, as evidenced by the region 141 of the graph. As indicated by the symbol, the decrease in the avalanche value in the region 141 is due to the (FPI) breakdown effect induced in the field plate.

Another way to show FPI breakdown is shown as a graph showing the relationship between junction breakdown and gate bias shown in FIG. 1E. In this configuration, a negative gate bias can exacerbate the breakdown voltage of the device when the source is biased to accumulate most of the carrier concentration in the body. As shown, the junction breakdown 142 is reduced by the presence of the trench plate field plate effect. Beginning with some negative gate bias, typically several voltages above the source voltage (ie VGS ≦ 0), curve 143 shows the occurrence of FPI breakdown. Due to the occurrence of this FPI breakdown, the BVD usually decreases in proportion to the gate voltage. Even so, the device of curve 143 shows minimal FPI effects because its breakdown remains at the maximum voltage when the gate-source voltage V _GS is zero. The different device curve 144 shows a stronger FPI effect, indicating a breakdown breakdown even when the gate-source voltage V _GS is zero. This curve 144 represents an example where the trench gate penetrates much deeper inside the body region or has a much thinner oxide layer than the device of curve 143. As can be clearly seen, the adverse effects of FPI breakdown become more dominant in the case of thin oxide layer devices. Thin oxide devices are commonly used for the operation of low voltage devices in battery powered applications and are therefore more susceptible to FPI related issues.

  One way to reduce the impact on gate breakdown is as described in US Pat. No. 5,072,266, entitled "Trench DMOS Power Transistor With Field-Shaping Body Profile And Three-Dimensional Geometry", granted to Bulucea et al. In this method, the bottom of the trench is electrostatically shielded using a deep junction having the same conductivity type as that of the body region. FIG. 2A shows a portion of a trench MOSFET 150 having a deep body region 153 diffused deeper than the bottom of the trench gate 155. Deep body region 153 has the same potential as body region 156, but generally has a higher dopant concentration. Regions 153 and 156 are both bonded at the surface of heavily doped contact region 157.

  The electrical characteristics of the trench MOSFET 150 are schematically shown in FIG. 2B, where the MOSFET 171 includes a gated diode 172. However, unlike the case of device 120 having a flat bottom body region of FIG. 1B, the gate of diode 172 with gate is directly connected to the gate of MOSFET 171, device 150 of FIG. The effect that can be best explained by the configuration in which the JFET 173 is connected between the actual gate and the gate representing the diode effect with the FIP gate is shown. When fully reverse biased, the depletion regions extending from adjacent deep body regions 153 will merge together to pinch off the field plate effect from the junction voltage (see shaded area in FIG. 2C). ). This FPI effect is greatly reduced and high breakdown is preserved.

  FIG. 2B shows the addition of a Zener diode 174 representing a PIN junction formed between the deep body region 153 and the heavily doped substrate 151. In the case of a high current avalanche, as shown in FIG. 2D, most of the current flows through the heavily doped region 153 rather than through the body region 156. The deep region 153 draws more current during avalanche because of its breakdown voltage (as indicated by the ionization profile) and series resistance (due to being more heavily doped than the body region 156). A flow joint is formed. The breakdown of the Zener diode 174 is lower than that of the gated diode 172. This is because the region 153 where the diode forms the anode is located closer to the substrate 151 than the shallow body 156, thereby reducing its PIN breakdown voltage. Therefore, since this breakdown occurs at a lower voltage than the body junction breakdown, the deep body region 153 clamps the maximum drain voltage to a lower value and raises that voltage to the point where field plate induced breakdown occurs. Not adding a second degree of protection. It is beneficial to avoid FPI breakdown. This is because the FPI breakdown is involved in the interface and surface of the semiconductor which is inherently less reliable than the bulk silicon avalanche breakdown. Note that the term “zena” does not represent a zener breakdown mechanism (a type of tunneling phenomenon), but simply represents the voltage clamping action of a diode.

  The deep body 153 can significantly improve the resistance of the trench MOSFET 150 in the avalanche, but it also gives a problematic limit to the on-state performance of the trench MOSFET 150. For example, FIG. 2E shows current flow in the on state, where the current flows vertically from the upper source 158 along the gate oxide underlayer 153 through the body region 156A and then through the bottom of the trench. It extends into the epitaxial layer 152.

  The current spread indicates that the entire cross section is not fully utilized by the current. Thus, the device is not operating at its theoretical minimum on-resistance. Further, the angle at which the current spreads (not more than about 45 degrees) is suppressed to a smaller angle by the penetration of the lateral diffusion of the deep body region 153. In fact, the epitaxial layer portions 177A and 177B immediately below the deep body region 153 do not pass any current, which contributes to a high resistance value.

The increase in on-resistance due to the deep body diode surrounding each trench gate 155 becomes a greater problem as the cell size decreases (ie, as the cell density increases). For example, in FIG. 2F, an increase in cell density should ideally increase the number of parallel transistors to reduce the overall resistance of a given area device. To avoid comparison of dissimilar regions of the device, the on-resistance RDS is often normalized by the area A, known as the intrinsic on-resistance value RDSA, whose unit is on-resistance × area (eg, mΩcm ² ). Expressed by a figure of merit. In region I (cell density less than about 12 M cells / in 2), as the cell density increases, the specific on-resistance decreases as expected. In region II where the cell density is higher than that, the effect of the deep body that regulates the current spread in the epitaxial layer causes an increase in the on-resistance value per cell, which is due to having more parallel conductive cells in the same area. It offsets the profits obtained. Limiting the current spread results in a constant specific on-resistance value, and thus a decrease in resistance due to an increase in cell density cannot be achieved. In region III (for example, the cell density is 24 M cells / in 2 or more), the on-resistance value starts to increase rapidly. This is the effect that occurs when the threshold voltage of the device is increased by the high concentration of the deep body beginning to adversely affect the channel concentration.

  FIG. 2G is a plan view of a closed cell array (in this case, a square) of the trench gate type MOSFET 180, and shows polysilicon filled in the trench region 181 and a mesa region (mountain shape region) 182 between the trenches. The deep body region 183 is disposed inside each mesa region 182. If the distance between the deep body region 183 and the trench region 181 is too close, the high concentration of the deep body region 183 adversely affects the channel concentration as described above. This effect may occur when the deep body region 183 is too large, or when the cell pitch is reduced and the deep body region 183 is not reduced together. The deep body region 183 must have a minimum size that will diffuse at least through the bottom of the trench. As the deep body region 183 becomes smaller than its depth, it begins to show a lack of diffusion effect (in this case the surface concentration along the entire surface is affected by both lateral and vertical diffusion). The effect of insufficient diffusion is that the deep body junction depth is shallower than in other regions and does not reach lower than the bottom of the trench, and the benefits gained from the presence of the deep body region are lost.

  Another method described in US Pat. No. 6,140,678 entitled “Trench-Gated Power MOSFET with Protective Diode” granted to W. Grabowskim, R. Williams, M. Darwish uses a deep body region for each mesa region. Instead, it is instead limited to a portion of the device's mesa area (typically 1/16 of all active device cells). In FIG. 3A, a cross-sectional view of the device shows an array of trenches with a gate oxide underlayer 204 formed in an epitaxial layer 202 on a heavily doped substrate 201 and a buried trench polysilicon 205. A body diffusion region (collectively 203) is formed in each mesa region including active channel portions 203A, 203B, 203C, 203E, and 203F between the trenches. The body region 203D has no source region but a deep body region 209 having a width ydP + that can extend entirely between two adjacent trenches (indicated by the sign dP + in the example of the N channel shown in the figure). Is formed in a diode-only cell.

  Device 200 is similar to device 150 of FIG. 2A, but the operation of device 200 is substantially different, as schematically illustrated in FIG. 3B as an equivalent circuit diagram. In FIG. 3B, MOSFET 220 and Zener diode 222 in parallel with it have different areas. Each area is represented by the symbol “1 / A” for the diode and “(n−1) / A” for the MOSFET. These symbols indicate that in the active area A (including n cells), one cell constitutes a diode cell and the other (n−1) cells have active transistors. Yes. The active transistor also includes an integral body-drain PN junction diode 221 that is gated by the trench gate electrode. The benefit of the deep body region charge sharing effect (JFET effect) that minimizes gated diode breakdown in the device 150 of FIG. 2A is lost in the 1 / n design. This is because there is no deep body region in or near each cell. Without the charge sharing effect, device protection would rely entirely on sparse but evenly spaced zener diodes. Note that since there is no charge sharing effect, the Zener breakdown voltage of diode 222 will be lower than the breakdown voltage of gated diode 221, which provides some protection.

  In an “n” cell device, one cell per n cells (1 / n cell) has a protective Zener diode clamp 222 and the remaining cells have active devices. The layout is best shown in the top view of the closed cell array vertical trench gate MOSFET in FIG. 3C. In such a design, the trench gate array 231 includes an array of 16 repeated cells, 15 of which have active devices 234 and the remaining one diode cell 232 has a deep body 233. Have. The entire array is repeatedly arranged at predetermined intervals.

  In principle, the diode clamp 222 formed by the deep body opening 233 limits the maximum voltage applied to the device. The contact and junction regions of the Zener diode must be large enough to allow avalanche current to flow without damage. In practice, however, the deep body region dimension ydp + must be generally smaller than the mesa region 232, but the lateral diffusion of the deep junctions proceeds above the adjacent active cells and impairs their conducting ability.

  FIG. 3D shows an operation during 1 / n design avalanche, that is, a state in which a current flows while maintaining a high voltage and a strong electric field at a silicon avalanche point. In proper operation, the deep body region 209 maintains the strongest electric field in the device, the ionization profile shows breakdown, and the resulting current is generated at the bottom of the deep body diffusion region away from the trench gate oxide layer 204. . In order to maintain a low level of ionization in the vicinity of the trench gate (under the body 203C in the vicinity of the trench), the avalanche breakdown from the deep body diode 209 to the epitaxial layer 202A causes the body 203C to be gated by the trench gate. From the breakdown to the epitaxial layer 202 must be substantially lower.

This principle is illustrated in the graph of FIG. 3E, where the component diode breakdown voltage BV is shown as a function of the gate oxide underlayer thickness Xox. The flat body junction breakdown BV (PB) reduces the avalanche voltage indicated by line 242 until the gate oxide underlayer is thin enough to induce the field plate induced breakdown indicated by line 243. Have. Avalanche breakdown voltage BV _Z of deep body zener diode clamp showing the line 240, so as not to cause breakdown in the vicinity of the trench gate, intentionally designed to be lower than the breakdown voltage of the body diode (line 242) Has been. In order to allow manufacturing changes such that the FPI breakdown voltage does not become lower than the Zener voltage, it is desirable that the voltage margin be 4V to 10V.

When the FPI breakdown falls below the zener voltage BV _Z on line 240, the device is no longer protected. This problem occurs when the epitaxial dopant concentration in the epitaxial layer is high and the gate oxide underlayer is thinner. That is, it occurs when the conditions are necessary to optimize the low voltage trench device to minimize the on-resistance. This effect is illustrated by the graph of FIG. 3F. FIG. 3F shows that the transition from the avalanche breakdown of the PN junction to the FPI breakdown 251 depends on the epitaxial concentration when the epitaxial concentration is high. Zener voltage BV _Z is hardly concentration dependence in the region 253, also Zener diode is in the PIN reach through avalanche. That is, the depletion region in the avalanche is in a state where the epitaxial layer is completely depleted (more specifically, the state where the net epitaxial layer exists only between the bottom of the deep body junction and the top of the heavily doped substrate). . At higher dopant concentrations, the epitaxial layer is no longer depleted and the diode will exhibit the classic PN doping dependence of region 254. But before that happens, the FPI breakdown at the body junction drops to a voltage below BV _Z and the device is no longer protected.

  In conclusion, the 1 / n clamping scheme has limited clamping capability and ability to provide protection against FPI breakdown in low voltage devices. For example, to protect a 30 rated MOSFET with a thin gate oxide underlayer, the Zener must be designed to break down at 34V. A gated body diode must use a very low concentration of epitaxial doping that breaks down above 40V. In short, a 40V MOSFET can only be used to operate safely at 30V. The extra 10V avalanche protection band means that the device has an on-resistance of 40V devices instead of 30 devices. Although this method is not as severe as the device 150 of FIG. 2A, it still has a higher on-resistance than the desired on-resistance.

  A method for reducing the impact of the FPI breakdown problem is described in US Pat. No. 6,291,298 to Williams et al. As shown in FIG. 4A, the trench-gate vertical power MOSFET 300 shown in cross-section includes buried polysilicon gates 304A-304C (collectively referred to as gates 304) and thin sidewall gate oxide underlayers 310A-310C (collectively). And a thick oxide region 303A-303C (collectively referred to as a thick bottom acid underlayer 303) located at the bottom of each trench. The thick bottom acid underlayer (TBOX) has a typical thickness on the order of 2 kÅ, greatly reducing the effect of the trench gate on the junction formed by the body regions 305A-305D (collectively referred to as the body 305), Reduces field plate induced impact ionization, protects the oxide layer from degradation due to carrier injection at the bottom of the trench, and reduces capacitance at the drain-gate overlap. The effect of the sidewall gate oxide underlayer 310 on the PN junction breakdown from the thickness body 305 to the epitaxial layer 302 is particularly important when the body of the gate polysilicon 304 overlaps the body 305 only slightly beyond the body 305. The presence of region 303 is significantly reduced. The best way to form the body region has been found to be using high energy ion implantation and an as-implanted dopant profile without redispersion due to thermal diffusion.

  The device shown comprises a uniform cell with source regions 306A-306D shorted to metal 311, and a three-dimensional protruding portion of the device (not shown in the particular cross section of FIG. 4A). 1 includes a contact portion to the body region 305 to which the metal 311 is connected. Each trench is insulated from the source metal by upper dielectrics 308A-308C. A schematic equivalent circuit diagram of device 300 is shown in FIG. 4B, where MOSFET 320 is connected in parallel with body-drain junction 321. There is no zener diode clamp and virtually no field plate induced breakdown mechanism.

  FIG. 4C illustrates the advantage of a thick bottom oxide layer in a continuous avalanche that does not require a voltage clamp. When the trench device is biased to an avalanche state (shown in simplified form as a gated diode in FIG. 4C), an avalanche occurs at the bottom of the trench opposite the TBOX region 303B, as shown by the ionization profile, It does not occur in the vicinity of the overlapping portion of the thin gate oxide layer 310B beyond the body region 305C. In this structure, although the junction formed by the body region 305B and the epitaxial layer 302 of the opposite conductivity type and the gate electrode 304B are close to each other, only a minimum amount of hot carriers is formed on the thin side gate oxide layer 310B. Is not injected. The reliability of hot carriers in such devices is significantly improved over unclamped devices with a thin oxide layer throughout the trench lining. Furthermore, the breakdown of such devices is minimally dependent on the thickness of the gate acid underlayer 304B. However, it should be noted that a lateral current during avalanche may be generated in body region 305 (body region 305C in FIG. 4C). This lateral current is less desirable than a pure vertical current and is an important issue as described below.

  FIG. 5A is a diagram illustrating the phenomenon of hot carrier trapping and oxide layer degradation in a conventional trench gated diode 340 (or similar trench gated MOSFET) with a uniform gate oxide underlayer. The presence of the gate electrode 346 induces FPI carrier generation at the reverse bias junction between the bodies 343A, 343B and the epitaxial layer 342. Electron pairs are generated by impact ionization, including the trench curvature effect that locally enhances the electric field in region 350. Even at voltages below the avalanche voltage, these carriers are accelerated by the local high electric field at the reverse-biased junction, and electrons are collected towards the contact on the backside of the wafer, and the holes are negatively biased. Accelerated toward the gate electrode. If the holes have sufficient energy, the holes may overcome the energy barrier at the silicon oxide interface and enter the oxide layer 345 by themselves, and the thin gate acid lower layer 345 may be gradually charged and deteriorated. .

  In contrast, the trench gate type device 360 with the TBOX region 361 shown in FIG. 5B exhibits hot carrier generation induced mainly by impact ionization in the region 367, which does not substantially affect the reliability of the device. This results in hot hole injection into the thick oxide layer 361. Only hot carrier generation in the region 368 in the vicinity of the thin sidewall gate oxide underlayer 362 can compromise the conductive properties and long-term reliability of the device 360. Since this defect is a statistical process and a statistical phenomenon, if the cross-sectional area of the region 368 is reduced, the charge injection is minimized, and in the worst case, only a very time-consuming deterioration occurs. By setting the injection to such a low level, it is possible to ensure the reliability of operation for 20 years or more and to achieve the product life. Thus, while the thick bottom acid underlayer 361 prevents hot carrier-induced degradation, the thick bottom acid underlayer 361 does not completely prevent the double injection effect that can occur under high current avalanche conditions.

This double injection effect is illustrated in FIG. 6A. In this figure, a trench gated vertical power MOSFET 380 with a thin gate is replaced by the previously shown gated diode structure (gate 385, thin gate oxide underlayer 384, body regions 383A, 383B, and heavily doped body contact region 386A. 386B), as well as source regions 387A, 387B of opposite conductivity types (shown as N + regions). As illustrated by the current line, the pre-avalanche current from impact ionization flows through the electrons in the N-type epitaxial layer 382 and the body region 383B laterally and into the body contact P + region 383B. And holes in the body region. Assuming that body region 383B is not relatively depleted during such operation, the flow of holes in P-type body region 383B constitutes the majority of carrier conduction. As shown in FIG. 6B, hole conduction in the P-type material is caused by the voltage drop associated with the parasitic resistance rb and the voltage of the body region 383C to a voltage V _B (y) higher than the source-body ground potential (0V). Showing rise. Thus, the gated diode 391 generates an FPI ionization current, thereby removing the body voltage bias. When the voltage V _B (y) becomes higher than the potential of the N + source 387C by 0.6V (ie, forward bias diode voltage) or more, the N + source 387C starts injecting electrons into the thin P-type body region 383C. These injected electrons increase the collector current of a parasitic NPN bipolar transistor having an N + source region 387C as an emitter, a P-type body 383C as a base, and an N-type epitaxial layer 382 as a collector, and thus doubly It is called injection. This flow of electrons flows in parallel with the gate current, but this gives positive feedback, and a potential runaway state occurs particularly at high temperatures. The positive feedback of NPN parasitic transistors worsens with increasing temperature, causing device overheating due to local overheating, hot spots, and increased local current density.

As a solution to the double injection problem, the length of the N + source region 387C is shortened to keep the resistance rb small, and the concentration of the body region 383C is made as high as possible (predetermined target threshold voltage and gate acid). Under the condition of the lower layer thickness). The principle of this good source-body short circuit is shown as a schematic equivalent circuit diagram in FIG. 6C. In this figure, MOSFET 400 has a source-body shorted contact having a drain-body PN diode 401 (which may have an FPI effect in an avalanche), a parasitic NPN transistor 403, and a parasitic base resistance 402 of magnitude rb. If this short is complete and ideal, the resistance rb will be zero and the NPN transistor 403 will not turn on, avoiding electron injection from the N + source, and thus the current _ID and drain-source voltage V in FIG. 5D. _The risk of voltage snapback shown in the relationship with _DS can be avoided.

  It is particularly difficult to reduce the resistance rb in a trench gate type power MOSFET having a narrow mesa that does not have sufficient margin to contact the P + body contact along the entire length of the body region. In the device 500 shown in cross section in FIGS. 6E and 6F, the resistance rb to the P + contact 505A may not be negligible, especially for the current flowing in the P-type body 503 under the N + source 504A. The source must be configured to be interrupted to allow room for contact with the P + contact 505A, which allows the source circumference (low on-resistance) and body contact P + (resistance rb An undesirable trade-off relationship arises between low and improved snapback.

  Thus, in summary, double implantation can reduce the off-state cutoff characteristics of a trench gated power MOSFET to a voltage even lower than that resulting from field plate induced (FPI) impact ionization and FPI avalanche current. Without further voltage clamping, the high avalanche current is shunted away from the trench edge (to avoid lateral current in the body region) to suppress snapback induced by double injection. It is difficult. A method using a deep body region as realized in the device 150 of FIG. 2A and a distributed (1 / n-type) diode clamp as realized in the device 200 of FIG. 3A suppress double injection. However, it increases the on-resistance of the device. This high on-resistance places a severe limit on the cell density of device 150, which requires a deep body in each cell. The increase in resistance at the distributed clamp is also not negligible and requires at least 10V design grace (which can result in a 20-40% increase in on-resistance) to avoid FPI breakdown. On the other hand, it is still not possible to completely remove the FPI impact ionization current.

  As shown in the cross-sectional view of the device 550 of FIG. 7, the 1 / n clamp method is used, but the device 550 is sufficiently protected when a shallow heavily doped body 554 or a shallow zener voltage clamp is used at the same time. Can not do it. This is because the trench gates 556A, 556B are deeper than the diode junction clamp, so that they first break down. As an example, non-targeting in device manufacturing tends to cause avalanche on one side of the trench, such as regions 558 and 559, rather than on both sides, making double injections likely due to high local ionization currents. Become.

  A thick bottom acid underlayer reduces the FPI impact ionization current, increases avalanche generation, and increases the breakdown voltage of the device, but the thick bottom acid underlayer itself, in particular, causes the device to enter high current breakdown operation. When driven in such a manner (a general condition in the use of a power supply circuit having an inductive load), it is not guaranteed to prevent the occurrence of double injection.

  A method available to clamp the voltage (and bypass the avalanche current) to avoid snapback in trench gated power MOSFETs results in high on-resistance and impact ionization from thin gate field plate inductive (FPI) effects The methods available to reduce the seldom prevent double injection and snapback. What is needed is a device that can clamp or bypass avalanche current and avoid (at least minimize) FPI impact ionization (even under a thin gate acid underlayer) without excessively increasing resistance to the on state. .

According to one aspect of the present invention, a trench gate type MOSFET is
An epitaxial layer on a substrate of the same conductivity type;
A trench including a thick bottom acid underlayer, under a sidewall gate acid, and a conductive gate;
A body region of opposite conductivity type shallower than the gate;
A zener clamp region that is more heavily doped than the body region and deep but shallower than the trench. The Zener junction clamps the drain-source voltage below the FPI breakdown of the body junction near the trench, but the Zener junction shallower than the trench avoids excessive reduction of the maximum drain-source voltage. .

  One particular embodiment of the invention is a semiconductor device having a gate structure in a trench in the substrate. In each of the trenches, the gate structure is electrically conductive (eg, poly-silicone) surrounded by an insulating material such as silicon dioxide having a first thickness on the sidewalls of the trench and a second thickness on the bottom of the trench. Silicon or silicide) gate. The first thickness is the thickness of the gate acid underlayer, and the second thickness is the thickness of the bottom acid underlayer that is thicker than the first thickness. A first region of second conductivity type (eg, a body region) is adjacent to at least one of the trenches and extends into the substrate to a first depth. A second region of the second conductivity type (eg, a Zener clamp region) is in electrical contact with the first region and extends to a second depth deeper than the first depth and shallower than the trench. Yes. This conductive gate usually extends to a depth deeper than the first depth and shallower than the second depth.

  A third region of the first conductivity type (eg, a source region) is located on the body region and is adjacent to the gate and the gate oxide layer, and the voltage on the conductive gate is the third region. The current flowing from the first region to the lower portion of the substrate is controlled. This current generally flows from the third region through the first region and through the epitaxial layer to the highly doped semiconductor substrate.

  The structure of the substrate can be altered to control device characteristics. Typically, the substrate is a first semiconductor layer (for example, an epitaxial layer), a semiconductor substrate that is located below the first semiconductor layer and is doped at a higher concentration than the first semiconductor layer, and the first semiconductor layer And a trench provided therein. The first layer can be provided with a continuous concentration gradient in which the dopant concentration of the first conductivity type becomes higher as the dopant concentration becomes deeper in the layer. Also, a series of implantations having different implantation depths and dopant concentrations can increase the dopant concentration of the same conductivity type as the epitaxial layer as the depth increases. Alternatively, the substrate may have a first semiconductor layer and a second semiconductor layer doped thereon at a lower concentration than the first semiconductor layer. In this embodiment, the first region or body region forms a junction with the second semiconductor layer, and the second region or Zener clamp region forms a junction with the first semiconductor layer.

  The zener clamp region has continuous implants with different depths or is provided by diffusion to a desired depth. Usually, however, the Zener clamp as-implanted structure provides excellent joint profile and process repeatability. In one form, the Zener clamp region extends to completely fill the distance between adjacent trenches at selected locations, and further extends to a set of adjacent mesas between the trenches. obtain. Alternatively, a Zener clamp region may be included in the selected active transistor cell.

  A gate structure electrically connected to the gate structure of the trench may be located on a portion of the substrate that includes at least a portion of the body region and / or the Zener clamp. More particularly, the body and / or clamp region may be formed before forming the gate bus, or may be formed by implantation through the gate bus after forming the gate bus.

Another specific embodiment of the present invention is a process for manufacturing a semiconductor device such as a trench gate type MOSFET. This process
(A) forming a plurality of trenches in a first conductivity type substrate;
(B) depositing a thick oxide layer on the bottom of the trench;
(C) forming a gate acid underlayer on the trench sidewall;
(D) filling the trench with a conductive material;
(E) A process of forming a second conductivity type body region on the substrate in a region corresponding to one or more mesas (mountain shape regions) between the trenches, wherein the body region has a first depth. The process,
(F) forming a clamp region of the second conductivity type in a region corresponding to one or more mesas between the trenches, wherein the clamp region is deeper than the first depth and the trench The process having a shallower second depth; and
(G) forming an active region of the first conductivity type on the body region;
(H) providing an electrical connection to the conductive material, the active region, and the substrate. In another process flow, the steps (a) to (d) are performed before or after the steps (e) and (f).

  This process can use another process flow to form the gate bus. In one process flow, a conductive material is patterned to form a gate bus located on the substrate. The body and / or clamp region may be formed by implanting a dopant of the second conductivity type through the gate bus. Alternatively, the conductive material is removed from the surface of the substrate (eg, by an etch back or CMP process), and then the body region and clamp region are formed before forming the gate bus. DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. In different drawings, similar or identical elements are given the same reference numerals.

  FIG. 8 is a cross-sectional view of a trench gated MOSFET device 570, according to one embodiment of the present invention. Device 570 has an array of trenches with embedded polysilicon gates 576 and a thick bottom oxide layer 577A, 577B, 577C formed on an epitaxial layer 572 located on a heavily doped substrate 571 of the same conductivity type. . In a silicon mesa region (a plateau-shaped region) between trenches, a body 573 (specifically, bodies 573A to 573D) into which impurities of a conductivity type different from that of the epitaxial layer 572 are diffused or implanted is embedded in a polysilicon gate 576. The depth is slightly shallower than the depth of the bottom. The body 573 has the energy and dose to form any dopant profile (including box-shaped or Gaussian profile) such that thermal diffusion after ion implantation causes little or no dopant redispersion. It can be formed by using continuous ion implantation performed by changing. These as-implanted profiles are profiles consistent with low thermal budgets and low temperature processes.

  A number of active transistor cells or stripes are formed in the silicon mesa between the trenches. In FIG. 8, each active cell has a body region 573A, 573B, or 573D and a source region 574A, 574B, or 574C. The contacts to the body regions 573A to 573D are formed three-dimensionally, that is, in the Z-axis direction not shown in the cross section of FIG.

In FIG. 8, the active source regions 574A, 574B, and 574C are labeled “N +”, and the epitaxial layer 572 is labeled “Nepi” to indicate an N-type doping region. Has been. The body region 573 is labeled with “P _B ” to indicate that the body is a P-type doping region. By reversing the conductivity type, a P-channel device can be formed.

  In the mesa that includes the body region 573C, a more heavily doped region 578 and / or a deep junction that includes a dopant of the same conductivity type as the body region 573C is formed and acts as a local Zener diode clamp. The Zener diode formed at the junction between the region 578 and the epitaxial layer 572 is designed to avalanche break down at a lower voltage than the junction between the body 573 and the epitaxial layer 572, Thus, the Zener diode formed by region 578 clamps the source-drain voltage of device 570. To achieve clamping to a voltage lower than the FPI breakdown of the trench gated body junction, the zener implant region 578 (here labeled PZ) is deeper than the bottom of the buried polysilicon gate 576. Although it should have depth, the junction should be shallower than the bottom of the trench to avoid degradation of breakdown. Thus, the Zener implant region 578 should be deeper than the polysilicon gate 576 but shallower than the trench, and this method is possible only when thick bottom oxide layers 577A, 577B, and 577C are present. Thus, the combination of a shallow voltage clamp and a thick bottom oxide layer provides a particularly advantageous effect that cannot be achieved with either element itself.

  To complete the device 570, each trench is covered with an upper oxide layer 580A, 580B, 580C to prevent the buried gate 576 from shorting to a thick aluminum, copper, silicon source metallization. Further, a TiN or silicide barrier layer 581 is used to form metal 582, source regions 574A, 574B, and 574C, and body-contact region 575 (all of these elements are not shown in the cross-sectional view of FIG. Can be provided in variously modified forms in the Z-axis direction).

  An equivalent circuit diagram of the device 570 of FIG. 8 is shown in FIG. 9A. In FIG. 9A, MOSFET 600 has its own body-drain diode 601 and zener diode clamp 602. Body-drain diode 601 has no or little FPI degradation (since gate 576 overlaps only slightly beyond the junction between body 573 and epitaxial layer 572 in FIG. 8). BVj. The breakdown BVz of the Zener diode 602 is programmed for that purpose by implantation and diffusion only, or by a continuously implanted epitaxial layer, so that the thick bottom oxide layer shields the gate oxide underlayer from hot carrier degradation. The voltage may be a little lower than the voltage.

This principle is illustrated in the graph of FIG. 9B showing the relationship between BV _DSS and dopant concentration Nepi. The body-epitaxial junction exhibits two breakdown mechanisms. One is a junction avalanche of size BV _{j (Pbody)} indicated by line 610, and the other is a very high epitaxial concentration, a very thin gate oxide underlayer, and a statistical process. FPI avalanche BV _FPI , indicated by line segment 611, which only occurs when the variation reaches the trench gate well beyond the body junction (ie, is over-etched). Under nominal conditions of epitaxial doping, gate oxide underlayer thickness, and trench depth, no FPI mechanism can occur for a device with a TBOX formed. In either case, when using a trench gate filled with TBOX, the start of FPI breakdown occurs at a very high voltage when compared to a standard trench gate MOSFET. This voltage improvement can be as much as 10V.

FIG. 9B also shows that the Zener diode clamp design has a breakdown value BV _Z indicated by line 612, which under most conditions is the breakdown BV of the body junction. _It is lower than _{j (Pbody)} . Since it has an implanted Zener anode that is deeper than the body region and / or has a higher dopant concentration, the Zener diode clamp has the point 613 (the FPI effect lowers the breakdown voltage than the breakdown at the body junction). It will have a breakdown voltage that is lower than the body junction breakdown voltage for virtually any epitaxial concentration up to the point). The occurrence of FPI breakdown will occur at a very high voltage (if it occurs), and BV _Z is inherently lower than BV _{j (Pbody)} , and both draw parallel lines to changes in epitaxial concentration. The voltage protection band between the breakdown voltages can be minimum, that is, about several volts.

  Thus, unlike some conventional trench gate MOSFETs that employ a high voltage margin design to ensure a clamp to a very low voltage that prevents FPI breakdown, this new device The zener clamped TBOX trench MOSFET maintains this condition naturally. By substantially eliminating the FPI condition using a gate with a TBOX, both the Zener and body junction breakdown voltages will draw substantially parallel lines as the epitaxial concentration changes, which results in higher epitaxial It is possible to use a concentration and a small protection voltage band. Therefore, the trench gate type MOSFET formed according to one aspect of the present invention exhibits lower on-resistance than the conventional trench gate type MOSFET, and the performance caused by field plate induced breakdown, which is a problem in a thin gate device. A decrease in reliability can be avoided.

  The magnitude of the on-resistance improvement obtained is proportional to the high concentration of epitaxial doping for any voltage device. Although this principle can be applied to any voltage device, the impact of voltage overspec design is even more negligible in low voltage devices (each voltage value device is in a very competitive market) It becomes a problem that can not be. For devices below 50V, the improvement using this new design and process is roughly proportional to voltage. For example, a thin gate 30V device formed in accordance with the present invention is designed with a nominal breakdown of 33V (this voltage still avoids FPI breakdown). In contrast, to prevent FPI breakdown in some conventional devices, a lower concentration of epitaxial doping, which is targeted at approximately 43V, is required. When comparing the 33V epitaxial layer and the 43V epitaxial layer, the improvement in on-resistance is approximately 33/44, or a decrease of about 25%. Since both devices in this comparison are clamped to 33V to ensure reliability, the conventional device is 30V despite its low doped epitaxial layer and proportionally high on-resistance. It can only be sold as a rated MOSFET.

FIG. 9C shows the biasing and operation of a voltage clamped TBOX trench gated MOSFET according to this design, shown as a cross-sectional view without the source region. Device 620 has an epitaxial layer 622 grown on a heavily doped substrate 621 (both elements are N-type in this example). The trench in the epitaxial layer 622 includes a polysilicon gate electrode 627, a thin gate oxide layer sidewall 626, and a thick bottom acid underlayer (TBOX) region 625. Two mesa regions adjacent to the trench have (P _B ) P-type bodies 623A, 623B and heavily doped P + contact regions 628A, 628B, respectively, one of the mesa regions being body regions 623A and 623B. It includes a PZ Zener diode anode region 624 that is more concentrated and has a depth that is the same as or deeper than the body regions 623A and 623B, and preferably shallower than the bottom of the trench and the deepest portion of the TBOX oxide layer 625.

  As shown in FIG. 9C, when an external power source biases device 620 to its off state, the strongest electric field is generated along the junction between PZ region 624 and N-type epitaxial layer 622, particularly along the region near the trench. Impact ionization at point 630, when it occurs, injects hot carriers into the thick oxide layer 625 that is remote from the thin sidewall acid underlayer 626. The ionization rate of the region adjacent to the thin sidewall gate underlayer 626 of the PN junction of the body 623A and the epitaxial layer 622 is reduced by several orders of magnitude, and thus the voltage clamp formed by this embodiment of the invention. It can be seen that the TBOX gate structure is protected.

  Accordingly, preferred embodiments of the present invention are designed so that the breakdown of the Zener diode clamp is lower than the body junction for any gate oxide underlayer thickness, deeper than the body but shallower than the bottom of the trench. A trench gate type MOSFET having a Zener clamp implant (PZ region) and a thick body oxide trench gate.

  Referring to FIG. 8 again, the N + source regions 574A, 574B, and 574C exist only in the mesa regions including the body regions 573A, 573B, and 573D, and do not exist in the body region 573C in which the PZ Zener node 578 is integrated. Please be careful. Instead, only the P + contact implantation part 575 is formed in the body region 575. Therefore, (as in other preferred embodiments of the present invention) the P-type Zener implant region 578 is a mesa region (where the source (N +) implant 574 is not locally present and the P + body contact region 575 is in contact). Further, it should be formed only in a local portion of the stripe-type mesa region. By avoiding the presence of a combination of N + source 574 and PZ region 578 in the vicinity of the same mesa, the zener clamp region 578 of the device 570 (the region forced to generate avalanche) is parasitic. Since there is no N + region that becomes the emitter of the bipolar NPI transistor, there is no risk of the aforementioned double injection, parasitic NPN transistor being turned on, and snapback breakdown problems.

  10A and 10B show two variations 650 and 690 of voltage clamped TBOX trench gate MOSFET designs for different PZ conditions. In FIG. 10A, the PZ Zener region 654 is slightly shallower than the body 653B. In order to ensure that breakdown is caused by the Zener implant 654, the dopant concentration in the Zener region 654 must be at least 40% higher than the dopant concentration in the body region 653B, or a clamp benefit can be obtained. Absent. Such a structure is still affected by some hot carrier injection in the thin gate 656 adjacent to the TZ Zener region 654, but the Zener injection region 654 is formed only where the P + contact region 670 is present. The damage caused by hot carriers does not affect the characteristics of the active cell and hence the MOSFET. Similarly, when the N + region 659A or 659B does not exist on the PZ Zener region 654, double injection or snapback cannot occur in the region where the avalanche occurs.

  In FIG. 10B, zener region 694 of device 690 is implanted (or diffused) deeper than the bottom of thick bottom acid underlayer 695A, 695B. This design is inferior in on resistance than the preferred embodiment of FIG. 8 because the deep Zener region 694 reduces the breakdown voltage of the device 690 without reducing the on resistance. Reduced breakdown of device 690 is a reach-through (PIN) break between the bottom of PZ Zener region 694 and the top of N + substrate 691 (where epitaxial layer 692 is fully depleted in the off state). It is due to down.

  The structure of device 690 is similar to device 200 of FIG. 3A, but the operation of device 690 is substantially different. In the conventional device 200, a thin gate acid underlayer 204 provides field enhancement, ionization and reduced breakdown induced in the field plate. By reducing the breakdown voltage of the Zener clamp diode (under all operating and process conditions) to a voltage lower than the smallest possible FPI breakdown, the FPI breakdown of the device 200 can be avoided. Even if this is achieved, some hot carriers will still occur in the vicinity of the gate 205. The maximum voltage applied to device 200, ie its breakdown voltage, also sets the ionization state in the vicinity of gate 205, but this ionization state still depends on the thickness of the gate acid underlayer.

  In device 690 of FIG. 10B, TBOXs 695A and 695B substantially eliminate current generated at the FPI in the vicinity of gates 697A, 697B, even during avalanche. Therefore, the FPI ionization and the Zener clamp voltage are completely disconnected. In such devices, it is virtually impossible to force the device into field plate induced failure mode because the zener absorbs most of the avalanche energy well before the region in the vicinity of the gate receives the electric field. Become. Thus, device 690 has a lower breakdown than device 670 of FIG. 8, and device 690 provides a very low resistance voltage clamp from its deeper PZ Zener clamp 694. Also, the doping profile of the device 200 of FIG. 3A will depict a Gaussian distribution as a product of the manufacturing process. In the case of reach-through clamp diodes, the box-shaped doping profile produces a more reproducible breakdown than the continuous concentration gradient profile with large variations in deep diffused junctions. Using a low thermal budget process that does not result in dopant redispersion, the sustained state dopant profile of the PZ Zener region 694 can be formed using a continuous implant that creates a junction of any shape. By shaping its concentration profile, in particular the deepest part of the PZ zener region 694, by injecting a lower dose into the deeper junction to form, for example, a stepped box-shaped profile with three different concentrations. Loss in breakdown voltage from can be minimized.

  By changing the depth of the PZ Zener region (as shown in the device cross-sectional views of FIGS. 10A, 8 and 10B), the protection band, or epitaxial, in the breakdown voltage clamp of the TBOX trench gated MOSFET The ΔBV, which is the difference between the body breakdown voltage 710 and the epitaxial-zener breakdown voltage 711, can be changed parameterically. As shown in the graph of FIG. 10C, the relationship between ΔBV and device behavior can be divided into three cases depending on the relative depths of the body, trench, and zener regions.

  The first case is illustrated by the device in FIG. 10A, where the Zener region 654 is shallower than the body 653, and the breakdown voltage drop is only caused by the absence of depletion regions on both sides extending to the diode. Thus, the clamp acts to divert the avalanche current away from other regions due to its high doping (ie, low series resistance), and the magnitude of the voltage clamp ΔBV is reduced.

  In the second case, the preferred embodiment of the present invention (see the cross-sectional view of FIG. 8) has a zener junction 574 that is deeper than the body 573 and shallower than the bottom of the trench and the thick bottom acid underlayer 577. By combining a Zener clamp and a thick bottom oxide layer, in this second case, a moderate voltage clamp ΔBV provides excellent protection for the MOSFET. As such, Zener junction 578 clamps the voltage and TBOX 577 provides protection against reduced FPI breakdown so that body diode 573, particularly the gate (in contact with body 573 and sidewall gate oxide layer 579) gate. In the vicinity of 576, the breakdown voltage is maintained higher than the zener breakdown voltage.

  The junction avalanche breakdown mechanism in the first and second cases is the standard PN junction (in one-dimensional approximation, the PN junction exhibits a triangular electric field with a peak at the body-epitaxial junction. ), Which depends mainly on the doping concentration (both the Zener region and the epitaxial material), but is not significantly affected by variations in the thickness of the epitaxial layer corresponding to nominal manufacturing differences.

  The third case is when the zener region depth is deeper than both the body junction and bottom of the trench (as shown in device 690 of FIG. 10B), which provides a better clamping effect. However, there is a trade-off relationship between lower breakdown and / or higher on-resistance. Since the deep zener clamp 694 acts as a low impedance clamp during the avalanche, virtually all avalanche current is diverted away from the active cells 693A and 693B. This reduces the avalanche voltage, that is, device 690 has a lower voltage rating for a given on-resistance, or device 690 uses a thicker and / or lightly doped epitaxial layer. This means that the target value must be changed (that is, the on-resistance of the device is increased).

  Under the third condition, not only the voltage difference ΔBV is increased, but also the physical avalanche mechanism of the Zener diode is different (as compared to the first and second cases). A “net” epitaxial layer between the bottom of the zener region and the top of the N + substrate for an optimal epitaxial layer thickness (such that the epitaxial layer is as thin as possible and meets the target breakdown voltage requirements) In the third case, it will be completely depleted before reaching the avalanche state (ie, applying an electric field will sweep all free carriers in the epitaxial region). Such a diode is said to operate with a “reach-through” breakdown reflecting that the fully depleted state of the epitaxial layer reaches the substrate. Since the epitaxial layer is completely depleted, the concentration of the epitaxial layer has little effect on the device, and the epitaxial region behaves like an electrically induced intrinsic semiconductor layer in the off state. The breakdown voltage of such a diode (referred to as a PIN diode) depends only on the thickness of the net epitaxial layer of the true semiconductor (ie, the “I” portion of the PIN diode) and depends on the doping concentration of the epitaxial layer. Not. Therefore, in the third case, the breakdown voltage with respect to a predetermined on-resistance is lowered, and is greatly affected by the variation in the thickness of the epitaxial layer.

  Referring now again to FIG. 10C, the nominal design of the device should be selected to allow for expected variations in process conditions. The largest variation in such zener-clamped TBOX trench gate vertical MOSFETs is relative to the bottom of the polysilicon gate embedded in the trench, particularly in the body and zener junction depth, in the epitaxial and trench etch steps. Occurs with respect to the depth of the image. However, when the low thermal budget process is used, the reproducibility of the implantation state maintaining type zener region and the continuous body implantation becomes very high, and the trench depth becomes the first variable to be controlled.

  In the preferred embodiment of the present invention, the target condition 712 is selected to be nominally within the condition of the second case, and therefore, in the first case (using less protection) due to the effects of process variations. In the third case of a deep Zener (in which the on-resistance and breakdown characteristics of the device are inferior) of the deep Zener, the manufacturing condition should be prevented from entering statistically. Maintaining device fabrication in the second case by providing a 3k thick thick bottom oxide layer, using high energy continuous implantation, and performing dry silicon trench etching is possible with today's processing equipment. Is possible. As such, a trench gate MOSFET with a thin gate oxide layer with the highest reliability with low on-resistance, high breakdown voltage, and good avalanche energy absorption capability is used as a device according to the present invention. It is feasible.

  FIG. 11 is a three-dimensional cutaway view of a voltage clamped TBOX trench gate MOSFET 740 similar to the device shown in FIG. Device 740 includes an array of cellular or striped trench gates, each trench gate formed on top of buried polysilicon gate 745, gate oxide sidewall 744, and N + substrate 741. A thick bottom oxide layer TBOX 743 formed on N-type epitaxial layer 742 is included. The top metal mask or surface contact mask or dielectric feature on the silicon surface is not shown in FIG.

  P-type body region 746 (746 A, 746 B, 746 C) is formed inside epitaxial layer 742 having a depth shallower than the bottom of buried trench gate 745. The body region 746 can be formed either uniformly or masked and localized to the active MOSFET channel region. N + source region 747 (747A-747D) has a shallower junction depth than body region 746 and is formed within body region 746 and is disposed around the trench gate and buried polysilicon 745. ing. The portion of the silicon surface where the N + region 747 is blocked comprises a shallow P + region 748 (748A, 748B), which facilitates electrical contact with the underlying P-type body region 746.

  Zener region 750 is provided to control the avalanche characteristics and breakdown voltage of device 740. The PZ Zener region 750 is shallower than the etched silicon trench (and thus shallower than the bottom of the TBOX 743) and deeper than the bottom of the buried gate 745, and is located in the portion of the silicon mesa region between the trench gates. The Ideally, the PZ Zener region 750 is placed over or under the shallow P + region 748 so that it overlaps or only slightly overlaps the lower N + source region 747.

  The body contact region 748 and the PZ Zener region 750 may be uniformly distributed, and may have a stripe shape that is orthogonal to the trench gate and the N + source stripe region.

  The zener clamp formation process can be applied to any sequence as long as the trench MOSFET fabrication sequence incorporates a thick bottom oxide layer and a deep zener clamp region.

  In FIG. 12A, the trench gate structure 760 shown in cross section was formed before introducing the zener clamp. As shown, in an intermediate step in the manufacture of a trench gate MOSFET, device 760 includes an N + substrate 761, an N type epitaxial layer 762, thick bottom oxide layers 763A, 763B, a thin sidewall gate oxide layer 764, a buried layer. And etched polysilicon trenches 765A, 765B and a thin top oxide layer 769.

  The depth xtrench of the silicon trench that encloses the gate polysilicon 765 and the TBOX 763 is the shallowest, 0.5 μm deep, and 3.0 μm, and a 1.0 μm-1.8 μm trench is easy to manufacture and control of reproducibility It is. A trench that is too shallow is prone to the risk of short channel effects (such as punch-through breakdown), and a trench that is too deep may exhibit a high electric field (which adversely affects device reliability) at the tip of the trench, It becomes difficult to fill the trench. The thickness of the TBOX can range from 1k to 5k in final thickness (after the sidewall oxide etch back step), but is preferably about 3k. The bottom of the polysilicon gate electrode 765 is determined by the difference between the trench depth and TBOX, and this difference is expressed by the relational expression xgate = xtrench−xTBOX, generally in the range of 0.5 μm−1.5 μm. is there. The thickness of the sidewall gate oxide layer 764 is in the range of 50 Å-1200 、, with 150 Å-500 よ り being more common.

The deep zener anode region 767 is ion-implanted once at 80-120 keV, followed by drive-in diffusion (900 ° C. to 1150 ° C. for 30 minutes to 10 hours), preferably with different energies. This is performed by continuous implantation in which a plurality of ions are implanted continuously at a dose. The deepest implant is done with an energy as high as 3 MeV (1.3 MeV is more common as the maximum energy of the implant). Implantation dose is generally in the range of ^{1E12cm -2} -5E14cm -2 ^(preferably 7E12cm ^-2 -5E13cm -2). As previously mentioned, the depth of region 767 can vary from a depth slightly shallower than gate depth xgate to a depth of 1 μm or more from trench depth xtrench, but as described above, gate depth xgate. A depth that is deeper and shallower than the trench depth xtrench is preferred. The photoresist 768 must be thick enough to block the deepest ion implantation and can be 3 μm-4 μm thick. Photoresist 768 must have a sidewall surface that is typically inclined at an angle of 85 ° -90 ° to the surface of the wafer to prevent implantation into adjacent device mesas. A thin upper oxide layer 769 having a thickness of about 200-700 mm is used as a pre-implant oxide layer to prevent contamination of the silicon mesa region and implantation channeling.

  In FIG. 12B, the surface of the device 780 has a silicon nitride layer 787 having a thickness of 200 to 3000 mm (preferably 500 to 1500 mm), and a lower side of a thickness of 100 to 1000 mm (preferably about 300 mm). An oxide layer 786. A device with silicon nitride on its surface is compatible with a super self-aligned process (eg, as described in US Pat. No. 6,438,822 to Williams et al.).

  FIG. 12C shows an example of a concentration profile for a continuous injection Zener voltage clamp where the deepest implant has the highest dose and the shallowest implant has the lowest dose. The graph showing the relationship between the concentration and the depth refers to the cross section of the trench 800 having the depth xtrench which is the horizontal axis in FIG. 12C. The trench 800 includes a polysilicon gate 803 having a depth xgate and a TBOX 804 extending to the bottom of the trench 800. The continuous injection portion shown in the figure includes four continuous injection portions, injection portions 801A, 801B, 801C, and 801D. The implantation portion 801D is the deepest implantation portion, and forms a PN junction portion with the opposite conductivity type epitaxial layer 802 at the depth Xj (PZ). As shown in the figure, the depth of the PZ Zener clamp is preferably deeper than the gate depth xgate and shallower than the trench depth xtrench.

The PZ Zener implants 801A-801D may be of the same dose amount or a form in which the dose amount increases as it becomes deeper as shown in FIG. 12C, but any concentration profile is possible. For example, PZ continuous infusion profile, an injection portion 801A of 5E13 cm ^-2 at 250 keV, and the injection portion 801B of 7E13cm ^-2 at 500 keV, and the injection portion 801C of 9E13cm ^-2 at 900 keV, 1.2E14cm at 1.2 MeV ^-2 The injection part 801D. This implantation sequence creates a doping profile that gradually increases in concentration with increasing depth as shown in FIG. 12C. Note that each injection need not be spaced at regular intervals.

  In FIG. 12D, a heavily doped shallow P + region 821 is introduced in contact with the zener clamp anode region. In FIG. 12D, a P + region 821 of depth Xj (P +) merges with a P-type continuous implant 822 to complete the Zener clamp. By implanting a shallow P + region using a low energy, high dose (high beam current) ion implanter, there is no need to perform high concentration implantation in continuous implantation. By performing the shallow high dose implant and the deep low dose separately on two different machines, a time consuming high dose using a high MeV level capable (ie high energy) ion implanter. Manufacturing costs are minimized by eliminating the need for quantitative ion implantation. The P + region 821 can also be used at other locations in the device that contact the P-type body region where there is no PZ Zener region.

  Note that the P-type body region 824 can also include a continuous implant, but that is done at low energy. Compared to a trench cross-sectional view 820 of trench depth xtrench with a buried polysilicon gate 825 and a thick bottom oxide layer 826, the depth of the P-type body region is the same in FIG. 12D. It has been shown that the depth Xj (PB) needs to be shallower than the gate depth xgate to facilitate active channel formation of the device.

  Another possible PZ Zener region profile is shown in FIG. 12E, where the PZ Zener region constitutes one deep implant 821 and there is no shallow PZ ion implant. In this case, the Zener region is in contact with the upper shallow P + (not shown) through the continuous implant including implants 831A, 831B, 831C, and 831D. As in the previous example, the operation of the MOSFET in the active cell of the same device requires that the body dopant profile has a depth Xj (PB) that is less than the gate depth xgate. The PZ Zener region implant profile of the implant 832 must overlap the PB body implant profile 831 to ensure clamp diode electrical connection. The device of FIG. 12E is easier to manufacture, but exhibits a higher series resistance than the device of FIG. 12D, thus lowering the robustness of the clamp and thus lowering the avalanche energy absorption capability.

  In the above example, the polysilicon gate contact is not particularly described. Specifically, in the device 840 of FIG. 13A, the embedded polysilicon gate 844 provides a polysilicon region 845 to facilitate electrical contact to the metal gate bus 852 and gate bond pads (not shown). Must be extended to the surface. The problem is one of the sequences. Since polysilicon 845 and silicide contact region 851B extend over the surface of the wafer, the presence of polysilicon 845 causes the deep zener clamp implant (and thus any P-type region) to move into the silicon under polysilicon gate bus 845. It may even prevent or even prevent introduction into the area.

  Electrically, the lack of P-type material under the polysilicon gate bus 845 is a significant problem. Since this gate is grounded (ie tied to the source potential) and the epitaxial drain is biased to the full drain potential, the silicon underneath the unshielded polysilicon gate bus (ie no P region underneath) (Polysilicon) and the oxide layer are subjected to a strong electric field, and may be subject to avalanche in silicon and deterioration of the dielectric.

  Three solutions to this problem are possible. That is, a method of forming a P region in a gate bus region before forming a trench gate, a method of implanting through a gate contact polysilicon, and a gate embedded in one of two deposited portions by dividing the gate polysilicon. And forming the surface polysilicon 845 extending outside the trench to facilitate connection.

  Of these three options, the disadvantage of early (pre-trench) implants is that they are subject to the overall thermal budget of the process. The adverse effects of the high temperature process are dopant diffusion (especially due to relatively high temperature sacrificial acid and gate oxidation cycles) and dopant separation and dopant disappearance due to trench etching. Both of these effects make it difficult to provide a PZ Zener Clamp together in this step of the process because undesirable diffusion reduces the PZ concentration and creates a low tilt angle PZ Clamp dopant profile. Thus, the gate bus shielding problem can be overcome by incorporating a P-type implant in front of the trench, but it is difficult to use such an early stage implant as a zener clamp.

  The second option is to implant the PZ region through a polysilicon gate bus. The disadvantage of this method is that the Zener diode doping profile and junction depth are highly dependent on the thickness of the polysilicon (i.e. drastic changes caused by poorly controlled chemical mechanical etchback processes). It is a point. Creating a Zener doping profile with well-controlled junction depth during fabrication is difficult because there are many process variables that cannot be controlled well as long as the implant is through the surface polysilicon layer.

  A preferred sequence is to divide the polysilicon gate and gate bus formation into two deposition steps, the PZ region after the deposition and etchback of the buried polysilicon gate and before the deposition of the surface polysilicon. By injecting the PZ anode at a later stage in the process. FIG. 13A illustrates a cross-section 840 including embedded gates 844A-844F that have been deposited and etched back (planarized) prior to ion implantation of P-type Zener implants 853A and 853B. P-type body regions 843A-843G can also be implanted at this point in the manufacturing sequence. Both implants of body 843 and zener region 853 can be formed using diffused junctions, preferably using high energy continuous implantation. As is apparent from the fact that the polysilicon layer 845 overlaps the PB body regions 843D and 843E and the PZ Zener regions 853A and 853B, the second polysilicon layer 845 has a P-type body and a Zener implantation portion. Formed after.

  In device 900 of FIG. 13B, a relatively well controlled silicon nitride layer 909 is passed through a trench defined by a sandwich type hard mask that includes a thin oxide layer 908 and silicon nitride 909 (including regions 909A, 909B, 909C). Ion implantation may be performed to form PZ Zener anode regions 904A and 904B. The PZ Zener region is implanted using a thick photoresist mask 910 to limit the position to receive the PZ Zener implant after depositing and etching back the first polysilicon 907 (including 907A and 907B). . In the example shown in the figure, the PZ Zener injection portion is formed in the mesa region corresponding to the PB body regions 905A and 905B (excluding the body region 905C). The cross-sectional shape of the photoresist 910 must be vertical with a steep slope to prevent non-negligible implantation intrusion into the protected mesa (such as the mesa contained in the body region 905C).

  Implantation of the body region 905 (including 905A, 905B, and 905C) is also preferably performed after the formation of the buried polysilicon gate and before or after the PZ Zener implantation. Thereafter, a second polysilicon gate contact or gate bus region 912 as shown in FIG. 13C is deposited and patterned by photolithography, mask and etching. Since the second polysilicon 912 is formed after the PB body region 905 and the PZ Zener region 904, the implanted region can be located below the surface polysilicon 912. As a result, the P region electrostatically shields the gate bus 912 from the drain potential of the epitaxial layer 902.

  When the device is manufactured using ion implantation after the formation of the upper polysilicon bus, the depth of the body 843 and the Zener 853 varies depending on the shape of the surface, depending on whether there is a polysilicon layer on the surface. Note that it becomes shallower and completely blocked.

  One possible manufacturing flow for the manufacture of trench gate MOSFETs according to one embodiment of the present invention is outlined in FIG. 14A. The process of FIG. 14A includes substrate preparation and an initial step 920 of etching the trench in the epitaxial layer. Next, in step 922, a thick bottom oxide layer (TBOX formation) is formed in the trench, a gate oxide layer (GOX) is formed on the sidewall of the trench, and a first polysilicon layer “poly 1” is formed. PB and PZ implantation can be performed at this point.

  A combination of two possible processes is obtained. If poly 1 remains on the silicon and the PB body and PZ Zener regions are implanted, there is no need to form a second polysilicon layer at step 926, and the process proceeds to N + in step 924 or directly at step 928. And proceed to formation of the P + region. Alternatively, if the first polysilicon layer “Poly 1” is etched back before the PB body and PZ Zener implants are performed, then in step 926 the second polysilicon layer before performing the N + and P + implants. “Poly 2” is applied to form a pattern. Finally, in step 928, the contact and metal are formed, and the manufacturing is finished.

  In another process shown in FIG. 14B, the epitaxial and field oxide formation step 920 is followed by all dopant implantation processes (eg, PZ, PB, N +, P + implantation) 934 followed by etching the trench in step 936. To do. The trench gate is subjected to trench etching, TBOX formation, and gate oxidation in step 936, one polysilicon deposition and mask etch back in step 938, and then a contact and metal layer process 940. Formed by.

15A-15E illustrate an example of an integrated process flow used for the fabrication of a Zener clamped TBOX trench gate type device 950 according to the present invention. The process begins with an N + substrate of 1 to 3 mΩcm ² with a crystal orientation <100> as shown in FIG. 15A, and has an N-type silicon layer with a resistivity and thickness in a range according to the drain voltage rating of the device An epitaxial growth of 952 is performed (see Table 1 below for target values of epitaxial layer thickness and resistivity).

  After the epitaxial growth is completed, the silicon material is oxidized at a temperature of 850 ° C. to 1100 ° C. for 10 minutes to 2 hours, preferably at a temperature of 900 ° C. to 1000 ° C. for 300 minutes. The resulting oxide layer 953 has a target thickness of 100 to 1000 mm, but preferably about 300 to 500 mm. Next, a silicon nitride layer 954 is deposited to a thickness of 800 to 5000 using CVD. Thereafter, the silicon nitride layer 954 is patterned using photolithography technology to expose the trench etching region, and then dry etching is performed using a plasma method or an RIE method, so that the silicon nitride layer 954, the oxide layer 953, and finally Then, the exposed portion of the silicon epitaxial layer 952 is removed. The photoresist used to define the etch window is typically removed prior to the silicon etch step that forms trench 955. The trench 955 may have a depth in the range of 1.5 μm to several μm as described above.

To form the structure of FIG. 15B, the trench is oxidized at 900 ° C. to 1100 ° C. for 30 minutes to 5 hours, preferably 950 ° C. to 1000 ° C. for 30 minutes to remove etch damage. Next, the oxide layer in the trench 955 is removed by performing a hydrofluoric acid or BOE (buffered oxide etch), and a second layer of silicon dioxide (not shown), a so-called “lining oxide layer” ( Grow to a thickness of several hundreds of microns using thermal conditions similar to sacrificial oxide growth (as previously described). Next, a high bottom plasma CVD is used to deposit a thick bottom acid underlayer and using a directional deposition method (described in US Pat. No. 6,291,298 to Williams et al.), Preferably 1 to 5 k thick, preferably Form a thick bottom acid underlayer of 2k 3 to 3k. A thick oxide layer is also formed on silicon mesas such as regions 956A and 956C. The deposition on the sidewalls of trench 955 is minimal. After being immersed in hydrogen fluoride for a short time, the oxide layer 956 deposited on the sidewall is removed along the sidewall portion of the lining oxide layer. A gate oxide underlayer 957 is grown on the trench sidewall using conditions similar to the sacrificial oxidation process described previously. The final thickness of the gate acid underlayer 957 is determined by the maximum gate voltage rating V _GS (max) of the device. In general, the maximum continuous operating voltage of the gate should be such that the gate electric field (defined as V _GS (max) / X _OX ) does not exceed 4 MV / cm (provided that the electric field is 5 MV / cm). Except for an oxide layer thinner than 200 mm that can be safely applied to the gate). For example, a 300Å gate can support a maximum operating voltage of 12V, and a 500Å gate acid underlayer can be used to fabricate devices with a 20V rated gate.

  After gate oxidation, a polysilicon layer 958 is deposited to a thickness approximately equal to the depth of the trench using CVD technology, and then etch back or CMP processing for planarization is performed. Polysilicon 958 may be doped in situ, or dopant may be implanted into trench polysilicon layer 958 after ion implantation and diffusion at 950 ° C. to 1000 ° C. for 1 hour. Generally, phosphorus is used for N-channel MOSFETs (and boron is used for P-channel devices, but some P-channel MOSFETs are doped with phosphorus for the purpose of improving reliability. Polysilicon or boron doped polysilicon with a small amount of phosphorus may be used.) After the final etch back of the polysilicon 958, a thin oxide layer 959 having a thickness of 100 to 300 mm is applied at 900 ° C. to 950 ° C. for 30 minutes to 1 hour mainly to seal the upper part of the polysilicon gate 958. And heat grow.

  In FIG. 15C, for example, glass 960, silicon dioxide, TEOS, or BPSG is deposited using spin-on or CVD techniques, and then all of the surface present on the surface of silicon nitride layer 954 by planarization etchback or CMP processing. Remove the glass. During this step, portions of glass 960 and the entire TBOX 956A and 956B region of the surface are removed.

  In FIG. 15C, as described above, the PZ Zener region 961 and the PB body regions 962A and 962B are preferably formed by continuous implantation of boron. In this step, the oxide layer over the gate bus region (not shown) is cleaned, and a second polysilicon layer is deposited to a thickness of 1 to 6 k, preferably 3 k. The polysilicon layer is masked and etched back to form a gate bus region (not shown).

To form the structure of FIG. 15D, the silicon nitride layer 954 is removed from the top of the polysilicon gate 958 embedded in the trench without removing the glass 960 by plasma etching. Next, the N + region 964 is selectively masked and implantation is performed in the active mesa region. N + injection region 965 may include phosphorus, but preferably utilizes arsenic ion implantation 5E15 cm ^-2 to 8E15cm ^-2 in 80-120KeV. P + implantation region 964 may be formed by implanting 2E15 cm ^{−2 to} 4E15 cm ⁻² of boron at 60-100 keV with a mask or blanket layer.

  The source injection can be followed by 20 seconds of RTA (rapid thermal annealing) or 10 minutes of thermal annealing at 950 ° C. Alternatively, implant annealing may be performed by a subsequent glass reflow step.

  After the source and body contact implants, the thin oxide layer 953 can be removed to expose the silicon mesa. Alternatively, glass BPSG or spin-on-glass (SOG) can be deposited and masked with a contact mask to expose the silicon mesa region. As shown in FIG. 15E, the glass 962 can be chamfered after a contact mask by thermal annealing for 15 minutes, typically at 900 ° C. for 15 minutes. The advantage of this chamfering of the glass is that the problem of metal voids and step coverage can be prevented. Metal formation begins with a thin titanium / TiN barrier metal 995 and then sputters a thick aluminum-copper or aluminum-copper-silicon 996, typically 3 μm thick. The metal 995 and 996 are then masked and dry etched to separate the gate bus from the source metal.

  The resulting structure 950 shown in FIG. 15E is one of the completed voltage clamped TBOX trench gate MOSFET with a buried trench gate and comprising a thick bottom oxide layer 956B, a Zener clamp 961 and a body 962. It is a form. In such a process, the gate 958 is formed before the junction of the Zener clamp 961 and the body 962.

  In another process flow shown in FIGS. 16A and 16B, a doping region is formed first, followed by a trench. In this alternative, the device 980 is formed by a continuous masking, ion implantation, and continuous ion implantation in the N-type epitaxial layer 982 on the N + substrate 981, PZ zener clamp 982, PB body region 938, N + A source 984 and a P + region 985 are provided. Depending on the selection, high temperature diffusion may be used to drive the body 983 and Zener 982 regions. The implantation dose in this process flow is similar to the aforementioned energy and dose conditions used in the manufacture of the device of FIG. 15E.

  In order to create the structure shown in FIG. 16A, a trench gate is then formed using silicon trench etching, then a sacrificial oxide layer is formed, a lining acid underlayer is formed, TBOX990A and 990B are deposited, and a gate acid underlayer is formed. 991 is formed, and a polysilicon refill portion is deposited and etched back to form gates 992A and 992B. Note that zener clamp 982 is not self-aligned with trench gate 992A and may therefore extend on either side of the trench gate.

  Either process flow (ie, trench formation before doping or trench formation after doping) can be used to adjust the size of the Zener diode clamp to handle the total avalanche current of the device. In FIG. 17, Zener diodes have Zener regions 1004A-1004C, which extend over several trench gates 1003A, 1003B, and 1003C. The contacts to the mesa region where the Zener regions 1004A-1004C are located have shallow P + regions 1008A, 1008B, and 1008C, and preferably an N + source region 1009 that exists inside or substantially overlaps the Zener diode region. Does not have.

  18A, 18B, and 18C show various zener diode clamp designs for TBOX trench gate MOSFETs. In FIG. 18A, Zener clamp 1035 and P + region 1039B are located in an inactive (diode only) cell or mesa region, and the active transistor includes a shallow P + 1039A that forms a contact contact to source regions 1038B, 1038C. obtain.

  As another embodiment of a device with a source-body short circuit, FIG. 18B shows that in a wide mesa device, a surface P + region 1061 coupled with a PZ zener clamp 1055 is integrated into the central portion of the active cell. It has been shown that Unlike conventional clamped devices, the PZ Zener clamp 1055 extends under the gate polysilicon, but preferably does not extend under the trench and its TBOX portion 1053.

  In another embodiment of the present invention, the Zener clamp of FIG. 18C is a deep PZ implanted clamp region with a single implant (without using a continuous implant to form a P-type array as shown in FIG. 18B). 1079 may be provided. However, such devices exhibit higher impedance at breakdown than devices incorporating a P-type Zener that includes a high concentration region from the surface to the bottom of the junction (as in the device of FIG. 18A).

19A and 19B show a Zener clamp structure according to another embodiment of the present invention. In the diode 1090 of FIG. 19A, the PZ Zener anode region 1093 is diffused into the epitaxial layer 1092. After a single shallow implant, the P-type Zener anode region is implanted to its target depth using high temperature drive-in diffusion at 1050 ° C. to 1150 ° C. for 3 to 10 hours. In the case of N-channel MOSFET, the zener implant is a boron dose of 5E14 cm ^-2 to 5E15 cm ^-2 at 80 keV. In the case of a P-channel device, the zener implant is boron with a comparable or slightly higher energy (approximately 100 keV to 120 keV). As previously described, the diffused junctions exhibit a generally Gaussian-shaped dopant profile that decreases in concentration, which is not a preferred dopant profile to form a highly reproducible voltage clamp. Furthermore, if the width of the junction is not restricted by the trench gate, it expands in the horizontal direction as it does in the vertical direction. The width of the diffused junction is three times the width y of the mask opening used to determine the PZ diode by photolithography because the lateral diffusion reaches about 80% of the depth in each direction. Can be doubled.

  In contrast, the continuous PZ anode-injected diode 1100 shown in FIG. 19B extends in a generally vertical column direction formed by overlapping and coupling different dose and energy injection portions 1104A-1104D. It has a P-type material of structure. The depth of the composite Zener structure 1104 is determined by the energy of the dopant implantation 1104A. The width of the PZ row is slightly wider than the width y of the mask due to lateral variation (bounce) of implantation. Unlike the diffused junction, the width of the implanted region becomes wider as it becomes deeper (since the lateral variation increases in proportion to the implantation energy). The mask material 1103 can be a thick photoresist, silicon dioxide, silicon nitride, or other dielectric material to such an extent that implantation at maximum energy can be blocked from entering the epitaxial layer 1102 through the mask protected area. A sufficient thickness must be selected.

  If the trench abuts one or both of the side surfaces of the PZ implant, the lateral variation of the implant is regulated by the trench (unless the trench is too thin).

  20A-20H illustrate various examples of epitaxial layers according to embodiments of the present invention. In each case, the purpose of the epitaxial layer is to minimize the ionization current near the thin gate oxide underlayer without sacrificing the voltage clamping capability of the PZ Zener clamp. In FIG. 20A, a cross section 1120 includes a uniformly doped epitaxial layer 1122A of thickness xepi formed on an N + substrate 1121A. The corresponding dopant profile is shown in FIG. 20B.

  In FIG. 20C, a cross-section 1130 includes a highly doped N + substrate 1131A, a first N-type epitaxial layer 1132A formed on the N + substrate 1131A, and a second N located on the epitaxial layer 1132A. Type epitaxial layer 1133A. FIG. 20D shows the dopant profile of the upper epitaxial layer 1133A (thickness xepi2) where the stepped epitaxial layer has a concentration Nepi2 that is lower than the dopant concentration Nepi2 indicated by the dopant profile 1132B of the bottom epitaxial layer 1132A. The concentration Nepi2 of the upper epitaxial layer 1133 may be 5% to 40R lower than the concentration of the bottom epitaxial layer 1132A, but preferably the concentration Nepi2 is in a concentration range 15% to 25% lower than the concentration of the bottom epitaxial layer 1132A. Should. The thickness of the bottom epitaxial layer need only be sufficient to support the depletion layer that extends over the Zener voltage clamp during breakdown

  FIG. 20E shows an epitaxial layer 1152A having a continuous concentration gradient, which is maximum in the vicinity of the substrate 1151A and continuously increases toward the surface, as shown in the concentration graph of FIG. 20F. It is falling. Such an epitaxial layer 1152A is more difficult to grow than a constant concentration epitaxial layer and does not exhibit a step in its concentration profile (which is difficult to control reproducibility).

  A novel method for synthesizing an epitaxial layer having a continuous concentration gradient is by using multiple ion implantations 1172A, 1173A, and 1174A with different doses and energies, and FIG. The resulting concentration profiles 1172B, 1173B, and 1174B are shown in FIG. 20H. This structure consists of a uniformly doped lightly doped epitaxial layer Nepi 1175A grown on an N + substrate 1171A, then a deep high energy implant 1172A (reference NW1), a shallow medium energy implant 1173A (reference NW2), Furthermore, it is formed by continuously performing low energy injection 1174A (reference numeral NW3). The lowest energy implant may be spread over the surface or implanted below the surface to leave the epitaxial layer 1175A portion uncompensated.

  The advantage of combining stepwise or continuous concentration gradient epitaxy and a Zener clamped TBOX trench gate device is that the ionization current near the thin gate oxide sublayer without sacrificing the voltage clamping capability of the PZ Zener clamp. Can be further minimized. FIG. 21A shows the relative depth of the stepped epitaxial layers 1182, 1183 relative to the trench gate inside the device 1180. Upper epitaxial layer 1183 has a thickness xei2 selected to be deeper than the bottom of buried polysilicon gate 1187 (thus lowering the hot carrier level in the vicinity of gate oxide underlayer sidewall 1188). Furthermore, the bottom of the PZ anode region 1185 should overlap the first epitaxial layer 1182 so that the first epitaxial layer 1182 rather than the upper epitaxial layer 1183 determines the breakdown of the clamp diode.

  As an example, consider a trench MOSFET with a 1.7 μm trench and a 0.3 μm thick TBOX layer. In such a device, the bottom of the buried polysilicon gate 1185 is 1.4 μm deep. Thus, the transition between the first and second epitaxial layers is between 1.4 μm and 1.8 μm, but 1.6 μm (to be far enough away from the thin gate oxide sidewall 1188 of the device). Deeper is preferred.

  FIG. 21B is a cross-sectional view showing the dopant profile through the active MOSFET channel, taken at section A-A ′ of the device 1180 of FIG. 21A. In this dopant profile, the buried PB body region 1184A with profile 1184B is shallower than the upper epitaxial layer 1183, and thus the junction depth (PB) is shallower than the depth Xepi2 of the upper epitaxial layer 1183A.

  Since the PB body region 1184A does not extend into the more heavily doped bottom epitaxial layer 1182A, the ionization rate at the epitaxial drain (in the vicinity of the gate) It becomes lower than the case where it is manufactured using.

  FIG. 21C is a cross-sectional view showing dopant profiles 1185B and 1181B through the PZ Zener clamp anode 1185A, taken along section B-B 'of device 1180. FIG. The doping profile 1185B shows that the implanted PZ anode region 1185A extends deeper than the upper epitaxial layer 1183A and below the bottom epitaxial layer 1182A. Since the PZ region anode 1185A is shallower than the total thickness of the epitaxial layer, the depth Xepi2 of the upper epitaxial layer 1183A is shallower than the depth Xj (PZ) of the Zener diode junction, and Xj (PZ) is the total thickness of the epitaxial layer. Shallow than the thickness (Xepi1 + Xepi2).

The thickness Xepi1 of the bottom epitaxial layer 1182A must maintain the device's rated breakdown voltage BV _DSS and is ideally maintained just before reaching the reach-through breakdown limit. The reach-through limit depends on the net epitaxial thickness, which is the thickness of the epitaxial region between the PZ anode 1185A and the upper side of the N + substrate 1181A. Since the PZ anode region 1185A overlaps the bottom epitaxial layer 1182A, the net epitaxial thickness of the Zener is determined from the total thickness of the epitaxial layer (Xepi1 + Xepi2) by the junction depth Xj (PZ) of the PZ anode region 1185A. Subtracted thickness. Therefore, the depth and thickness preferably satisfy the following formula 1.

Here, the doping of the upper epitaxial layer 1183A is, assuming lower than the doping of the bottom layer 1182A, Formula 1, the body - epitaxial layer junction breakdown voltage _{BV body} must be higher than the Zener breakdown voltage BV _Z It is to confirm that.

  If the depth of the bottom of the buried polysilicon trench gate 1187 is xpoly and the depth of the bottom of the trench (ie, TBOX region 1186) is xtrench, the following can be determined. That is, the polysilicon gate 1187 must be deeper than the body 1184A, and in a more preferred embodiment, at a depth that is less than the thickness of the lightly doped upper epitaxial layer 1183A, and therefore satisfies Equation 2 below. Should be.

  Combining the trench polygate criteria with the step-wise epitaxial junction breakdown criteria described above, the general rule for improving a Zener-clamped TBOX trench-gate MOSFET with a step-like epitaxial layer is: 3 is obtained.

  In short, the body must be shallower than the polysilicon gate, and the polysilicon gate should be at a depth shallower than the lightly doped epitaxial layer that is thinner than the thickness of the entire epitaxial layer.

  In the preferred embodiment, the depth of the PZ Zener clamp junction is also shallower than the bottom of the trench, and therefore satisfies Equation 4 below.

  Such criteria can only be met if the trench is substantially deeper than the gate, i.e. there is a thick bottom acid layer.

  The above-described devices according to the present invention and any processes used in their manufacture (eg, those shown in FIGS. 15A-15E and FIGS. 16A-16B) take N-channel devices as examples, but the methods disclosed herein. Note that is equally applicable to P-channel devices. A person skilled in the art will replace phosphorus or arsenic with boron (or vice versa) and adjust the implantation energy as appropriate to allow for different dopant species and charge-to-mass ratios during ion implantation. Can be formed. Furthermore, the above process illustrations are not intended to limit the process flow used to that disclosed herein. In many cases, the sequence of the processing sequence can be reordered without fundamentally changing the resulting structure or the advantages of the voltage clamped TBOX trench gate MOSFET.

Sectional view of a conventional, “flat bottom” trench gate type power MOSFET with a uniform gate oxide layer. FIG. 1B is an equivalent circuit diagram of the device shown in FIG. 1A. The figure which shows the effect of the diode with a gate. 1B is a graph showing the relationship between trench gate junction breakdown and oxide layer thickness for the device of FIG. 1A. 1B is a graph illustrating the relationship between trench gate junction breakdown and gate bias for the device of FIG. 1A. Sectional drawing of the existing trench gate type power MOSFET with a deep body shield provided with the uniform gate oxide layer. FIG. 2B is a schematic diagram of the device of FIG. 2A showing the JFET shielding effect of a gated diode. It is sectional drawing of the device of FIG. 2A, Comprising: The figure which shows the shielding effect of a depletion layer expansion. FIG. 2B is a cross-sectional view of the device of FIG. 2A showing avalanche current flow through the center of each cell. FIG. 2B is a cross-sectional view of the device of FIG. 2A showing current flow in the on state including current “spread” in the epitaxial drain. 2B is a graph showing on-resistance as a function of cell density in three operating regions of the device of FIG. 2A. The top view of trench gate type MOSFET which provided the clamp diode in each cell. Sectional view of a conventional "1 / n" (one of n) zener clamped trench gate type power MOSFET with a uniform gate oxide layer. FIG. 3B is an equivalent circuit diagram of the device of FIG. 3A and shows a zener clamp effect of a gated diode. The top view of the trench gate type MOSFET by which "1/16" (one of 16 pieces) was Zener clamped. FIG. 3B is a cross-sectional view of the device of FIG. 3A showing avalanche current flow through a cell with a Zener clamp. 3B is a graph showing the relationship between trench gate junction breakdown and oxide layer thickness for the device of FIG. 3A. 3B is a graph showing the relationship between trench gate junction breakdown and epitaxial dopant concentration for the device of FIG. 3A. FIG. 3 is a cross-sectional view of an existing, unclamped trench gate MOSFET with a thick bottom oxide layer. FIG. 4B is an equivalent circuit diagram of the device of FIG. 4A and clearly shows that no gated diode is provided. Sectional drawing of a device showing the flow of avalanche current. 1 is a cross-sectional view of a device showing how hot carriers are injected into a thin gate oxide layer by impact ionization in a uniform gate oxide layer trench device. FIG. 4 is a cross-sectional view of a device showing how hot carriers are injected into a thick oxide layer with little implantation into a thin gate oxide layer by impact ionization in a TBOX trench gate type device. FIG. 3 is a cross-sectional view showing the current flow in an unclamped vertical trench gate MOSFET with a thick bottom oxide layer. The equivalent circuit diagram of the parasitic bipolar transistor superimposed on the cross section of the device for demonstrating the mechanism of double injection. 1 is an equivalent circuit diagram of a trench MOSFET with an integrated parasitic bipolar transistor, drain diode, and resistive emitter-base short. The figure which shows the current-voltage characteristic of the snapback breakdown induced by the parasitic bipolar. A cutaway view of a trench MOSFET showing the origin of a parasitic bipolar base resistor. 3 is a cutaway view showing a stripe-shaped trench MOSFET having a bamboo source-body mesa contact design. FIG. FIG. 4 is a cross-sectional view of a trench MOSFET having a uniform gate oxide layer, and shows that a shallow Zener diode cannot prevent substantial impact ionization in a thin gate oxide layer. 1 is a cross-sectional view of a Zener clamped TBOX trench gate MOSFET according to one embodiment of the present invention. FIG. 9 is an equivalent circuit diagram of the device of FIG. 8 showing a drain diode and a zener clamp without a field plate. 9B is a graph showing the relationship between breakdown voltage and epitaxial dopant concentration for the Zener diode and body diode of FIG. 9A. FIG. 4 is a cross-sectional view of a device showing that a zener clamp forces an avalanche adjacent to the TBOX region. 1 is a cross-sectional view of a TBOX trench gate MOSFET with a shallow Zener clamp, according to one embodiment of the invention. Sectional drawing of TBOX trench gate type MOSFET provided with the deep Zener clamp. The graph which shows the relationship between a breakdown voltage and the depth of a PZ Zener anode. 1 is a cutaway view of a Zener clamped TBOX trench gate MOSFET according to one embodiment of the invention. FIG. FIG. 4 is a cross-sectional view of a device with a thin top oxide layer undergoing continuous implantation for the formation of a Zener diode. FIG. 3 is a cross-sectional view of a device undergoing continuous implantation through a silicon nitride hard mask for the formation of a Zener diode. FIG. 5 shows the concentration profile resulting from formation by continuous injection of a PZ anode. FIG. 6 shows the concentration profile as a result of continuous injection with shallow P + regions superimposed. FIG. 5 shows a concentration profile of a continuous injection body with a deep Zener injection region. Sectional drawing of a device which shows a gate bus | bath with the PZ area | region which makes a lower layer. FIG. 6 is a cross-sectional view of the device during a Zener implant performed prior to the second polysilicon deposition. FIG. 3 is a cross-sectional view of a device after a second polysilicon deposition, masking, and etching. Flow chart of a process in which dopant is introduced after trench formation. Flow chart of a process in which trench formation is performed after dopant introduction. 1 is a cross-sectional view of a structure formed during a zener-clamped TBOX trench gate MOSFET manufacturing process according to one embodiment of the invention. 1 is a cross-sectional view of a structure formed during a zener-clamped TBOX trench gate MOSFET manufacturing process according to one embodiment of the invention. 1 is a cross-sectional view of a structure formed during a zener-clamped TBOX trench gate MOSFET manufacturing process according to one embodiment of the invention. 1 is a cross-sectional view of a structure formed during a zener-clamped TBOX trench gate MOSFET manufacturing process according to one embodiment of the invention. 1 is a cross-sectional view of a structure formed during a zener-clamped TBOX trench gate MOSFET manufacturing process according to one embodiment of the invention. FIG. 6 is a cross-sectional view illustrating masked implant formation in a doping region in another process of a Zener clamped TBOX trench gate MOSFET. Sectional drawing which shows trench formation, trench filling, contact formation, and metallization in another process of a Zener clamped TBOX trench gate type MOSFET. FIG. 5 is a cross-sectional view of a Zener clamped TBOX trench gate type MOSFET with an extra width Zener diode overlying a plurality of gates. FIG. 4 illustrates a TBOX trench gate MOSFET having a zener cell isolated from an active cell, according to one embodiment of the invention. FIG. 3 illustrates a TBOX trench gated MOSFET with a narrow implanted Zener column in the center of an active cell, according to one embodiment of the invention. FIG. 4 illustrates a TBOX trench gated MOSFET with a deep implanted Zener in the center of an active cell, according to one embodiment of the invention. FIG. 3 is a cross-sectional view of a structure during formation of a deep diffusion Zener diode. FIG. 3 is a cross-sectional view of a structure during formation of a continuously injected Zener diode. Sectional view of a structure with a uniform epitaxial layer. FIG. 5 shows a dopant profile of a structure with a uniform epitaxial layer. Sectional drawing of the structure provided with the step-like epitaxial layer. FIG. 4 shows a dopant profile of a structure with an epitaxial layer on the stairs. FIG. 3 is a cross-sectional view of a structure with an epitaxial layer having a continuous concentration gradient. FIG. 4 shows a dopant profile of a structure with an epitaxial layer having a continuous concentration gradient. Sectional view of a structure with a uniform epitaxial layer having a continuous implant. FIG. 5 shows a dopant profile of a structure with a uniform epitaxial layer having a continuous implant. 1 is a cross-sectional view of a Zener clamped TBOX trench gate MOSFET with stepped epitaxial drain according to one embodiment of the present invention. FIG. 21B shows a dopant profile along a location of the MOSFET of FIG. 21A. FIG. 21B shows a dopant profile along a location of the MOSFET of FIG. 21A.

Claims (25)

A first conductivity type substrate;
A gate structure in a plurality of trenches in the substrate, wherein the gate structure in each trench has a first thickness at a sidewall portion of the trench and a second thickness greater than the first thickness at a bottom portion of the trench. A gate structure including a conductive gate surrounded by an insulating material having a thickness of:
A first region of a second conductivity type adjacent to at least one of the trenches, extending to a first depth of the substrate and including a channel region adjacent to the trench;
A second region of the second conductivity type in electrical contact with the first region and extending to a second thickness deeper than the first depth and shallower than the trench;
A third region of the first conductivity type located on the first region, wherein a voltage of the conductive gate forms a lower layer of the substrate from the third region through the first region And a third region for controlling a current flowing to the semiconductor device.   The semiconductor device according to claim 1, wherein the conductive gate extends to a depth deeper than the first depth and shallower than the second depth.   The substrate includes a first semiconductor layer, the first semiconductor layer is located on a heavily doped semiconductor substrate, and the trench extends into the first semiconductor layer. The semiconductor device according to claim 1.   The substrate is a second semiconductor layer formed on the first semiconductor layer, and further includes the second semiconductor layer doped at a lower concentration than the first semiconductor layer. The semiconductor device according to claim 3. The first region forms a junction with the second semiconductor layer;
The semiconductor device according to claim 4, wherein the second region forms a junction with the first semiconductor layer.   4. The semiconductor device according to claim 3, wherein a voltage of the conductive gate controls a current flowing from the third region through the first region to the semiconductor substrate through the first semiconductor layer. 5. .   The substrate of claim 1, wherein the substrate comprises a layer having a continuous dopant concentration gradient such that a trench is present and the dopant concentration of the first conductivity type increases with the depth of the layer. Semiconductor device.   The semiconductor of claim 1, wherein the substrate includes a series of implants having different depths and dopant concentrations such that the dopant concentration of the first conductivity type increases with the depth of the substrate. apparatus.   The semiconductor device according to claim 1, wherein the second region includes a series of a plurality of implantation portions having different depths. The first region and the third region are in a first mesa (a plateau-shaped region) between a first pair of trenches,
The semiconductor device according to claim 1, wherein the second region is between a second pair of trenches.   11. The method of claim 10, further comprising a fourth region of the second conductivity type on the surface of the substrate and extending completely across a portion separating the second pair of trenches. Semiconductor device. The mesa between the first trench and the second trench (the plateau shape region)
The third region on the surface of the substrate and adjacent to the first trench;
A fourth region of the first conductivity type on the surface of the substrate and adjacent to the second trench;
A fifth region of the second conductivity type located on the surface of the substrate and between the third region and the fourth region;
A first region forming a lower layer of the third region and the fourth region;
2. The semiconductor device according to claim 1, wherein the semiconductor device includes the second region which forms a lower layer of the third region and is located away from the first trench and the second trench.   The semiconductor device according to claim 12, further comprising an electrical connection portion between the third region, the fourth region, and the fifth region.   The second region extends to a first plurality of adjacent mesa sets between the plurality of pairs of trenches, and a second plurality of adjacent mesas between the plurality of pairs of trenches. The semiconductor device according to claim 1, wherein the semiconductor device does not exist in the set.   The semiconductor of claim 1, further comprising a gate bus in electrical contact with the gate structure in the trench and located over a portion of the substrate that includes at least a portion of the first region. apparatus.   The semiconductor of claim 1, further comprising a gate bus in electrical contact with the gate structure in the trench and overlying a portion of the substrate that includes at least a portion of the second region. apparatus.   2. The semiconductor device according to claim 1, wherein the second region has a dopant concentration of the second conductivity type higher than a dopant concentration of the first region. A method for manufacturing a semiconductor device, comprising:
(A) forming a plurality of trenches in a first conductivity type substrate;
(B) depositing a thick oxide layer on the bottom of the trench;
(C) forming a gate acid underlayer on the trench sidewall;
(D) filling the trench with a conductive material;
(E) forming a second conductivity type body region on the substrate in a region corresponding to one or more mesas (mountain shape region) between the trenches, wherein the body region has a first depth; The process,
(F) forming the second conductivity type clamp region in a region corresponding to one or more mesas between the trenches, wherein the clamp region is deeper than the first depth and more than the trench; The process having a shallow second depth; and
(G) forming an active region of the first conductivity type on the body region;
(H) providing an electrical connection to the conductive material, the active region, and the substrate.   The method of claim 18, wherein the step (a) is performed before the step (e) and the step (f).   The method of claim 18, wherein the step (e) and the step (f) are performed before the step (a).   The method of claim 18, further comprising: patterning the conductive material to form a gate bus located on the substrate.   The method of claim 21, wherein forming the body region comprises implanting the second conductivity type dopant through the gate bus.   The method of claim 21, wherein forming the clamp region comprises implanting the second conductivity type dopant through the gate bus. Removing the conductive material from the surface of the substrate;
Forming a gate bus in contact with the conductive material and located on a portion of the substrate;
19. The step of forming the body region and the step of forming the clamp region are performed after removing the conductive material from the surface of the substrate and before forming the gate bus. The method described in 1.   The method of claim 18, wherein each of the trenches traverses one or more other trenches.

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