CN103578952B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
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- CN103578952B CN103578952B CN201210283261.XA CN201210283261A CN103578952B CN 103578952 B CN103578952 B CN 103578952B CN 201210283261 A CN201210283261 A CN 201210283261A CN 103578952 B CN103578952 B CN 103578952B
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- Prior art keywords
- clearance wall
- gate electrode
- dummy gate
- material layer
- gate
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 55
- 238000000151 deposition Methods 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 239000011810 insulating material Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000003989 dielectric material Substances 0.000 description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910002244 LaAlO3 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- 150000002910 rare earth metals Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
Method, semi-conductor device manufacturing method.The invention provides the manufacture method of a kind of transistor utilizing clearance wall technology to form grid.In the method for the invention, side at dummy gate electrode storehouse, sequentially form the first clearance wall, the second clearance wall and third space wall, define, by removing the second clearance wall, the gate recess that width is controlled by the second clearance wall, in gate recess, then form required grid and gate insulator.In the present invention, utilize and be etched back to form clearance wall, it is not necessary to use extra mask, and, limit grid width by controlling the width of the second clearance wall, it is possible to achieve the formation of the grid lines of sub-22nm, and make technique have good controllability.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, relate to one and utilize clearance wall technology to form grid
The transistor device manufacture method of pole.
Background technology
Semiconductor integrated circuit technology, after the technology node entering into 90nm characteristic size, maintains or improves transistor
Can be more and more challenging.In sub-22nm field, high K gate insulation and metal gates are used to maintain and improve transistor
Performance.But, when gate line bar rule little progress enters sub-22nm field, the controllability of gate line bar formation process starts to run into very
A big difficult problem, people cannot control the pattern of obtained grid lines well, and this influences whether the performance of transistor.
Accordingly, it is desirable to provide a kind of new transistor fabrication process, it is possible to while forming the most tiny gate line bar, make
Technical process has a controllability, and can Simplified flowsheet, thus better assure that transistor performance.
Summary of the invention
The present invention provides the manufacture method of a kind of transistor, utilizes clearance wall technology to form grid, overcomes prior art
Present in process controllability difference defect.Its
According to an aspect of the present invention, the present invention provides a kind of method, semi-conductor device manufacturing method, it includes walking as follows
Rapid:
Semiconductor substrate is provided, this Semiconductor substrate is formed sti structure, and carries out well region injection；
Form the dummy gate electrode storehouse being made up of dummy gate electrode and dummy gate electrode insulating barrier；
Comprehensive deposition the first spacer material layer, and being etched back to, formed be positioned at described dummy gate electrode insulating barrier and
The first clearance wall on the side of described dummy gate electrode；
Comprehensive deposition the second spacer material layer, and be etched back to, form the side being positioned at described first clearance wall
On the second clearance wall；
Comprehensive deposition third space wall material layer, and be etched back to, form the side being positioned at described second clearance wall
On third space wall；
Remove described second clearance wall, form gate recess；
It is sequentially depositing gate insulating material layer and gate material layers；
Use CMP, remove the described gate material layers of part and described gate insulating material layer so that described grid material
Within the bed of material and described gate insulating material layer are only located at described gate recess, thus form grid and gate insulator；
Remove described dummy gate electrode and described dummy gate electrode insulating barrier.
In the method for the invention, described dummy gate electrode material is polysilicon.
In the method for the invention, the material of described first clearance wall and third space wall is Si3N4, described second gap
The material of wall is SiO2。
In the method for the invention, remove described second clearance wall, formed in the step of gate recess, use DHF or BOE
Wet corrosion technique remove described second clearance wall.
In the method for the invention, the width of described second clearance wall is 10-30nm.
In the method for the invention, described gate insulating material layer is high K gate insulation, and described gate material layers is gold
Belong to.
In the method for the invention, described CMP is with dummy gate electrode as terminal.
It is an advantage of the current invention that: successively formed in the side of dummy gate electrode storehouse the first clearance wall, the second clearance wall and
Third space wall, defines the gate recess that width is controlled by the second clearance wall, then at grid by removing the second clearance wall
Groove is formed required grid and gate insulator.In the present invention, utilize and be etched back to form clearance wall, it is not necessary to use volume
Outer mask, and, limit grid width by controlling the width of the second clearance wall, it is possible to achieve the gate line of sub-22nm
The formation of bar, and make technique have good controllability.
Accompanying drawing explanation
The manufacture method schematic flow sheet of the transistor device that Fig. 1-11 present invention provides；
Detailed description of the invention
Hereinafter, by the specific embodiment shown in accompanying drawing, the present invention is described.However, it should be understood that these describe simply
Exemplary, and it is not intended to limit the scope of the present invention.Additionally, in the following description, eliminate known features and technology
Describe, to avoid unnecessarily obscuring idea of the invention.
The present invention provides a kind of method, semi-conductor device manufacturing method, specifically relate to and relates to a kind of clearance wall technology that utilizes
Transistor fabrication process, referring to accompanying drawing 1-11, will describe the method, semi-conductor device manufacturing method that the present invention provides in detail.
First, see accompanying drawing 1, form dummy gate electrode insulating barrier 2, dummy gate electrode 3 on semiconductor substrate 1.
Specifically, it is provided that Semiconductor substrate 1, the present embodiment have employed monocrystalline substrate, alternatively, it is possible to use germanium
Substrate or other suitable Semiconductor substrate.Sti structure can be formed the most on semiconductor substrate 1 and carry out well region injection
(being not shown).Then, one layer of dummy gate electrode insulating layer material, e.g. SiO are first deposited on substrate 1 surface2Or high K
Gate dielectric materials thin film.High-K gate insulant has and compares SiO2Bigger dielectric constant, to transistor device performance more
Favorably.Gate insulator in the present invention be selected from one or a combination set of following material constitute one or more layers: Al2O3,
HfO2, including HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOxAnd HfLaSiOxAt least one interior
Hafnio high K dielectric material, including ZrO2、La2O3、LaAlO3、TiO2, or Y2O3At least one at interior rare earth base high K dielectric material
Material, SiO2, SiON, Si3N4.The thickness of dummy gate electrode insulating layer material is preferably 0.5-10nm, depositing operation for example, CVD.It
After, depositing dummy gate electrode material, dummy gate electrode material is polysilicon.After deposition dummy gate electrode material, carry out photoresist coating,
Photoetching, defines dummy gate electrode figure, to dummy gate electrode material and dummy gate electrode insulating layer material order etching, thus is formed
Figure including the dummy gate electrode storehouse of dummy gate electrode insulating barrier 2 and dummy gate electrode 3.
Then, accompanying drawing 2, comprehensive deposition the first spacer material layer 4 are seen.The material of the first spacer material layer is preferred
For Si3N4, use the depositing operation of good shape retention so that it is cover the end face of dummy gate electrode 3 and illusory grid with desired thickness
Pole insulating barrier 2 and the side of dummy gate electrode 3.
Then, see accompanying drawing 3, form the first clearance wall 5.Specifically include, after forming the first spacer material layer 4,
First spacer material layer 4 is carried out the anisotropic technique that is etched back to, removes end face and substrate 1 table being positioned at dummy gate electrode 3
The first spacer material layer 4 on face, only retains and is positioned between first on the side of dummy gate electrode insulating barrier 2 and dummy gate electrode 3
Gap wall material layer 4, thus form the first clearance wall 5.
Then, accompanying drawing 4, comprehensive deposition the second spacer material layer 6 are seen.The material of the second spacer material layer is
SiO2, use the depositing operation of good shape retention so that it is cover end face and first gap of dummy gate electrode 3 with desired thickness
On the side of wall 5.
Then, see accompanying drawing 5, form the second clearance wall 7.Specifically include, after forming the second spacer material layer 6,
Second spacer material layer 6 is carried out the anisotropic technique that is etched back to, removes end face and substrate 1 table being positioned at dummy gate electrode 3
The second spacer material layer 6 on face, only retains the second spacer material layer 6 being positioned at the first clearance wall 5 side, thus is formed
Second clearance wall 7.
Then, accompanying drawing 6, comprehensive deposition third space wall material layer 8 are seen.The material of third space wall material layer is permissible
Identical with the material of the first spacer material layer, preferably Si3N4, use the depositing operation of good shape retention so that it is with desired
Thickness covers end face and the side of the second clearance wall 7 of dummy gate electrode 3.
Then, see accompanying drawing 7, form third space wall 9.Specifically include, after forming third space wall material layer 8,
Third space wall material layer 8 is carried out the anisotropic technique that is etched back to, removes end face and substrate 1 table being positioned at dummy gate electrode 3
Third space wall material layer 8 on face, only retains the third space wall material layer 8 being positioned on the side of the second clearance wall 7, thus
Form third space wall 8.So far, the side at dummy gate electrode storehouse has defined first clearance wall the 5, second clearance wall 7 and
The compound clearance wall of three clearance wall 9 compositions.
It follows that see accompanying drawing 8, remove the second clearance wall 7, between the first clearance wall 5 and third space wall 9, form grid
Pole groove 10.Wet etching can be used to remove the second clearance wall 7, specifically can use DHF or BOE.Gate recess 10 is used for
Grid to be prepared and gate insulator is accommodated in technique subsequently.The width of the second clearance wall 7 limits gate recess
The width of 10, thus also define the width of the grid formed afterwards.In view of grid width, the width of the second clearance wall 7 can
To be formed 10-30nm.
Then, see accompanying drawing 9, sequentially form gate insulating material layer 11 and gate material layers 12.Gate insulating material layer
11 use high K gate insulation, selected from one or a combination set of following material constitute one or more layers: Al2O3, HfO2, including
HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOxAnd HfLaSiOxAt least one be situated between at interior hafnio height K
Material, including ZrO2、La2O3、LaAlO3、TiO2, or Y2O3At least one at interior rare earth base high K dielectric material, SiO2,
SiON, Si3N4.The thickness of gate insulating material layer 11 is preferably 0.5-5nm, depositing operation for example, CVD.Gate material layers 12
For metal.In accompanying drawing 9, gate insulating material layer 11 and gate material layers 12 cover sidewall and the bottom surface of gate recess 10.
Then, see accompanying drawing 10, use CMP, remove the gate insulating material layer 11 outside gate recess 10 and grid
Pole material layer 12.This step CMP, can remove the gate dielectric materials outside gate recess 10 with dummy gate electrode 3 as terminal
Layer 11 and gate material layers 12.Through this step, gate insulating material layer 11 and gate material layers 12 are only located at gate recess 10
Within, define required gate insulator 13 and grid 14.
Then, see accompanying drawing 11, remove dummy gate electrode 3 and dummy gate electrode insulating barrier 2, complete grid and prepare.Wherein, first
Clearance wall 5 and third space wall 9 respectively become the clearance wall of grid 14 both sides.Other techniques of transistor can be carried out afterwards,
Including forming source and drain, LDD/Halo, source and drain contact etc..
So far, the present invention proposes and describes the manufacture method of the transistor utilizing clearance wall technology formation grid in detail.
In the method for the invention, in the side of dummy gate electrode, successively form the first clearance wall, the second clearance wall and third space wall,
Define, by removing the second clearance wall, the gate recess that width is controlled by the second clearance wall, in gate recess, then form institute
The grid needed and gate insulator.In the present invention, utilize and be etched back to form clearance wall, it is not necessary to use extra mask,
Further, grid width is limited by controlling the width of the second clearance wall, it is possible to achieve the formation of the grid lines of sub-22nm, and
And make technique have good controllability.
Above by reference to embodiments of the invention, the present invention is described.But, these embodiments are only used to
Bright purpose, and be not intended to limit the scope of the present invention.The scope of the present invention is limited by claims and equivalent thereof.
Without departing from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall
Within the scope of the present invention.
Claims (7)
1. a method, semi-conductor device manufacturing method, it is characterised in that comprise the steps:
Semiconductor substrate is provided, this Semiconductor substrate is formed sti structure, and carries out well region injection；
Form the dummy gate electrode storehouse being made up of dummy gate electrode and dummy gate electrode insulating barrier；
Comprehensive deposition the first spacer material layer, and being etched back to, is formed and is positioned at described dummy gate electrode insulating barrier and described
The first clearance wall on the side of dummy gate electrode；
Comprehensive deposition the second spacer material layer, and be etched back to, formed and be positioned on the side of described first clearance wall
Second clearance wall；
Comprehensive deposition third space wall material layer, and be etched back to, formed and be positioned on the side of described second clearance wall
Third space wall；
Remove described second clearance wall, form gate recess；
It is sequentially depositing gate insulating material layer and gate material layers；
Use CMP, remove the described gate material layers of part and described gate insulating material layer so that described gate material layers
Within being only located at described gate recess with described gate insulating material layer, thus form grid and gate insulator；
Remove described dummy gate electrode and described dummy gate electrode insulating barrier.
Method the most according to claim 1, it is characterised in that described dummy gate electrode material is polysilicon.
Method the most according to claim 1, it is characterised in that the material of described first clearance wall and third space wall is
Si3N4, the material of described second clearance wall is SiO2。
Method the most according to claim 3, it is characterised in that remove described second clearance wall, forms the step of gate recess
In Zhou, the wet corrosion technique of DHF or BOE is used to remove described second clearance wall.
Method the most according to claim 1, it is characterised in that the width of described second clearance wall is 10-30nm.
Method the most according to claim 1, it is characterised in that described gate insulating material layer is high K gate insulation, institute
Stating gate material layers is metal.
Method the most according to claim 1, it is characterised in that described CMP is with described dummy gate electrode as terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210283261.XA CN103578952B (en) | 2012-08-09 | 2012-08-09 | Method, semi-conductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210283261.XA CN103578952B (en) | 2012-08-09 | 2012-08-09 | Method, semi-conductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103578952A CN103578952A (en) | 2014-02-12 |
| CN103578952B true CN103578952B (en) | 2016-12-28 |
Family
ID=50050476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210283261.XA Active CN103578952B (en) | 2012-08-09 | 2012-08-09 | Method, semi-conductor device manufacturing method |
Country Status (1)
| Country | Link |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874341A (en) * | 1996-10-30 | 1999-02-23 | Advanced Micro Devices, Inc. | Method of forming trench transistor with source contact in trench |
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN1612297A (en) * | 2003-10-27 | 2005-05-04 | 上海宏力半导体制造有限公司 | Method for forming grooved grid structure |
| EP1296366B1 (en) * | 2001-09-24 | 2008-05-07 | Sharp Kabushiki Kaisha | Metal gate CMOS and method of manfacturing the same |
| CN101593684A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Polysilicon gate, semiconductor device and forming method thereof |
| CN102479694A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Formation method of metal gate and MOS transistor |
-
2012
- 2012-08-09 CN CN201210283261.XA patent/CN103578952B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874341A (en) * | 1996-10-30 | 1999-02-23 | Advanced Micro Devices, Inc. | Method of forming trench transistor with source contact in trench |
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| EP1296366B1 (en) * | 2001-09-24 | 2008-05-07 | Sharp Kabushiki Kaisha | Metal gate CMOS and method of manfacturing the same |
| CN1612297A (en) * | 2003-10-27 | 2005-05-04 | 上海宏力半导体制造有限公司 | Method for forming grooved grid structure |
| CN101593684A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Polysilicon gate, semiconductor device and forming method thereof |
| CN102479694A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Formation method of metal gate and MOS transistor |
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| CN103578952A (en) | 2014-02-12 |
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