CN104008976A - Manufacturing method of groove power device - Google Patents
Manufacturing method of groove power device Download PDFInfo
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- CN104008976A CN104008976A CN201410253267.1A CN201410253267A CN104008976A CN 104008976 A CN104008976 A CN 104008976A CN 201410253267 A CN201410253267 A CN 201410253267A CN 104008976 A CN104008976 A CN 104008976A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000002513 implantation Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000000717 retained effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000000016 photochemical curing Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of manufacturing of semiconductor power devices, and particularly relates to a manufacturing method of a groove power device. The manufacturing method includes the steps that after a field oxide layer is formed in a U-shaped groove of the device, photoresist is adopted as a sacrificial dielectric layer, the developed photoresist is reserved only in the U-shaped groove by controlling the exposure time and the development time of the photoresist, then the exposed portions of the field oxide layer are etched away, then the photoresist is stripped, then a gate oxide layer is oxidized, a polycrystalline silicon grid electrode is deposited, and finally source electrode metal making contact with a source area and a channel doping area is formed. The manufacturing method has the advantages of being simple and reliable in technical process, easy to control and the like, the production cost of the groove power device can be lowered, and yield of the groove power device can be improved.
Description
Technical field
The invention belongs to semiconductor power device manufacturing technology field, particularly relate to a kind of manufacture method of groove power device.
Background technology
The development that deepens continuously along with modern microelectric technique, power MOS transistor is fast with the high and low loss of its input impedance, switching speed, without second breakdown, safety operation area is wide, dynamic property good, easily realize large electric current, conversion efficiency advantages of higher with front utmost point coupling, substituting gradually bipolar device becomes the main flow that current power device develops.Known power device mainly contains the types such as planar diffusion type MOS transistor and groove type MOS transistor.Take groove type MOS transistor as example, and this device is because having adopted vertical channel type structure, and its Area Ratio planar diffusion type MOS transistor is much smaller, so its current density improves a lot.
The manufacture method of groove type MOS transistor: as shown in Figure 1, first in this device, form U-shaped groove, then on the surface of this U-shaped groove, form thick field oxide layer 101, follow depositing polysilicon sacrificial dielectric layer 102 and sacrifice polysilicon dielectric layer is carried out to etching, sacrifice polysilicon dielectric layer 102 after etching is only retained in the certain depth of U-shaped groove, etch away afterwards the thick field oxide exposing, in the thick field oxide layer place oxidation etching away, form one deck thin gate oxide 103 again, in forming thin gate oxide 103 processes, can on the surface of sacrifice polysilicon dielectric layer, form oxide layer simultaneously, next, as shown in Figure 2, the method of using plasma etching, etch away the oxide layer on sacrifice polysilicon dielectric layer 102 surfaces, and continue to etch away sacrifice polysilicon dielectric layer 102, then etch away gate oxide 103, then re-start the oxidation of gate oxide 104 and the deposit of polysilicon gate 105, finally form again source region and contact with source metal.
The manufacture method of above-mentioned groove type MOS transistor device, when carrying out thin gate oxide 103 oxidations, can form oxide layer on sacrifice polysilicon dielectric layer surface, thereby blocked being connected of sacrifice polysilicon dielectric layer 102 and outer electrode, for not affecting this connection, need to be by etching away the oxide layer on sacrifice polysilicon dielectric layer surface, but can cause damage to thin gate oxide 103 again when carrying out etching, therefore need eating away sacrifice polysilicon dielectric layer 102 and thin gate oxide 103 in the same time, re-start again the oxidation of gate oxide and the deposit of polysilicon gate, this just makes the manufacturing process of this device very complicated, not only manufacturing cost is high, and reduced the rate of finished products of this device.How to overcome the deficiencies in the prior art and become one of focus of studying in current semiconductor power device manufacturing technology field.。
Summary of the invention
The object of the invention is to provide for overcoming the deficiencies in the prior art a kind of manufacture method of groove power device, the present invention adopts photoresist to substitute polysilicon as sacrificial dielectric layer, can simplify the manufacturing process of groove power device, reduce the manufacturing cost of groove power device and improve its rate of finished products.
The manufacture method of a kind of groove power device proposing according to the present invention, its concrete steps comprise:
(1) in the Semiconductor substrate of the first doping type, carry out channel ion injection, form the channel doping district of the second doping type;
(2) on the surface of described Semiconductor substrate, form hard mask layer;
(3) adopt photoetching and lithographic method, in described Semiconductor substrate, form U-shaped groove;
(4) surface oxidation at described U-shaped groove forms ground floor insulation film;
Characterized by further comprising:
(5) deposit one deck photoresist exposure, develop, make photoresist after developing only be retained in described U-shaped groove and be positioned at the bottom in described channel doping district;
(6) etch away the described ground floor insulation film exposing;
(7) divest photoresist;
(8) oxidation forms second layer insulation film;
(9) deposit ground floor conductive film this ground floor conductive film is carried out to etching, the described ground floor conductive film after etching is lower than the surface of described Semiconductor substrate;
(10) the three-layer insulated film of deposit this three-layer insulated film is carried out to etching, the described three-layer insulated film after etching is lower than the surperficial hard mask layer of described Semiconductor substrate;
(11) etch away hard mask layer;
(12) carry out Implantation, in described Semiconductor substrate, the source region of the first doping type is formed on the top in described channel doping district;
(13) carry out photoetching, expose the source region of the described the first doping type of part;
(14) take photoresist carves etching is carried out in the source region of the described the first doping type of the part exposing as mask, along this exposure place, carry out afterwards the Implantation of the second doping type, in described Semiconductor substrate, form the doped region of the high-dopant concentration in the channel doping district contacting with external metallization;
(15) finally remove deposited metal after photoresist, form the source metal contacting with channel doping district with described source region.
The further preferred version of the present invention is:
Step of the present invention (1) and the described the first doping type of step (12) are N-shaped doping, and step (1) and the described the second doping type of step (14) are p-type doping.
Step of the present invention (1) and the described the first doping type of step (12) are p-type doping, and step (1) and the described the second doping type of step (14) are N-shaped doping.
The material of the described ground floor insulation film of step of the present invention (4) is silica, and its thickness is 20～300 nanometers.
The material of the described second layer insulation film of step of the present invention (8) is silica, and its thickness is 4～30 nanometers.
The material of the described three-layer insulated film of step of the present invention (10) is silica or for silicon nitride, its thickness is 50～500 nanometers.
The material of the described ground floor conductive film of step of the present invention (9) is the polysilicon of doping or is metallic conduction material.
The channel doping district of the described the second doping type of step of the present invention (1) can etch away after hard mask layer described in step (11), adopts ion injection method, in described Semiconductor substrate, forms.
The principle that realizes of the present invention is: the present invention forms after thick field oxide layer in the U-shaped groove of described device, in the alternative traditional handicraft of the photoresist of usining, polysilicon is as sacrificial dielectric layer, by controlling the time for exposure of photoresist, control again the degree of depth of photoresist photocuring reaction, then the time of controlling photoresist developing is only retained in the certain depth of U-shaped groove the photoresist after development, to etch away the thick field oxide exposing, then divest photoresist, then carry out the oxidation of gate oxide and the deposit of polysilicon gate.
The present invention compared with prior art its remarkable advantage is:
The one, the present invention is the exposure of whole to the exposure of photoresist, does not need to manufacture mask plate and carries out Alignment Process, therefore can not increase technology difficulty, and the spin coating proceeding of photoresist than the depositing technics of polysilicon be easy to control, cost is low.
The 2nd, the photoresist process that goes that the present invention adopts can not cause damage to Semiconductor substrate, does not therefore need to carry out the pre-oxidation of gate oxide, after removing photoresist, can directly carry out the oxidation of gate oxide and the deposit of polysilicon gate.Table 1 is to form after field oxide on the surface of device U-shaped groove, the contrast of the main distinction of the manufacturing process of groove power device of the present invention and the manufacturing process of existing groove power device, as shown in Table 1, the present invention adopts photoresist as sacrificial dielectric layer, although photoetching process can increase step of exposure, but can dispense step of gate oxide pre-oxidation and two steps of oxide layer etching, simplify on the whole and optimized the manufacturing process of groove power device, thereby can reduce the production cost of groove power device and improve its rate of finished products.
Table 1: the contrast table of technique of the present invention and the prior art manufacturing process main distinction
| Key step | Prior art | The present invention |
| 1 | Depositing polysilicon | Spin coating photoresist |
| 2 | Polysilicon returns quarter | Exposure, development |
| 3 | Field oxide etching | Field oxide etching |
| 4 | Gate oxide pre-oxidation | / |
| 5 | Anisotropic etching oxide layer | / |
| 6 | Etching polysilicon | Remove photoresist |
| 7 | Oxide layer etching | / |
| 8 | Gate oxide oxidation | Gate oxide oxidation |
| 9 | Polysilicon gate deposit | Polysilicon gate deposit |
Accompanying drawing explanation
Fig. 1 and Fig. 2 are the part process flow diagrams in the manufacture method of known groove power device.
Fig. 3 to Figure 11 is the process flow diagram of an embodiment of the manufacture method of groove power device of the present invention.
Figure 12 and Figure 13 are the generalized sections that the manufacture method of employing groove power device of the present invention obtains two embodiment of groove power device.
Embodiment
For the specific embodiment of the present invention is clearly described, listed diagram in Figure of description, has amplified the thickness in layer of the present invention and region, and shown in feature size do not represent actual size; Accompanying drawing is schematically, should not limit scope of the present invention.In specification, listed embodiment should not only limit to the given shape in region shown in accompanying drawing, but comprise that deviation that resulting shape causes as manufactured etc., the curve that etching obtains for another example conventionally have crooked or mellow and full feature, but all with rectangle, represent in embodiments of the present invention; In the following description, the term Semiconductor substrate of using can be regarded as and comprises the just semiconductor wafer in processes, also comprises other prepared thin layer thereon simultaneously.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
Fig. 3 to Figure 11 is the process flow diagram that the manufacture method of a kind of groove power device of application the present invention proposition is manufactured an embodiment of three groove power devices in parallel simultaneously, and its concrete implementation step is as follows successively:
In conjunction with Fig. 3, first channel ion is provided in the Semiconductor substrate providing and injects the channel doping district 202 that forms the second doping type, in the Semiconductor substrate of being somebody's turn to do, also include the drain region 200 of the first doping type of high-dopant concentration and the drift region 201 of the first doping type of low doping concentration.
The material of described Semiconductor substrate can be selected gallium nitride etc. on carborundum, the silicon on insulator or the silicon on silicon, carborundum, GaAs, gallium nitride, insulator; The first doping type and the second doping type are contrary doping type, and when the first doping type is N-shaped doping, the second doping type is p-type doping; Corresponding, when the first doping type is p-type doping, the second doping type is N-shaped doping.
The silicon substrate of take is below described the manufacture method of groove power device of the present invention as example.
In conjunction with Fig. 4, on the surface of described Semiconductor substrate, form a hard mask layer 301, this hard mask layer 301 comprises one deck thin oxide layer and thick layer silicon nitride layer, thin oxide layer is for improving the stress between silicon nitride layer and Semiconductor substrate, then adopt photoetching process and etching technics, in Semiconductor substrate, form U-shaped groove.
In conjunction with Fig. 5, at the surface oxidation of the U-shaped groove of device, form ground floor insulation film 203, this ground floor insulation film 203 is as thick field oxide layer, and its material is silica, and its thickness range is 20～300 nanometers; Next, spin coating one deck photoresist 302 exposure, develop, make photoresist 302 after developing only be retained in U-shaped groove and be positioned at the bottom in channel doping district 202; Wherein: by controlling the time for exposure of photoresist, control the degree of depth of photoresist photocuring reaction, the photoresist after the time of then controlling photoresist developing makes to develop is only retained in the interior of U-shaped groove and is positioned at the bottom in described channel doping district 202.
In conjunction with Fig. 6, etch away the ground floor insulation film 203 exposing, and divest photoresist 302, then oxidation forms second layer insulation film 204, and this second layer insulation film 204 is as gate oxide, and its material is silica, and its thickness range is 4～30 nanometers; Before carrying out the oxidation of gate oxide 204, the oxide impurity on 202 surfaces, channel doping district that can first expose by the hydrofluoric acid clean of diluting.
In conjunction with Fig. 7, deposit ground floor conductive film 205 also carries out etching to this ground floor conductive film 205, and the ground floor conductive film 205 after etching should be lower than the surface of described Semiconductor substrate; The material of this ground floor conductive film 205 both can be the polysilicon of doping, also can be metallic conduction material.
In conjunction with Fig. 8, the three-layer insulated film 206 of deposit also carries out etching to this three-layer insulated film 206, and the three-layer insulated film 206 after etching should be lower than the surface of hard mask layer 301; The material of three-layer insulated film is silica or silicon nitride, and its thickness range is 50～500 nanometers.
In conjunction with Fig. 9, etch away hard mask layer 301, the three-layer insulated film 206 of then take carries out Implantation as mask, and in described Semiconductor substrate, the source region 207 of the first doping type is formed on the top in described channel doping district 202.
In conjunction with Figure 10, deposit one deck photoresist 303 exposure, development are to expose the source region 207 of part the first doping type, thereby the photoresist of then take comes out channel doping district 202 as mask carries out etching to source region 207 parts that expose, along this exposure place, carry out afterwards the Implantation of the second doping type, in described Semiconductor substrate, form the doped region 208 of the high-dopant concentration in the channel doping district 202 contacting with external metallization.
In conjunction with Figure 11, finally remove photoresist 303, then deposited metal is to form the source metal 209 contacting with 207He channel doping district, source region 202.
The specific embodiment of the present invention need to further illustrate:
By photoetching process, expose behind part source region 207, when being carried out to etching, this source region 207 can not be etched to the surface in channel doping district 202, then the Implantation that carries out the second doping type forms the doped region 208 of high-dopant concentration in Semiconductor substrate, forms afterwards structure after source metal as shown in figure 12; Adopt the method can reduce the time in etching source region 207, and with high-dopant concentration the doping ion of doped region 208 the source region 207 part transoids that are not etched to 202 surfaces, channel doping district are fallen, thereby make 208Yu channel doping district, doped region 202 contacts of high-dopant concentration.
When forming source region, can not select take three-layer insulated film 206 is mask, and first by a step photoetching process, define the position in source region, then the photoresist of take carries out the formation source region, top 207 in Implantation described channel doping district 202 in Semiconductor substrate of the first doping type as mask, and then define the position of substrate contact by a step photoetching process, and take Implantation that photoresist carries out the second doping type as mask and in Semiconductor substrate, form the doped region 208 of the high-dopant concentration in the channel doping district 202 contacting with external metallization; Form afterwards structure after source metal as shown in figure 13.Adopt the method can dispense the etching to Semiconductor substrate, but can increase by a step photoetching process.
The channel doping district 202 of the second doping type also can be after hard mask layer 301 be etched away, employing ion injection method forms, etch away after hard mask layer 301, take three-layer insulated film 206 as mask carries out Implantation, in described Semiconductor substrate, form the channel doping district 202 of the second doping type.
In the specific embodiment of the present invention, all explanations not relating to belong to the known technology of this area, can be implemented with reference to known technology.
Above embodiment and embodiment are the concrete supports to the manufacture method technological thought of a kind of groove power device of the present invention's proposition; can not limit protection scope of the present invention with this; every technological thought proposing according to the present invention; the change of any equivalent variations of doing on the technical program basis or equivalence, all still belongs to the scope that technical solution of the present invention is protected.
Claims (8)
1. a manufacture method for groove power device, comprises the following steps:
(1) in the Semiconductor substrate of the first doping type, carry out channel ion injection, form the channel doping district of the second doping type;
(2) on the surface of described Semiconductor substrate, form hard mask layer;
(3) adopt photoetching and lithographic method, in described Semiconductor substrate, form U-shaped groove;
(4) surface oxidation at described U-shaped groove forms ground floor insulation film;
Characterized by further comprising:
(5) deposit one deck photoresist exposure, develop, make photoresist after developing only be retained in described U-shaped groove and be positioned at the bottom in described channel doping district;
(6) etch away the described ground floor insulation film exposing;
(7) divest photoresist;
(8) oxidation forms second layer insulation film;
(9) deposit ground floor conductive film this ground floor conductive film is carried out to etching, the ground floor conductive film after etching is lower than the surface of described Semiconductor substrate;
(10) the three-layer insulated film of deposit this three-layer insulated film is carried out to etching, the three-layer insulated film after etching is lower than the surperficial hard mask layer of described Semiconductor substrate;
(11) etch away hard mask layer;
(12) carry out Implantation, in described Semiconductor substrate, the source region of the first doping type is formed on the top in described channel doping district;
(13) carry out photoetching, expose the source region of the described the first doping type of part;
(14) take photoresist carves etching is carried out in the source region of the described the first doping type of the part exposing as mask, along this exposure place, carry out afterwards the Implantation of the second doping type, in described Semiconductor substrate, form the doped region of the high-dopant concentration in the channel doping district contacting with external metallization;
(15) finally remove deposited metal after photoresist, form the source metal contacting with channel doping district with described source region.
2. the manufacture method of groove power device according to claim 1, is characterized in that step (1) and the described the first doping type of step (12) are N-shaped doping, and step (1) and the described the second doping type of step (14) are p-type doping.
3. the manufacture method of groove power device according to claim 1, is characterized in that step (1) and the described the first doping type of step (12) are p-type doping, and step (1) and the described the second doping type of step (14) are N-shaped doping.
4. the manufacture method of groove power device according to claim 1, is characterized in that the material of the described ground floor insulation film of step (4) is silica, and its thickness is 20～300 nanometers.
5. the manufacture method of groove power device according to claim 1, is characterized in that the material of the described second layer insulation film of step (8) is silica, and its thickness is 4～30 nanometers.
6. the manufacture method of groove power device according to claim 1, the material that it is characterized in that the described three-layer insulated film of step (10) is silica or is silicon nitride, its thickness is 50～500 nanometers.
7. the manufacture method of groove power device according to claim 1, is characterized in that polysilicon or metallic conduction material that the material of the described ground floor conductive film of step (9) is doping.
8. the manufacture method of groove power device according to claim 1, the channel doping district that it is characterized in that the described the second doping type of step (1) can etch away after hard mask layer described in step (11), adopt ion injection method, in Semiconductor substrate, form.
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| CN201410253267.1A CN104008976A (en) | 2014-06-09 | 2014-06-09 | Manufacturing method of groove power device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112309975A (en) * | 2020-10-27 | 2021-02-02 | 杭州士兰微电子股份有限公司 | Manufacturing method of bidirectional power device |
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|---|---|---|---|---|
| CN112309975A (en) * | 2020-10-27 | 2021-02-02 | 杭州士兰微电子股份有限公司 | Manufacturing method of bidirectional power device |
| CN112309975B (en) * | 2020-10-27 | 2024-02-02 | 杭州士兰微电子股份有限公司 | Manufacturing method of bidirectional power device |
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