CN104253041A - Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method - Google Patents
Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method Download PDFInfo
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- CN104253041A CN104253041A CN201310265444.3A CN201310265444A CN104253041A CN 104253041 A CN104253041 A CN 104253041A CN 201310265444 A CN201310265444 A CN 201310265444A CN 104253041 A CN104253041 A CN 104253041A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000009825 accumulation Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 74
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract 3
- 229940090044 injection Drugs 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method which includes the steps of forming an IGBT structure on the front side of a silicon wafer until finishing deposition of an interlayer dielectric; covering the interlayer dielectric with a protective film; thinning the silicon wafer from the back thereof and forming a P-type layer on the back of the thinned silicon wafer; removing the protective film and annealing the silicon wafer at the temperature higher than 500 DEG C; and forming metal layers on the P-type layer and on the surface of the interlayer dielectric. Since the P-type layer is annealed before the metal layer is formed in the method, the annealing temperature of the P-type layer is not limited by metal melting temperature and can be high, and further the NPT IGBT formed has high performance. The method is compatible with the traditional technology and accordingly has high efficiency.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of non-through insulated-gate bipolar transistor.
Background technology
Traditional non-through insulated-gate bipolar transistor (Non Punch Through Insulated Gate Bipolar Transistor; NPT IGBT) back side P-type layer manufacture method mainly; after front operation completes; give disk front pasting protective film again, then carry out thinning back side and inject ion.
Be limited to front metal fusion temperature, the annealing temperature of back side P-type layer can not higher than 500 degree.This makes the injection efficiency of NPT IGBT back side P-type layer very low, causes the forward conduction voltage drop Vce of NPT IGBT not to be reduced to ideal value, greatly limit the performance of NPT IGBT.
Summary of the invention
Based on this, be necessary to provide a kind of can the manufacture method of non-through insulated-gate bipolar transistor of improving performance.
A manufacture method for non-through insulated-gate bipolar transistor, comprises the steps: to form igbt structure to the complete inter-level dielectric of accumulation at front side of silicon wafer; Described inter-level dielectric forms silicon nitride layer and oxide layer successively as diaphragm; Start described silicon chip to carry out reduction processing from described silicon chip back side, and the silicon chip back side after thinning forms P-type layer; Remove described diaphragm, and annealing in process is carried out to described silicon chip; Wherein annealing temperature is greater than 500 degrees Celsius; At described P-type layer and inter-level dielectric forming metal layer on surface.
Wherein in an embodiment, described silicon nitride layer and the oxide layer of being formed successively on inter-level dielectric comprises as the step of diaphragm: silicon chip is carried out silicon nitride grown; Silicon chip is carried out oxide layer growth; Remove the oxide layer of described silicon chip back side; Remove the silicon nitride layer of described silicon chip back side; The diaphragm that described inter-level dielectric is formed comprises the silicon nitride layer and oxide layer that are formed at described inter-level dielectric surface.
Wherein in an embodiment, the step of the oxide layer of described removal silicon chip back side comprises: in the oxide layer of described front side of silicon wafer, apply photoresist; Wet etching is adopted to remove the oxide layer of described silicon chip back side.
Wherein in an embodiment, the step of the silicon nitride layer of described removal silicon chip back side comprises: remove the photoresist that the oxide layer of described front side of silicon wafer applies; Nitride Strip liquid is adopted to remove the silicon nitride layer of described silicon chip back side.
Wherein in an embodiment, described P-type layer adopts ion implantation mode to be formed, and injection ion is boron.
Wherein in an embodiment, described ion implantation adopts front to inject board process.
Wherein in an embodiment, described annealing temperature is greater than 800 degrees Celsius.
Wherein in an embodiment, described reduction processing is by wafer thinning to 300 ~ 500 micron.
Wherein in an embodiment, described reduction processing adopts cmp.
In said method, owing to being the annealing in process of carrying out P-type layer before metal level is formed, therefore the annealing in process temperature of P-type layer can not be subject to the restriction of melting temperature metal, and higher temperature can be adopted to carry out annealing in process, thus the performance of the NPT IGBT formed is higher.Meanwhile, the method is also compatible with traditional handicraft, and therefore efficiency is higher.
Accompanying drawing explanation
Fig. 1 is the manufacture method flow chart of the non-through insulated-gate bipolar transistor of an embodiment;
Fig. 2 to Figure 10 is the sectional schematic diagram of the intermediate structure that in Fig. 1 flow process, each step is corresponding.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is further described.
As shown in Figure 1, be the manufacture method flow chart of non-through insulated-gate bipolar transistor of an embodiment.The method comprises the steps.
Step S101: form igbt structure to the complete inter-level dielectric of accumulation at front side of silicon wafer.This step is identical with the technique of traditional manufacture igbt.
This step mainly comprises:
Step S111: form field oxygen layer in N-type substrate, and carry out photoetching formation injection zone.With reference to figure 2, N-type substrate 100 is silicon chips of lightly doped n-type impurity.By being oxidized to obtain to N-type substrate 100 surface oxygen layer 200 of showing up.By carrying out photoetching to field oxygen layer 200, by field oxygen layer 200 needing the corresponding part forming p type island region etch with N-type substrate 100, oxygen layer 200 on the scene forms injection zone.
Step S112: carry out ion implantation to injection zone, forms heavily doped p type island region.With reference to figure 3, the part that oxygen layer 200 on the scene etches, being also injection zone part, by injecting ion, N-type substrate 100 forming heavily doped p type island region 112.Then oxidation processes is carried out to above p type island region 112.
Step S113: carry out the process of grid oxygen and polysilicon deposition, and carry out photoetching and obtain grid structure.With reference to figure 4, N-type substrate 100 surface is oxidized again, forms grid oxide layer 300.And deposit forms polysilicon layer 400 on grid oxide layer 300.Photoetching is carried out to described polysilicon layer 400, obtains grid structure 402.Wherein, when polysilicon deposition, be carry out deposition process to whole silicon chip, therefore at the back side of silicon chip, also namely the back side of N-type substrate 100 is also formed with this polysilicon layer 400.
Step S114: carry out ion implantation, forms lightly doped p type island region.With reference to figure 5, carry out ion implantation in grid structure 402 both sides, form lightly doped p type island region 114.This lightly doped p type island region 114 is merged with the heavily doped p type island region 112 phase counterdiffusion formed before.Then the grid oxide layer 300 above lightly doped p type island region 114 is removed.
Step S115: carry out ion implantation in the position of removing described grid oxide layer, form heavily doped N-type region.With reference to figure 6, on lightly doped p type island region 114, also namely carry out ion implantation form heavily doped N-type region 116.
Step S116: accumulation inter-level dielectric.With reference to figure 7, whole silicon chip forms inter-level dielectric 500.To be used in inter-level dielectric 500 semiconductor fabrication process insulate and isolate conductive layers.In traditional technique, namely manufacture metal level after the complete inter-level dielectric of accumulation, carry out metal connecting line technique.
The concrete steps comprised in front side of silicon wafer formation igbt structure to the step of the complete inter-level dielectric of accumulation in above-mentioned steps S111 ~ S116 and step S101.So far the Facad structure of IGBT is not fully formed.
After above-mentioned steps completes, continue to perform following steps.
Step S102: form silicon nitride layer and oxide layer successively as diaphragm on described inter-level dielectric.This step mainly comprises:
S121: silicon chip is carried out silicon nitride grown.The growth of silicon nitride adopts the mode of deposit.With reference to figure 8, owing to being carry out deposition process to whole silicon chip, therefore the back side of silicon chip also creates silicon nitride layer 610.
S122: silicon chip is carried out oxide layer growth.Oxide layer growth adopts the mode of hot oxide growth.Continue with reference to figure 8.Oxide layer 620 is formed on silicon nitride layer 610 layers.
S123: the oxide layer removing described silicon chip back side.The oxide layer 620 of described front side of silicon wafer applies photoresist protect it, then adopt wet etching to remove the oxide layer 620 of silicon chip back side.
S124: the silicon nitride layer removing described silicon chip back side.The photoresist applied in removal step S123, then adopts Nitride Strip liquid to remove the silicon nitride layer 610 of described silicon chip back side.
S125: the polysilicon layer removing described silicon chip back side.Dry etching is adopted to remove the polysilicon layer 400 of described silicon chip back side.
Like this, namely the oxide layer 620 of silicon chip back side, silicon nitride layer 610 and polysilicon layer 400 are removed, and leave the oxide layer 620 of front side of silicon wafer and silicon nitride layer 610 as protective layer.
Step S103: start described silicon chip to carry out reduction processing from described silicon chip back side, and the silicon chip back side after thinning forms P-type layer.With reference to figure 9, P-type layer 700 is formed at the back side of N-type substrate 100.Described P-type layer 700 adopts ion implantation mode to be formed, and injection ion is boron.Front directly can be adopted to inject board and to carry out this ion implantation, with traditional process compatible.Described reduction processing can adopt the mode such as mechanical lapping or chemical corrosion to carry out reduction processing.Silicon chip entirety is thinned to 300 ~ 500 microns.
Step S104: remove described diaphragm, and annealing in process is carried out to described silicon chip; Wherein annealing temperature is greater than 500 degrees Celsius.The mode removing this diaphragm can adopt the method for abovementioned steps S123 and step S124, removes silicon nitride layer 610 and the oxide layer 620 of front side of silicon wafer respectively.Because now metal level is not also formed, higher temperature (being greater than 500 degrees Celsius) can be used to carry out annealing in process.For making annealing effect better, described annealing temperature is greater than 800 degrees Celsius.
Step S105: at described P-type layer and inter-level dielectric forming metal layer on surface.With reference to Figure 10, inter-level dielectric 500 is formed metal level 800, P-type layer 700 is formed metal level 900.Wherein, inter-level dielectric 500 being formed metal level 800 is first on inter-level dielectric 500, form through hole (contact hole), and then form metal level 800.After formation metal level 800 and 900, draw the electrode of grid, collector electrode and source electrode respectively, the final complete structure forming NPT IGBT.
In said method, owing to being the annealing in process of carrying out P-type layer before metal level is formed, therefore the annealing in process temperature of P-type layer can not be subject to the restriction of melting temperature metal, and higher temperature can be adopted to carry out annealing in process, thus the performance of the NPT IGBT formed is higher.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a manufacture method for non-through insulated-gate bipolar transistor, comprises the steps:
Igbt structure is formed to the complete inter-level dielectric of accumulation at front side of silicon wafer;
Described inter-level dielectric forms silicon nitride layer and oxide layer successively as diaphragm;
Start described silicon chip to carry out reduction processing from described silicon chip back side, and the silicon chip back side after thinning forms P-type layer;
Remove described diaphragm, and annealing in process is carried out to described silicon chip; Wherein annealing temperature is greater than 500 degrees Celsius;
At described P-type layer and inter-level dielectric forming metal layer on surface.
2. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, described silicon nitride layer and the oxide layer of being formed successively on inter-level dielectric comprises as the step of diaphragm:
Silicon chip is carried out silicon nitride grown;
Silicon chip is carried out oxide layer growth;
Remove the oxide layer of described silicon chip back side;
Remove the silicon nitride layer of described silicon chip back side;
Remove the polysilicon layer of described silicon chip back side; The diaphragm that described inter-level dielectric is formed comprises the silicon nitride layer and oxide layer that are formed at described inter-level dielectric surface.
3. the manufacture method of non-through insulated-gate bipolar transistor according to claim 2, is characterized in that, the step of the oxide layer of described removal silicon chip back side comprises:
The oxide layer of described front side of silicon wafer applies photoresist;
Wet etching is adopted to remove the oxide layer of described silicon chip back side.
4. the manufacture method of non-through insulated-gate bipolar transistor according to claim 3, is characterized in that, the step of the silicon nitride layer of described removal silicon chip back side comprises:
Remove the photoresist that the oxide layer of described front side of silicon wafer applies;
Nitride Strip liquid is adopted to remove the silicon nitride layer of described silicon chip back side.
5. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, described P-type layer adopts ion implantation mode to be formed, and injection ion is boron.
6. the manufacture method of non-through insulated-gate bipolar transistor according to claim 5, is characterized in that, described ion implantation adopts front to inject board process.
7. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, the step of described removal diaphragm comprises:
Wet etching BOE is adopted to etch away the oxide layer of described front side of silicon wafer;
Nitride Strip liquid is adopted to remove the silicon nitride layer of described front side of silicon wafer.
8. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, described annealing temperature is greater than 800 degrees Celsius.
9. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, described reduction processing is by wafer thinning to 300 ~ 500 micron.
10. the manufacture method of non-through insulated-gate bipolar transistor according to claim 1, is characterized in that, described reduction processing adopts cmp.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310265444.3A CN104253041A (en) | 2013-06-27 | 2013-06-27 | Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method |
| PCT/CN2014/079275 WO2014206191A1 (en) | 2013-06-27 | 2014-06-05 | Method for manufacturing non-punch through insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310265444.3A CN104253041A (en) | 2013-06-27 | 2013-06-27 | Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method |
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| CN104253041A true CN104253041A (en) | 2014-12-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310265444.3A Pending CN104253041A (en) | 2013-06-27 | 2013-06-27 | Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method |
Country Status (2)
| Country | Link |
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| CN (1) | CN104253041A (en) |
| WO (1) | WO2014206191A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847909A (en) * | 2017-01-05 | 2017-06-13 | 江苏中科君芯科技有限公司 | A kind of manufacture method of FS types IGBT device |
| CN110246761A (en) * | 2019-06-19 | 2019-09-17 | 上海华力集成电路制造有限公司 | A method of removal backside of wafer silicon nitride film |
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| CN107731662A (en) * | 2017-11-22 | 2018-02-23 | 上海华力微电子有限公司 | A kind of method for improving device uniformity |
| CN109103242B (en) * | 2018-09-30 | 2023-12-15 | 江苏明芯微电子股份有限公司 | Silicon controlled rectifier chip with through structure and production method thereof |
| CN111799161B (en) * | 2019-04-08 | 2023-08-29 | 上海积塔半导体有限公司 | Manufacturing method of low-voltage shielded gate field effect transistor |
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2013
- 2013-06-27 CN CN201310265444.3A patent/CN104253041A/en active Pending
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2014
- 2014-06-05 WO PCT/CN2014/079275 patent/WO2014206191A1/en active Application Filing
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| US20020137264A1 (en) * | 2001-03-23 | 2002-09-26 | Ming-Jer Kao | Method of fabrication thin wafer IGBT |
| US20070026577A1 (en) * | 2005-07-27 | 2007-02-01 | International Rectifier Corp. | High voltage non punch through IGBT for switch mode power supplies |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106847909A (en) * | 2017-01-05 | 2017-06-13 | 江苏中科君芯科技有限公司 | A kind of manufacture method of FS types IGBT device |
| CN110246761A (en) * | 2019-06-19 | 2019-09-17 | 上海华力集成电路制造有限公司 | A method of removal backside of wafer silicon nitride film |
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| WO2014206191A1 (en) | 2014-12-31 |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant before: Wuxi CSMC Semiconductor Co., Ltd. |
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