CN106847909A - A kind of manufacture method of FS types IGBT device - Google Patents
A kind of manufacture method of FS types IGBT device Download PDFInfo
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- CN106847909A CN106847909A CN201710007355.7A CN201710007355A CN106847909A CN 106847909 A CN106847909 A CN 106847909A CN 201710007355 A CN201710007355 A CN 201710007355A CN 106847909 A CN106847909 A CN 106847909A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 66
- 239000010703 silicon Substances 0.000 claims abstract description 66
- 239000011241 protective layer Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010931 gold Substances 0.000 claims abstract description 7
- 229910052737 gold Inorganic materials 0.000 claims abstract description 7
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 3
- 239000000956 alloy Substances 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000002360 preparation method Methods 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 abstract description 11
- 150000002500 ions Chemical class 0.000 description 15
- 230000008569 process Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010511 deprotection reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention relates to a kind of manufacture method of FS types IGBT device, comprise the following steps：Silicon chip back side is thinning；N-type impurity is injected at the back side of silicon chip；Oxide layer protective layer is grown at the back side of silicon chip；Conventional steps are carried out to the front of silicon chip until ILD is deposited；SIN medium protective layers are deposited in the front of silicon chip；Silicon chip front surface coated photoresist and photoresist dried；Removal silicon chip back side oxide layer protective layer；Remove the protection of front side of silicon wafer with photoresist；In the ion of the back side implanting p-type heavy doping collecting zone of silicon chip；In the back side deposited oxide layer protective layer of silicon chip；Remove the SIN protective layers of front side of silicon wafer；Front to silicon chip proceeds conventional step since depositing step；Remove the oxide layer protective layer of silicon chip back side；The back side to silicon chip carries out conventional back of the body gold and alloy step.The present invention can carry out good activation to the p-type ion implanting of silicon chip back side, be unlikely to introduce Facad structure other influences and then cause the drift of electrical parameter again.
Description
Technical field
The present invention relates to a kind of preparation method of IGBT device, present invention relates especially to a kind of FS types IGBT
（Insulated Gate Bipolar Transistor, igbt）The manufacture method of device, the invention belongs to
Semiconductor fabrication process technical field.
Background technology
Internally in structure more like the MOSFET of vertical stratification, only it increased highly doped P+ to IGBT in drain side
Layer, referred to as colelctor electrode.In IGBT device, the p-type heavily doped region for newly increasing injects hole when IGBT device is turned on to base,
Base conductivity modulation effect is produced, so as to substantially increase the current handling capability of device.
IGBT device is broadly divided into PT types, NPT types and FS types by its vertical structure, and wherein PT types IGBT is with highly doped P
+ be substrate, on be that N+ cushions add the saturation voltage drop of the N- substrates being epitaxially formed, PT IGBT to have negative temperature coefficient, and
It, using low-doped N- bases as substrate, is the starting point of production procedure that NPT type IGBT and FS types IGBT is.FS IGBT be
Electric field stop layer is increased on the basis of NPT IGBT（N buffer layers）.NPT types and FS types IGBT are because of the positive temperature of its conduction voltage drop
Coefficient is spent, is easy to characteristic used in parallel and is widely used.
The existing preparation method of FS type IGBT devices be usually after the completion of the technique of front, then give disk front patch protection
Film, then carries out thinning back side, chemical attack and N-type ion implanting and pushes away trap, p-type ion implanting and activation, finally enters again
The golden manufacture craft to complete whole IGBT device of the row back of the body.
For thicker N buffer layers（10um and more than）FS devices, general way be before the technique of front,
Front side of silicon wafer is first deposited into one layer of dielectric layer as protective layer, then silicon chip back side is carried out thinning and is injected N-type impurity, then
Experience high temperature is annealed to form thicker N buffer layers for a long time, then overleaf dielectric layer deposited again（Generally aoxidize
Layer, thickness 2000A ~ 8000A）Back-protective is carried out, front technique is continued after removing positive protective layer again afterwards, until completing
The removal of back side dielectric layer, p-type ion implanting are carried out after the technique of front again with activation, back of the body gold until completing flow.
In above manufacture craft, annealing temperature after the p-type ion implanting of the back side has had gold due at this moment front side of silicon wafer
Belong to aluminium and be restricted（Not above 500 DEG C）, generally 400~450 DEG C.This is temperature limited will to cause p type impurity ion
Activity ratio it is very low, and then cause the forward conduction voltage drop Vce (sat) of IGBT can not to reach ideal value.
For this has improvement project again, will have thicker N buffer layers FS type IGBT back sides p-type ion injection and
Before activation advances to front metal deposit, but general way is before front metal is deposited, after Poly deposits（Or just
A certain operation before the Metal deposition of face）Front side of silicon wafer is protected with one layer of dielectric layer.Then wet etching removes the back side
Oxide layer, back side p-type ion implanting（Activation or not）, front is returned again to after the protection of back side dielectric layer, remove positive
Protective dielectric layer, continues to complete front technique, followed by back of the body gold process until completing flow.
On back side p-type ion front metal completion before which procedure carry out, we select after ILD DEP/
Before the etching of hole.Reason is as follows：（1）There is drawback in the injection that back side p-type ion is done after Poly deposits：To front after Poly deposits
Technique can experience multiple thermal process during completing（At least PWELL pushes away the thermal process of trap）, can so change back side p-type collection
The Impurity Distribution situation of electrode district, and then largely influence the characteristic of device；（2）Consider from above-mentioned angle, in ILD DEP
The injection of back side p-type ion is carried out before afterwards/hole etching, the activity ratio of back side p type impurity can be both lifted, the back of the body can not be changed again
The distributed area of face p type impurity.
On after ILD DEP/hole etching before carry out the injection of back side p-type ion, overleaf before p-type ion implanting, silicon
The positive protective layer of piece can select gluing or thick oxide layer or PECVD SiN or polysilicon or SIN adds oxide layer plus light
The combination of photoresist.And there are some drawbacks in existing front protecting method unavoidably：（1）Simple gluing protection may cause machine
Platform stain it is not recommended that selection；（2）The problem that simple thick oxide layer protection is present is that back side wet etching can also corrode the guarantor
Sheath, and there is problem in the front technique deprotection layer of back：Wet etching speed is uncontrollable, and dry etching is easily caused
The damage of ILD layer；（3）And protect front to there is also a problem with simple SiN：Wet etching removes 2000 ~ 4000A of the back side
The general BOE of oxide layer corrode, the bad selection of thickness of front protecting dielectric layer PECVD SiN.SiN it is too thick so that stress too
Big then silicon chip has the risk of warpage；If too thin, PECVD is loose in itself, and BOE has certain corrosion rate to SiN, may cause
SiN regional areas cannot play preferable protective effect, cause Facad structure impacted and then have influence on electrical parameter；（4）It is single
The problem that pure polysilicon protection is present be polysilicon removal can only dry method removal, dry etching easily causes to damage to ILD；
（5）The combination protection of various film layers, can increase operation again.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided it is a kind of can to the p-type of silicon chip back side from
Son injection carries out good activation and is unlikely to introduce Facad structure other influences and then cause the one of the drift of electrical parameter again
Plant the manufacture method of FS type IGBT devices.
According to the technical scheme that the present invention is provided, a kind of preparation method of FS types IGBT device is comprised the following steps：
It is a, silicon chip back side is thinning；
B, the back side injection N-type impurity in silicon chip；
C, the back side growth oxide layer protective layer in silicon chip；
D, the front to silicon chip carry out Conventional process steps until ILD depositing steps；
E, the front deposit SIN medium protective layers in silicon chip；
F, silicon chip front surface coated protection dry with photoresist and by photoresist；
The oxide layer protective layer that g, removal silicon chip back side are deposited；
Protection coated by h, removal front side of silicon wafer is with photoresist；
I, silicon chip back side implanting p-type heavy doping collecting zone ion；
J, the back side deposited oxide layer protective layer in silicon chip；
The SIN protective layers that k, removal front side of silicon wafer are deposited；
L, the front to silicon chip proceed conventional hole lithography step, front metal depositing step since depositing step, close
The lithography step of golden step, the depositing step of passivation layer and passivation layer；
The oxide layer protective layer that m, removal silicon chip back side are deposited；
N, the back side to silicon chip carry out conventional back of the body gold step and alloy step.
The present invention can carry out good activation to the p-type ion implanting of silicon chip back side, the preceding back side p-type of front metal from
Good protection can be carried out before and after son injection to front side of silicon wafer, and is unlikely to tie front in front protecting layer removal process
Structure introduces other influences and then causes the drift of electrical parameter.In addition before overleaf after p-type ion implanting/back metal deposit,
The back side can be protected, be unlikely to that the back side is caused to damage or polluted.
Specific embodiment
With reference to specific embodiment, the invention will be further described.
A kind of preparation method of FS types IGBT device is comprised the following steps：
A, a kind of N-type FZ substrates of preparation, require according to voltage class, by wafer thinning to required thickness；
B, front side of silicon wafer deposit layer protective layer typically use thermal oxidation method, and the equal growing silicon oxide of positive and negative, frontside oxide layer is made
Be protective layer, back-protective layer injects screen layer as N-type impurity, then carry out back side N-type impurity injection and through it is long when
Between Warming processes high with formed thickness N buffer layers；
C, silicon chip the back side growth oxide layer as back-protective layer；
D, front technique is carried out, polysilicon gate, p-well, N+ areas, P+ areas are formed, until ILD depositing steps（That is ILD DEP are walked
Suddenly）；
E, the front dielectric layer deposited protective layer in silicon chip, the front surface coated protection in silicon chip are dried with photoresist, front side of silicon wafer
The dielectric layer selection 2000A of deposit or so SIN, is used to protect front film layer and structure not to be damaged by machinery or other forms；
The oxide layer protective layer that g, removal silicon chip back side are deposited, the general method using wet etching is removed；
Protection coated by h, removal front side of silicon wafer is with photoresist；
I, the back side implanting p-type impurity in silicon chip, activation or do not activate, due to being that before metal, activationary temperature can be with>500
℃；
J, it is used to protect back side heavily doped P-type layer, the dielectric layer for being deposited in the back side deposit layer of oxide layer dielectric layer of silicon chip
Thickness be 2000A ~ 4000A；
The SIN dielectric layers that k, removal step (e) front side of silicon wafer are deposited, the general method using wet etching is removed；
L, continuation front side of silicon wafer technique form contact hole pattern, and deposit metal forms metal interconnection, passivation layer deposited, by electrode window
Mouth windowing etching；
The oxide layer dielectric layer that m, removal step (j) silicon chip back side are deposited；
N, the back side to silicon chip carry out back of the body gold and alloying.
Background technology processing step of the invention is substantially as follows：Main thought is all the activation effect of p-type heavy doping in the back side to be improved
Rate, advances to back side p-type heavy doping and injected before front metal and activated, but is broadly divided into three below aspect here and comes
Consider：
1st, p-type specific injection process before front metal in the back side is different:It is generally divided into front technique and starts preceding injection, front
Before metal/Poly deposit after or front metal before/ILD deposit after；
2nd, the protection of the preceding Facad structure of back side p-type injection：Polysilicon is used as protective layer, polysilicon+silica as protective layer, oxygen
SiClx is as protective layer, SIN+ silica+photoresist as protective layer；
3rd, the protection at the back side after back side p-type is injected：Matcoveredn or unprotect layer.
The process step of the invention is as follows with the main distinction of background technology processing step：
First, thick N buffer layers was formed before front side of silicon wafer technique；
2nd, on the basis of previous bar, back side p-type heavy doping collecting zone is formed before front metal deposit, can improve P
The activation efficiency of type impurity, effectively reduces saturation voltage drop；
3rd, it is most importantly on the basis of first and Article 2, takes back side p type impurity and inject preceding front ILD layer
The protection at the back side after protection and the injection of back side p type impurity；
Particularly the preceding front of back side p type impurity injection takes SiN (thickness is 2000 ~ 4000A)+photoresist combination as protection
Layer.The advantage of this protective layer combination is:
Facad structure obtains good protection and avoids ILD by machinery or other forms by SIN when the 1, overleaf carrying out p-type injection
Damage；
2nd, the photoresist that a thickness is coated on SIN be ensure protect during the chemical liquids removal back side thick oxide layer SIN by mechanical or
The damage of other forms；
3rd, after the activation of back side p type impurity, before wafer turn-over continues technical face, back side deposit layer of oxide layer is protected, and is made
Back side P-type layer is not damaged by machinery or other forms.
Claims (1)
1. a kind of preparation method of FS types IGBT device, it is characterised in that the preparation method is comprised the following steps：
It is a, silicon chip back side is thinning；
B, the back side injection N-type impurity in silicon chip；
C, the back side growth oxide layer protective layer in silicon chip；
D, the front to silicon chip carry out Conventional process steps until ILD depositing steps；
E, the front deposit SIN medium protective layers in silicon chip；
F, silicon chip front surface coated protection dry with photoresist and by photoresist；
The oxide layer protective layer that g, removal silicon chip back side are deposited；
Protection coated by h, removal front side of silicon wafer is with photoresist；
I, silicon chip back side implanting p-type heavy doping collecting zone ion；
J, the back side deposited oxide layer protective layer in silicon chip；
The SIN protective layers that k, removal front side of silicon wafer are deposited；
L, the front to silicon chip proceed conventional hole lithography step, front metal depositing step since depositing step, close
The lithography step of golden step, the depositing step of passivation layer and passivation layer；
The oxide layer protective layer that m, removal silicon chip back side are deposited；
N, the back side to silicon chip carry out conventional back of the body gold step and alloy step.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710007355.7A CN106847909A (en) | 2017-01-05 | 2017-01-05 | A kind of manufacture method of FS types IGBT device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710007355.7A CN106847909A (en) | 2017-01-05 | 2017-01-05 | A kind of manufacture method of FS types IGBT device |
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| CN106847909A true CN106847909A (en) | 2017-06-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003885A (en) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | Production method, epitaxial wafer and the semiconductor devices of twin polishing epitaxial wafer |
| CN109994544A (en) * | 2018-01-03 | 2019-07-09 | 宁波达新半导体有限公司 | The manufacturing method of field stop type power device |
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|---|---|---|---|---|
| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) device |
| CN104253041A (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method |
| CN104425255A (en) * | 2013-08-30 | 2015-03-18 | 无锡华润上华半导体有限公司 | Manufacturing method for NPT IGBT (non-punch through insulated gate bipolar transistor) |
-
2017
- 2017-01-05 CN CN201710007355.7A patent/CN106847909A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) device |
| CN104253041A (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Non punch through insulated gate bipolar transistor (NPT IGBT) manufacturing method |
| CN104425255A (en) * | 2013-08-30 | 2015-03-18 | 无锡华润上华半导体有限公司 | Manufacturing method for NPT IGBT (non-punch through insulated gate bipolar transistor) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994544A (en) * | 2018-01-03 | 2019-07-09 | 宁波达新半导体有限公司 | The manufacturing method of field stop type power device |
| CN109003885A (en) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | Production method, epitaxial wafer and the semiconductor devices of twin polishing epitaxial wafer |
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Application publication date: 20170613 |