TWI715711B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer and a conducting pillar. The substrate has a trench　therein. The first dielectric layer includes an embedded part and a protruded part. The embedded part is located in the trench, and covers a bottom part and a side wall of the trench. The protruded part is connected with the embedded part, and protruded from a surface of the substrate. The conducting pillar includes a body and a capping part. The body is located in the trench and surrounded by the embedded part of the first dielectric layer. The capping part is connected with the main part, and covers the protruded part of the first dielectric layer.

Description

Semiconductor element and its manufacturing method

The present invention relates to a semiconductor element and its manufacturing method, and more particularly to an embedded semiconductor element and its manufacturing method.

In recent years, embedded semiconductor devices with trench structures have been developed, which can increase the integration of semiconductor devices to meet the demands of continuously shrinking semiconductor devices. However, during the manufacturing process of the trench structure, the dielectric layer in the trench may be damaged during the subsequent formation of contact holes, causing problems such as leakage or component failure.

The present invention provides a semiconductor element and a manufacturing method thereof, which can reduce or prevent the dielectric layer in the trench from being damaged during the subsequent formation of the first conductor layer contact hole.

The present invention provides a method for manufacturing a semiconductor element, including the following steps. A hard mask layer with openings is formed on the substrate. The substrate exposed by the opening is removed to form a trench in the substrate. A first dielectric layer is formed on the substrate, wherein the first dielectric layer covers the surface of the trench and the sidewall of the opening. A conductive pillar covering the top surface of the first dielectric layer is formed in the opening and the trench. A second dielectric covering the hard mask layer is formed on the substrate Floor. Using the substrate and the conductive pillars as the stop layer, the second dielectric layer, the first dielectric layer and the hard mask layer are patterned to form contact holes. A first conductor layer is formed in the contact hole.

In some embodiments of the present invention, the method of forming the above-mentioned conductive pillar may include the following steps. A conductor layer is formed on the first dielectric layer, and the conductor layer is filled in the trench. The conductive layer above the substrate is removed, leaving the conductive layer in the openings and trenches to form a conductive pillar covering the top surface of the first dielectric layer.

In some embodiments of the present invention, the above-mentioned hard mask layer may include silicon oxide, silicon nitride, or a combination thereof.

The invention provides a semiconductor element, which includes a substrate, a first dielectric layer and a conductor post. The base has trenches. The first dielectric layer includes an embedded part and a protruding part. The embedded part is located in the trench and covers the bottom and side walls of the trench. The protruding part is connected to the embedded part and protrudes from the surface of the base. The conductor post includes a main body part and a top cover part. The main body is located in the trench and is surrounded by the embedded part. The top cover part is connected to the main body part and covers the protruding part.

In some embodiments of the present invention, the surface of the top cover portion may have a depression.

In some embodiments of the present invention, the above-mentioned top cover portion may be V-shaped, r-shaped, γ-shaped, ν-shaped, or a combination thereof.

In some embodiments of the present invention, the aforementioned conductor post may be Y-shaped.

In some embodiments of the present invention, the above-mentioned first dielectric layer may be U-shaped, horseshoe-shaped, or a combination thereof.

The semiconductor device of the present invention may further include a second dielectric layer and a first conductor layer. The second dielectric layer is on the substrate. The first conductor layer passes through the second dielectric layer and is electrically connected to the conductor post.

In some embodiments of the present invention, the above-mentioned first dielectric layer may also be located between the second dielectric layer and the substrate.

The semiconductor device of the present invention may further include a hard mask layer. The hard mask layer is located between the first dielectric layer and the substrate.

Based on the above, in the embodiment of the present invention, after the trench is formed in the substrate, the hard mask layer is not removed but remains on the substrate, so that the subsequently formed first dielectric layer can not only be located in the trench but also protrude from the substrate s surface. In addition, the conductive layer subsequently formed in the trenches also extends to cover the top surface of the first dielectric layer. Therefore, the first dielectric layer in the trenches can be reduced or prevented from being damaged when the first conductive layer contact holes are subsequently formed. In this way, the leakage current between the conductive pillars in the trench and the substrate can be avoided, and the failure of the semiconductor device can be avoided.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

7, 9: opening

8, 19: mask layer

10: Base

11: Hard mask material layer

11a, 11b: hard mask layer

12: Ditch

13, 13a, 13b: first dielectric layer

13a1: Embedded part

13a2: protrusion

14: Conductor layer

14a: Conductor post

14a1: main body

14a2: Top cover

15, 15a: second dielectric layer

16: second conductor layer

17: Contact hole

18, 18a: the first conductor layer

20: opening

113a2: contact surface

W: width

1A to 1J are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the invention.

2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.

1A to 1J are the fabrication of a semiconductor device according to an embodiment of the present invention Schematic cross-section of the manufacturing process The manufacturing method of the semiconductor element of this embodiment includes the following steps.

1A, a hard mask material layer 11 and a patterned mask layer 8 with openings 7 are sequentially formed on the substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate. For example, the semiconductor substrate may include a silicon substrate. The silicon substrate can be an undoped silicon substrate, an N-type doped silicon substrate, or a P-type doped silicon substrate. The material of the hard mask material layer 11 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the method for forming the hard mask material layer 11 may include a spin coating method, a chemical vapor deposition method, or a combination thereof, and the present invention is not limited thereto. The patterned mask layer 8 is, for example, a patterned photoresist layer, and its formation method is, for example, to form the photoresist layer first, and then perform exposure and development processes.

1B, the patterned mask layer 8 is used as a mask to perform an etching process to remove the hard mask material layer 11 of the exposed part of the opening 7 to form a hard mask with an opening 9 on the substrate 10 Layer 11a. The etching process is, for example, an anisotropic etching process, an isotropic etching process, or a combination thereof.

Subsequently, the substrate 10 exposed by the opening 9 is removed to form a trench 12 in the substrate 10. The method of forming the trench 12 may include using the patterned mask layer 8 as a mask to perform an etching process on the substrate 10 exposed by the opening 7. The etching process is, for example, an anisotropic etching process, an isotropic etching process, or a combination thereof. In this embodiment, two trenches 12 are formed as an example for description. However, the present invention is not limited to the number of trenches 12, and those skilled in the art can adjust the number of trenches 12 according to design requirements. It is worth noting that after the trench 12 is formed, the hard mask layer 11a still remains on the substrate 10. After that, the patterned mask layer 8 is removed.

1B and 1C, a first dielectric layer 13 is formed in the trench 12. The first dielectric layer 13 is formed on the substrate 10 and covers the surface of the trench 12 and the sidewall of the opening 9. In some embodiments, the first dielectric layer 13 is a conformal layer. The material of the first dielectric layer 13 can be, for example, silicon oxide, silicon nitride, or a combination thereof. In other embodiments, the material of the first dielectric layer 13 may be a high dielectric constant material. The high dielectric constant material may be a dielectric material with a dielectric constant greater than 4, greater than 7, or greater than 10. The high dielectric constant material may include metal oxide. For example, the metal oxide may be a rare earth metal oxide, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, aluminum oxide (aluminum oxide). ), yttrium oxide, lanthanum oxide, lanthanum aluminum oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, zirconium Hafnium zirconium oxide, strontium bismuth tantalate, or a combination thereof. The method of forming the first dielectric layer 13 may include a chemical vapor deposition method or an atomic layer deposition method.

Next, a conductor layer 14 is formed on the substrate 10. The conductive layer 14 covers the substrate 10 and fills the first dielectric layer 13 in the trench 12. In some embodiments, the conductive layer 14 covers the first dielectric layer 13 and fills the trench 12 and the opening 9. The material of the conductor layer 14 may include a semiconductor material, a metal material, a metal alloy material, or a combination thereof. The semiconductor material is, for example, doped polysilicon, undoped polysilicon, silicon germanium material, or a combination thereof. The metal material may include metal or metal compound. The metal is, for example, copper, aluminum, tantalum, or tungsten. The metal compound is, for example, tantalum nitride or titanium nitride. The metal alloy material is, for example, copper aluminum alloy or tungsten, titanium, cobalt, or an alloy formed of nickel and polysilicon. The formation method of the conductor layer 14 is, for example, electroplating, electroless plating, chemical vapor deposition, or atomic layer deposition.

Please refer to FIGS. 1C and 1D to remove a portion of the conductor layer 14 above the surface of the substrate 10, leaving the conductor layer 14 in the opening 9 and the trench 12. In some embodiments, the conductor layer left in the trench 12 has a columnar shape, which is also called a conductor column 14a. The conductive pillar 14a is located in the opening 9 and the trench 12 and covers the top surface of the trench 12 and the first dielectric layer 13 in the opening 9. In other words, the first dielectric layer 13 at the top corner of the opening 9 is covered by the conductor post 14a. In some embodiments, the method of removing part of the conductor layer 14 may include a chemical mechanical polishing method, an etching back method, or a combination thereof.

1E, a second dielectric layer 15 is formed on the substrate 10. The second dielectric layer 15 covers the conductive pillar 14a and the first dielectric layer 13 on the hard mask layer 11a. In some embodiments, the second dielectric layer 15 is an inter-layer dielectric. The material of the second dielectric layer 15 may be the same as or different from the material of the first dielectric layer 13. In some embodiments, the material of the second dielectric layer 15 may include silicon oxide, silicon nitride, or a low dielectric constant material. For example, the dielectric constant of the low dielectric constant material can be lower than 4. The low dielectric constant material may include flourinated silicate glass, organosilicate glass, parylene, fluorinated amorphous carbon (FLAC) or hydrogenated Hydrogen Silsesquioxane (HSQ) etc. In some embodiments, the method for forming the second dielectric layer 15 may include a chemical vapor deposition method, a spin coating method, or a combination thereof.

1F, a patterned mask layer 19 having an opening 20 is formed on the second dielectric layer 15. The position of the opening 20 may correspond to the conductor post 14a. In other words, the orthographic projection of the opening 20 on the substrate 10 may at least overlap with the conductor post 14a, or at least cover the area of the conductor post 14a. The patterned mask layer 19 can be, for example, a patterned photoresist layer, and the method of forming it is, for example, to form a photoresist layer first, and then perform exposure and development processes. Cheng.

1G, the conductive pillar 14a and the substrate 10 are used as stop layers to perform an etching process to pattern the second dielectric layer 15, the first dielectric layer 13, and the hard mask layer 11a, thereby forming a contact hole 17 The second dielectric layer 15a, the first dielectric layer 13b, and the mask layer 11b, and the first dielectric layer 13a located in the trench 12. The contact hole 17 exposes the surface of the conductive pillar 14 a, the sidewall of the first dielectric layer 13 a and a part of the surface of the substrate 10. The etching process is, for example, an anisotropic etching process, an isotropic etching process, or a combination thereof.

In one embodiment, the conductor post 14a includes a main body portion 14a1 and a top cover portion 14a2. The main body 14a1 is located in the trench 12. The main body portion 14a1 is, for example, in the shape of a long column, extending from the inside of the base 10 to the surface of the base 10, and the bottom thereof may be a plane parallel to the surface of the base 10 or a curved surface. The sidewall of the main body 14a1 may be substantially perpendicular to the surface of the substrate 10, but is not limited to this. The top cover portion 14a2 protrudes from the surface of the base 10 and is connected to the main body portion 14a1. In some embodiments, the surface of the top cover portion 14a2 has a depression, so that the shape of the top cover portion 14a2 is V-shaped, r-shaped, γ-shaped, ν-shaped or a combination thereof. In other words, the conductor post 14a composed of the main body portion 14a1 and the top cover portion 14a2 may be Y-shaped.

The shape of the first dielectric layer 13a may include a U-shape, a horseshoe shape, or a combination thereof, so that the conductive pillar 14a is embedded therein, and the top end of the first dielectric layer 13a has a lead angle or a curved surface, so that the conductive pillar 14a can cover it. Top surface. In some embodiments, the first dielectric layer 13a may include embedded portions 13a1 and protruding portions 13a2. The embedded portion 13a1 is located in the trench 12, covers the bottom and side walls of the trench 12, and surrounds the main body 14a1. The embedded portion 13a1 is, for example, U-shaped, horseshoe-shaped, or a combination thereof. The protruding portion 13a2 is connected to the embedded portion 13a1 and protrudes from the surface of the base 10. In some embodiments, convex The contact surface 113a2 between the outlet portion 13a2 and the top cover portion 14a2 of the conductor post 14a includes a curved surface or an inclined surface. In other words, the closer to the top end of the protrusion 13a2, the smaller the width W of the protrusion 13a2, so that the protrusion 13a2 can be covered by the top cover portion 14a2 of the conductor post 14a. That is, the shape of the protrusion 13a2 may include a fan shape, a triangle shape, a trapezoid shape, or a combination thereof.

Since the top surface of the protrusion 13a2 is covered by the top cover 14a2, the top cover 14a2 can protect the protrusion 13a2 during the etching process of forming the contact hole 17, so that the protrusion 13a2 under the top cover 14a2 Can not be damaged or reduce the degree of damage during the etching process. In addition, since the embedding portion 13a1 of the first dielectric layer 13a is covered by the protruding portion 13a2, the protruding portion 13a2 can protect the embedding portion 13a1 underneath during the etching process of forming the contact hole 17 to prevent the embedding portion 13a1 from being etched. Therefore, the embedded portion 13a1 can maintain the required profile.

1H, a first conductive layer 18 is formed on the substrate 10. The conductor layer 18 covers the surface of the second dielectric layer 15 a and fills the contact hole 17 to cover the surface of the conductor post 14 and the substrate 10. In some embodiments, the material of the first conductor layer 18 is different from the material of the conductor post 14. The material of the first conductive layer 18 is, for example, a metal, a metal compound, or other conductive materials. The metal is, for example, copper, aluminum, tantalum, or tungsten. The metal alloy material is, for example, copper aluminum alloy. The formation method of the conductor layer 18 includes a chemical vapor deposition method or an electroplating method.

Afterwards, referring to FIG. 1I, using the second dielectric layer 15a as a stop layer, chemical mechanical polishing or etching back is performed to remove the first conductor layer 18 on the second dielectric layer 15a to form the first conductive layer 18 in the contact hole 17 A conductor layer 18a. The first conductive layer 18a passes through the second dielectric layer 15a and is electrically connected to the conductive pillar 14a.

1J, on the side of the substrate 10 opposite to the first conductor layer 18a The second conductor layer 16 is formed on the surface. The material of the second conductor layer 16 and the material of the first conductor layer 18 may be the same or different. For example, the material of the second conductive layer 16 may be metal, metal alloy or other conductive materials. The material of the second conductive layer 16 is, for example, a metal, a metal compound, or other conductive materials. The metal is, for example, copper, aluminum, tantalum, or tungsten. The metal alloy material is, for example, copper aluminum alloy. The formation method of the second conductor layer 16 includes a chemical vapor deposition method, a physical vapor deposition method, an electroplating method or a combination thereof.

In some embodiments, the substrate 10, the embedded portion 13a1 of the first dielectric layer 13a, and the conductive pillar 14a may form a Schottky diode. In other embodiments, a doped region may be formed in the substrate 10 around the trench 12, and the conductive layer 18 is used as a gate electrode, and the first dielectric layer 13a is used as a gate dielectric layer to form a transistor. In some embodiments, the transistor may be an insulated gate bipolar transistor (IGBT) or a field effect transistor (field effect transistor).

Next, the semiconductor element of the present embodiment will be explained using FIG. 1J. The semiconductor device includes a substrate 10, a first dielectric layer 13a, and a conductive pillar 14a. The substrate 10 has a trench 12. In this embodiment, two trenches 12 are taken as an example for description, but those with ordinary knowledge in the field can change the number of trenches according to design requirements, and the present invention is not limited thereto. The first dielectric layer 13a includes an embedded portion 13a1 and a protruding portion 13a2. The embedded portion 13a1 is located in the trench 12 and covers the bottom and sidewalls of the trench 12. The protruding portion 13a2 is connected to the embedded portion 13a1 and protrudes from the surface of the base 10.

The conductor post 14a includes a main body portion 14a1 and a top cover portion 14a2. The main body portion 14a1 is located in the trench 12 and is surrounded by the embedded portion 13a1. The top cover portion 14a2 is connected to the main body portion 14a1 and covers the protruding portion 13a2 of the first dielectric layer 13a. In some embodiments, the surface of the top cover portion 14a2 may have a depression. The top cover 14a2 may be V-shaped, r-shaped, γ-shaped, ν-shaped, or a combination thereof. In some embodiments, the first dielectric layer 13a may be U-shaped, Horseshoe shape or a combination thereof; the conductor post 14a may be Y-shaped.

The semiconductor device may further include a second dielectric layer 15a and a first conductive layer 18a. The second dielectric layer 15a is located on the substrate 10. The first conductive layer 18a passes through the second dielectric layer 15a and is electrically connected to the conductive pillar 14a. In addition, the semiconductor device may further include a first dielectric layer 13b and a hard mask layer 11b. The first dielectric layer 13b is located between the second dielectric layer 15a and the substrate 10. The hard mask layer 11b is located between the first dielectric layer 13b and the substrate 10. Furthermore, the semiconductor device may further include a second conductor layer 16. The second conductor layer 16 is located on the side of the substrate 10 opposite to the first conductor layer 18a. In some embodiments, the first conductive layer 18a is formed on the front surface of the substrate 10 as the first electrode; the second conductive layer 16 is formed on the back surface of the substrate 10 as the second electrode. Since the first conductive layer 18a is formed on the front surface of the substrate 10 and the second conductive layer 16 is formed on the back surface of the substrate 10, the first conductive layer 18a is also called a front electrode; and the second conductive layer 16 is also called a back electrode.

2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. The semiconductor element of this embodiment is similar to the semiconductor element shown in FIG. 1J, and only the differences will be discussed below, and the same or similar parts will not be repeated. The substrate 10 of this embodiment has a single trench 12, and therefore, the first conductive layer 18a is electrically connected to a single conductive post 14a in the trench 12.

In summary, in the embodiment of the present invention, after the trench is formed in the substrate, the hard mask layer is not removed but remains on the substrate, so that the subsequently formed first dielectric layer is not only located in the trench but also protruding from the substrate s surface. In addition, the conductive layer subsequently formed in the trenches also extends to cover the top surface of the first dielectric layer. Therefore, the first dielectric layer in the trenches can be reduced or prevented from being damaged when the first conductive layer contact holes are subsequently formed. In this way, leakage current can be avoided between the conductor post in the trench and the substrate. Furthermore, the problem of failure of semiconductor components can be avoided.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Base

11b‧‧‧Hard mask layer

12‧‧‧Ditch

13a, 13b‧‧‧First dielectric layer

13a1‧‧‧Embedded part

13a2‧‧‧Protrusion

14a‧‧‧Conductor post

14a1‧‧‧Main body

14a2‧‧‧Top cover

15a‧‧‧Second dielectric layer

16‧‧‧Second conductor layer

17‧‧‧Contact hole

18a‧‧‧First conductor layer

Claims (11)

A method for manufacturing a semiconductor element includes: forming a hard mask layer with an opening on a substrate; removing the substrate exposed by the opening to form a trench in the substrate; and forming a first dielectric on the substrate Layer, wherein the first dielectric layer covers the surface of the trench and the sidewalls of the opening; a conductive pillar covering the top surface of the first dielectric layer is formed in the opening and the trench; Forming a second dielectric layer covering the hard mask layer; using the substrate and the conductive pillar as a stop layer to pattern the second dielectric layer, the first dielectric layer, and the hard A mask layer to form a contact hole; and a first conductor layer is formed in the contact hole. According to the method for manufacturing a semiconductor device described in claim 1, wherein the method of forming the conductor post comprises: forming a conductor layer on the first dielectric layer, and the conductor layer is filled in the trench; And removing the conductive layer above the substrate, leaving the conductive layer in the opening and the trench to form the conductive pillar covering the top surface of the first dielectric layer. According to the method of manufacturing a semiconductor device described in the first item of the patent application, the hard mask layer includes silicon oxide, silicon nitride, or a combination thereof. A semiconductor component, including: A substrate with a trench; a first dielectric layer, including: an embedded part located in the trench, covering the bottom and sidewalls of the trench; and a protruding part, connected to the embedded part, protruding from the surface of the substrate and The first dielectric layer does not cover the surface of the substrate; and the conductor post includes: a main body part located in the trench, surrounded by the embedded part, and the bottom of the main body part and the first The embedded part of the dielectric layer is in direct contact; and the top cover part is connected to the main body part and covers the protruding part. The semiconductor device described in claim 4, wherein the surface of the top cover portion is recessed. The semiconductor device described in item 5 of the scope of the patent application, wherein the top cover portion is V-shaped, r-shaped, γ-shaped, ν-shaped or a combination thereof. The semiconductor device described in item 4 of the scope of patent application, wherein the conductor post is Y-shaped. The semiconductor device according to claim 4, wherein the first dielectric layer is U-shaped, horseshoe-shaped or a combination thereof. The semiconductor device described in item 4 of the scope of the patent application further includes: a second dielectric layer on the substrate; and a first conductor layer that passes through the second dielectric layer and is electrically connected to the conductor post Sexual connection. According to the semiconductor device described in claim 9, wherein the first dielectric layer is also located between the second dielectric layer and the substrate. The semiconductor device described in item 10 of the scope of patent application further includes a hard mask layer located between the first dielectric layer and the substrate.

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