TWI584433B - Semiconductor structure and manufacturing method thereof - Google Patents

Description

Semiconductor structure and manufacturing method thereof

The invention relates to the field of semiconductor manufacturing, in particular to a method for simultaneously forming a contact structure of a semiconductor element by using a mask layer on a metal gate with a plurality of etching processes.

As the integration of integrated circuits (ICs) continues to increase and the feature size continues to decrease, the interconnect line width and geometry of semiconductor components are becoming smaller and smaller. In general, the individual semiconductor elements in the integrated circuit are electrically connected to each other by the contact plug and the interconnect structure. Therefore, the plug structure and its process are becoming more and more important in the next generation of semiconductor manufacturing.

Due to the current process capability of the semiconductor back end of the line (BEOL), the current technology still cannot meet the high aspect ratio (HAR) contact hole etching process yield and improve the correlation accumulation. The process integration technology requires that the plug structure cannot be obtained by a single metal deposition or polishing process. In order to overcome these process obstacles, the industry is gradually making the required component patterns by means of double patterning (developing-etching-developing-etching, 2P2E). The two-stage metal deposition process replaces the conventional one-step metal deposition process. In general, conventional contact plug structures are broken down into two parts, one being a lower contact structure and the other being an upper metal structure (or referred to as a zeroth metal layer, M0). After the preparation of the underlying contact structure is completed, the upper metal structure is continuously formed thereon, and the upper metal structure is not limited to the columnar structure, and it may also be a strip structure. However, since the upper metal structure and the lower layer contact structure are The steps are completed in different steps, so that a barrier layer is located at the boundary between the upper metal structure and the lower contact structure, which may affect the conductivity of the contact plug structure, and the process step is also complicated.

Accordingly, there is a need for an improved interconnect structure and method of making the same to overcome the above disadvantages.

In order to solve the above problems, the present invention provides a semiconductor structure including a substrate, a first dielectric layer on the substrate, a metal gate, in the dielectric layer, and a source/drain region. Both sides of the metal gate, and a mask layer, are located on the metal gate, and the top end of the mask layer is flush with the top end of the first dielectric layer.

The present invention further provides a method for fabricating a semiconductor structure, comprising the steps of: firstly providing a substrate having a first dielectric layer formed thereon, at least one metal gate being located in the first dielectric layer, and at least a source/drain region is disposed on both sides of the metal gate, and then a second dielectric layer is formed on the first dielectric layer, and then a first etching process is performed on the first dielectric layer and the first Forming a plurality of first recesses in the two dielectric layers, exposing each of the source/drain regions, and performing a metal telluride process to form a metal telluride layer in the first recess and performing a first And a second etching process is formed in the first dielectric layer and the second dielectric layer, wherein the second recess exposes the metal gate.

The invention is characterized in that a mask layer is included at the top end of the metal gate, and the mask layer and the dielectric layer are selectively etched using different etching selectivity gases. In this way, the structure on the gate and the contact structure on the source/drain region can be completed at the same time, replacing the conventional underlying contact structure and the upper metal layer. (M0) A total of two parts, reducing the process steps.

1‧‧‧Semiconductor components

10‧‧‧Base

12‧‧‧Metal gate

12a‧‧‧Metal gate

12b‧‧‧Metal gate

12c‧‧‧Metal gate

14‧‧‧Source/bungee area

15‧‧‧ epitaxial layer

16‧‧‧Fin structure

17‧‧‧Shallow trench isolation

18‧‧‧ Sidewall

20‧‧‧etch stop layer

22‧‧‧First dielectric layer

24‧‧‧ mask layer

26‧‧‧Second dielectric layer

28‧‧‧Photoresist layer

28a‧‧‧Organic Dielectric Layer

28b‧‧‧Anti-reflective layer with enamel mask

28c‧‧‧ photoresist layer

30‧‧‧ openings

32‧‧‧First groove

34‧‧‧metal telluride layer

38‧‧‧Photoresist layer

38a‧‧‧Organic Dielectric Layer

38b‧‧‧矽 矽 抗 anti-reflective layer

38c‧‧‧ photoresist layer

40‧‧‧ openings

42‧‧‧second groove

44‧‧‧Barrier layer

46‧‧‧metal layer

52‧‧‧ first contact

54‧‧‧second contact

54A‧‧‧second contact

60‧‧‧ third dielectric layer

61‧‧‧metal layer

62‧‧‧Electrical through holes

64‧‧‧Wire

66‧‧‧ Third contact

E1‧‧‧ etching step

E2‧‧‧ etching step

E3‧‧‧ etching step

1 to 9 are schematic views showing the structure of a fin-shaped transistor device according to a first preferred embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the figure, it should be understood by those skilled in the art that it refers to the relative position of the object, and therefore can be flipped to present the same member, which should belong to the same specification. The scope of the disclosure is hereby stated.

Referring to FIGS. 1-9, a schematic structural view of a fin-shaped transistor component according to a first preferred embodiment of the present invention is shown. As shown in FIG. 1, first, a substrate 10 is provided, and the substrate 10 includes at least A metal gate 12 and at least one source/drain region 14 are located on opposite sides of each of the metal gates 12. Further, the substrate 10 may optionally include at least one fin structure 16, in this embodiment, a metal gate. 12 includes a metal material, and source/drain regions 14 may be formed in the substrate 10 on either side of the metal gate 12 by ion implantation, or fin structures formed on both sides of the metal gate 12. in. The substrate 10 around the metal gate 12 further includes at least one shallow trench isolation 17 to electrically isolate the fin structure 16 and other semiconductor components on the substrate 10. In this embodiment, the metal gate 12 may be on the substrate 10 to intersect the fin structure 16 (such as the metal gate 12a in FIG. 1), or may be located on the shallow trench isolation 17 (as in FIG. 1). The metal gate 12c) is used as a dummy gate or may be located at the edge of the fin structure 16 (such as the metal gate 12b in FIG. 1) to protect the structural integrity of the fin structure 16. Sex.

In addition, in the fabrication method of the embodiment, an epoxy layer 15 is selectively formed on the source/drain region 14. In addition, it is more preferable to selectively form a sidewall 18 and an etch stop layer 20 on both sidewalls of the metal gate 12, and then cover a first dielectric layer 22, and then perform a planarization step, for example, The chemical mechanical polishing process (CMP) causes the top end of the metal gate 12 to be flush with the top end of the first dielectric layer 22. It should be noted that, in this embodiment, after the metal gate 12 is completed, a portion of the top end of the metal gate 12 is removed by an etching process, and a mask layer 24 is formed instead of the metal gate 12 of the top portion. And another planarization step is performed to remove the excess mask layer 24. That is, the present embodiment further includes a mask layer 24 at the top end of the metal gate 12, and the top end of the mask layer 24 is aligned with the top end of the first dielectric layer 22, and further, since the mask layer 24 is Instead of the partial top end of the original metal gate 12, the mask layer 24 is only located on the metal gate 12 and between the side walls 18. In addition, since the partial sidewalls 18 and the etch stop layer 20 are also removed during the above-described another planarization, the sidewalls 18 and the top end of the etch stop layer 20 have a truncated surface. In this embodiment, the material of the sidewall spacer 18, the etch stop layer 20, and the mask layer 24 is mainly tantalum nitride, and the main material of the first dielectric layer 22 is tantalum oxide, but is not limited thereto. The materials and manufacturing methods of the above various elements are all well-known technologies of the present invention, and will not be further described herein.

Next, as shown in FIG. 2, a second dielectric layer 26 is formed on the first dielectric layer. 22, in the present embodiment, the main material of the second dielectric layer 26 is ruthenium oxide, but is not limited thereto. Then, a photoresist layer 28 is formed on the second dielectric layer 26, wherein the photoresist layer 28 can be a single layer structure or a multilayer structure. According to an embodiment of the invention, the photoresist layer 28 sequentially comprises an organic dielectric layer. An organic dielectric layer (ODL) 28a, a silicon-containing hard mask bottom anti-reflecting coating (SHB) 28b, and a photoresist layer (PR) 28c. In short, the embodiment The photoresist layer 28 is a three-layer structure composed of ODL/SHB/PR, but is not limited thereto. Next, in order to fabricate a plug which is subsequently electrically connected to the source/drain region 14 (the plug can replace the underlying contact structure and the upper metal structure electrically connected to the source/drain region 14 in the prior art, referred to herein as As a zeroth metal contact, M0CT), an exposure and development process is performed to pattern the photoresist layer 28c to form a plurality of openings 30, and the positions of the openings 30 correspond at least to the source/drain regions 14 below, but are notable Yes, a portion of the opening 30 may also correspond to the shallow trench isolation 17 around the metal gate 12 to reduce the area of the transistor structure (mainly including the metal gate 12, the source/drain region 14 and the fin structure 16). A pattern density difference from the surrounding area.

Next, as shown in FIGS. 3 to 4, at least one etching step E1 is performed to transfer the pattern of the opening 30 into the lower layer structure, wherein the etching step E1 includes: etching from top to bottom, sequentially etching the mask The anti-reflection layer 28b, the organic dielectric layer 28a, the second dielectric layer 26 and the first dielectric layer 22 are exposed until the etch stop layer 20 is exposed, and then another etching step is performed as shown in FIG. E2, a portion of the etch stop layer 20 is removed to expose the underlying epitaxial layer 15 and a plurality of first recesses 32 are formed, each of the first recesses 32 exposing each of the epitaxial layers 15, notably Since the epitaxial layer 15 is selectively formed in the present invention, each of the first recesses 32 may directly expose the source/drain regions 14, and further, according to different embodiments, portions of the first recesses 32 are also May be located on the shallow trench isolation 17.

The etching step used in this embodiment is mainly gas etching, and may include perfluorocarbon gases such as Tetrafluoromethane (CF4), trifluoromethane (Fluoroform, CHF3), and perfluorobutane. Diene (Hexa-fluoro-1, 3+butadiene, C4F6), etc., additionally contains oxygen and argon (Argon, Ar), but is not limited thereto. It is worth noting that the higher the ratio of the perfluorocarbon gas to the oxygen contained in the etching gas, the higher the etching selectivity ratio of the etching gas to yttrium oxide/tantalum nitride. In other words, if the proportion of the perfluorocarbon gas contained in the etching gas is high, the rate of etching the yttrium oxide during the etching process will be greater than the rate of etching the tantalum nitride. In this embodiment, the first dielectric layer 12 and the second dielectric layer 22 are mainly yttrium oxide, and the etch stop layer 20 material mainly contains tantalum nitride. In this embodiment, the etching step E1 is selected for yttrium oxide. The etch of tantalum nitride selects a relatively high (preferably greater than 5) gas, so the rate at which the second dielectric layer 22 and the first dielectric layer 12 are etched is faster, but the rate at which the etch stop layer 20 is etched is slower. When the etching step E1 is performed, the rate of etching the second dielectric layer 22 and the first dielectric layer 12 is at least five times greater than the rate of etching the etch stop layer 20, so the etching step E1 does not easily etch through the etch stop layer 20, It will stop at the surface of the etch stop layer 20. Next, in the etching step E2, another gas is selected for etching to remove the etch stop layer 20 at the bottom of the first recess 32.

As shown in FIG. 5, a self-aligned silicide (salicide) is performed on the epitaxial layer 15 to form a metal telluride layer 34 at the bottom of the first recess 32. The self-aligned metal telluride process mainly comprises filling a metal layer (not shown) in each of the first recesses 32, and performing a heating step to form a metal germanium at the boundary between the metal layer and the germanium-containing surface. The layer 34 is then removed from the metal layer located in the first recess. It should be noted that the metal telluride layer 34 in the present invention is formed only in The surface of the crucible may thus be formed on the fin structure 16, the epitaxial layer 15 or the substrate 10 without being formed on the shallow trench isolation 17.

As shown in FIG. 6, a photoresist layer 38 is again covered, wherein the photoresist layer 38 is made of the same material as the photoresist layer 28, and includes an organic dielectric layer 38a, a germanium mask-containing anti-reflective layer 38b, and a photoresist layer. 38c. In order to fabricate a plug which is subsequently electrically connected to the source metal gate 12 (the plug can replace the underlying contact structure and the upper metal structure electrically connected to the metal gate 12 in the prior art, referred to herein as the zeroth metal Gate contact, M0PY), performing an exposure development step, patterning the photoresist layer 38c, forming a plurality of openings 40, and the positions of the openings 40 correspond at least to a portion of the metal gate 12, but are not limited thereto, and some are also The position of the opening 40 may correspond to the shallow trench isolation 17.

Next, as shown in FIG. 7, an etching step E3 is performed to transfer the pattern of the opening 40 to the lower layer structure. The etching step E3 includes: sequentially etching the anti-reflective layer 38b containing the germanium mask from top to bottom. The organic dielectric layer 38a, the second dielectric layer 26, and the mask layer 24. It should be noted that in the etching step E3, the ratio of the perfluorocarbon gas to the oxygen in the etching gas is adjusted so that the etching rate of the gas for the tantalum oxide/tantalum nitride is similar, that is, the gas selected in the etching step E3, The etching selectivity ratio for yttria/tantalum nitride is relatively low (preferably less than 5), so the gas can simultaneously remove the yttrium oxide and tantalum nitride layers, and after the etching step E3, the top of each of the metal gates 12 It can be directly exposed and a plurality of second grooves 42 are formed. An ash process or other etching process can then be performed to remove the remaining photoresist and the excess organic dielectric layer 38a in the first recess 32 or the second recess 42.

As shown in FIG. 8, a barrier layer 44 and a metal layer 46 are sequentially filled in each of the first recess 32 and each of the second recesses 42, and the barrier layer 44 may include titanium nitride. (Titanium nitride, TiN) and tantalum nitride (TaN) or a multilayer barrier layer such as titanium/titanium nitride to enhance the adhesion between the inner wall of each groove and the subsequently formed metal layer. Metal layer 46 preferably includes tungsten (tungsten, W) which has a preferred gap fill performance. Next, a planarization step is performed to remove the excess barrier layer and the metal layer on the top of the second dielectric layer 26 to complete the plurality of layers in the first dielectric layer 12 and the second dielectric layer 26 simultaneously. The first contact 52 and the plurality of second contacts 54, wherein each of the first contacts 52 is electrically connected to at least a portion of the source/drain regions 14 (that is, each of the first contacts 52 of the embodiment is the MOCT described above). Each of the second contacts 54 is electrically connected to at least a portion of the metal gate 12 (that is, each of the second contacts 54 of the embodiment is the above-mentioned MOPY). In addition, since each of the first contacts 52 and the second contacts 54 are completed after simultaneously filling the metal layer 46, each of the first contacts 52 and each of the second contacts 54 are monolithically formed. It should be noted that, in this embodiment, since a portion of the second recess 42 may overlap the portion of the first recess 32, a portion of the first contact 52 directly contacts the second contact 54 (eg, 8th The second contact 54A) in the figure, the connection portion of the first contact 52 and the second contact 54 can be used as a share contact in the semiconductor element, but is not limited thereto.

As shown in FIG. 9, a subsequent metal interconnect process is performed to form a third dielectric layer 60 on top of the second dielectric layer 26, where the third dielectric layer 60 is, for example, A plurality of conductive via patterns (not shown) and a plurality of conductive patterns are formed in the third dielectric layer 60 by etching or the like in an inter-metal dielectric layer (IMD). In the end, a metal layer 61 is simultaneously filled in each of the conductive via patterns and each of the conductive patterns, and a planarization step is performed to remove excess metal layer on the surface of the third dielectric layer 60. A plurality of conductive via structures 62 and a plurality of conductor structures 64 are completed. In this embodiment, by After the conductive via structures 62 and the conductor structures 64 are simultaneously filled with the metal layer, the two can be regarded as a third contact 66, and each of the third contacts 66 is an integrally formed structure. Each of the conductive via structures 62 directly contacts the first contact 52 or the second contact 54 located below in the vertical direction, and the respective conductor structures 64 are located on the same horizontal plane to connect other elements on the substrate 10 in the horizontal direction. From the top view, the conductive via structure 62 may exhibit a rectangular, circular or other shaped block structure, while the wire structure 64 may exhibit a long line structure, but is not limited thereto.

It should be noted that, in the above manufacturing process, the first groove 32 is first formed, and then the second groove 42 is formed. However, the present invention is not limited thereto, and in another embodiment of the present invention, The yttria/tantalum nitride etch is selected by etching a relatively low gas to form a second recess 42, and then a relatively high gas is etched for yttria/tantalum nitride etching to form a first recess. 32. Finally, filling the barrier layer 44 with the metal layer 46 and performing a planarization step to simultaneously complete the plurality of first contacts 52 and the plurality of second contacts 54 are also within the scope of the present invention.

The semiconductor device 1 provided by the present invention can be realized by the above-described manufacturing process. The final structure is as shown in FIG. 9. Referring to FIGS. 1-9, the semiconductor device 1 includes at least one substrate 10 and a first dielectric layer. The electrical layer 12 is disposed on the substrate 10, a metal gate 12 is disposed in the first dielectric layer 12, a source/drain region 14 is disposed on both sides of the metal gate 12, and a mask layer 24 is located on the metal. On the gate 12, the top end of the mask layer 24 is flush with the top end of the first dielectric layer 12; a second dielectric layer 26 is on the first dielectric layer 12; and a plurality of first contacts 52 are further included. , in the first dielectric layer 12 and the second dielectric layer 26 , and electrically connected to a portion of the source/drain region 14 , wherein each of the first contacts 52 is an integrally formed structure, and a plurality of second contacts 54 , Located in the first The electrical layer 12 and the second dielectric layer 26 are electrically connected to a portion of the metal gate 12, wherein each of the second contacts 54 is an integrally formed structure. In addition, the semiconductor device 1 further optionally includes the following components: an epitaxial layer 15 on the source/drain region 14; a shallow trench isolation 17 in the substrate 10 around the metal gate 12, The sidewall spacers 18 and an etch stop layer 20 are located on both sides of the metal gate 12, and both have a cross section at the top end; a fin structure 16 is disposed on the substrate 10; and a metal telluride layer 34 is located at each Between the source/drain region 14 and the first contact 52; a third dielectric layer 60 at the top end of the second dielectric layer 26, and a plurality of third contacts 66 located at a portion of the first contact 52 or a portion of the second Each of the third contacts 66 includes a conductive via structure 62 and a conductor structure 64, and each of the conductive via structures 62 and the respective conductor structures 64 comprise the same material. And in direct contact with each other. The materials and manufacturing methods of the above-mentioned components are the same as those in the manufacturing process of the first preferred embodiment of the present invention, and details are not described herein again.

In summary, the present invention is characterized in that a mask layer is included at the top end of the metal gate, and the mask layer and the dielectric layer are selectively etched using etching gases of different etching rates. In this way, the structure on the gate and the contact structure on the source/drain region can be completed at the same time, replacing the conventional lower contact structure and the upper metal layer (M0) in two parts, thereby reducing the process steps.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1‧‧‧Semiconductor components

10‧‧‧Base

16‧‧‧Fin structure

17‧‧‧Shallow trench isolation

18‧‧‧ Sidewall

20‧‧‧etch stop layer

22‧‧‧First dielectric layer

26‧‧‧Second dielectric layer

44‧‧‧Barrier layer

46‧‧‧metal layer

52‧‧‧ first contact

54‧‧‧second contact

60‧‧‧ third dielectric layer

61‧‧‧metal layer

62‧‧‧Electrical through holes

64‧‧‧Wire

66‧‧‧ Third contact

Claims (17)

a semiconductor structure comprising: a substrate; a first dielectric layer on the substrate; a second dielectric layer on the first dielectric layer; and a metal gate on the first dielectric layer a plurality of second contacts, located in the first dielectric layer and the second dielectric layer, electrically connected to a portion of the metal gates, wherein each of the second contacts is an integrally formed structure; a drain region on both sides of the metal gate; and a mask layer on the metal gate, and a top end of the mask layer is flush with a top end of the first dielectric layer. The semiconductor structure of claim 1 further includes an etch stop layer on both sides of the metal gate, and the top end of the etch stop layer has a cross section. The semiconductor structure of claim 1, further comprising a plurality of first contacts, located in the first dielectric layer and the second dielectric layer, electrically connected to a portion of the source/drain regions, wherein each The first contact is an integrally formed structure. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises at least one fin structure on the substrate. The semiconductor structure of claim 1, further comprising a metal telluride layer between each of the source/drain regions and the first contact. Such as the semiconductor structure of claim 1 of the patent scope, which further includes a plurality of third connections The touch is located on a portion of the first contact or a portion of the second contact, and each of the third contacts is an integrally formed structure. The semiconductor structure of claim 6, wherein each of the third contacts comprises a conductive via structure and a wire structure, and each of the conductive via structures and the respective wire structures comprise the same material and are in direct contact with each other. A method of fabricating a semiconductor structure includes the steps of: providing a substrate having a first dielectric layer formed thereon, at least one metal gate in the first dielectric layer, and at least one source/drain region Located on two sides of the metal gate; forming a second dielectric layer on the first dielectric layer; performing a first etching step to form a plurality of the first dielectric layer and the second dielectric layer a first recess, and exposing each of the source/drain regions; performing a metal telluride process to form a metal telluride layer in each of the first recesses; performing a second etching step on the first dielectric layer Forming a plurality of second recesses in the electrical layer and the second dielectric layer, wherein each of the second recesses exposes the metal gate; and simultaneously filling a metal layer in each of the first recesses and each of the first recesses The two grooves are formed to form a plurality of first contacts and a plurality of second contacts, wherein each of the second contacts is an integrally formed structure. The manufacturing method of claim 8 , further comprising forming a mask layer on each of the metal gate tips after the first dielectric layer is formed. The manufacturing method of claim 9, wherein the top of the mask layer and the first The top of a dielectric layer is aligned. The manufacturing method of claim 8, wherein the method further comprises forming a fin structure on the substrate. The manufacturing method of claim 8, wherein a portion of the second groove partially overlaps a portion of the first groove position. The manufacturing method of claim 8, further comprising forming a plurality of third contacts electrically connected to a portion of the first contact or a portion of the second contact, and each of the third contacts is an integrally formed structure. The manufacturing method of claim 13, wherein each of the third contacts comprises a conductive via structure and a wire structure, and each of the conductive via structures and the respective wire structures comprise the same material and are in direct contact with each other. The manufacturing method of claim 8, further comprising forming an etch stop layer on both sides of the metal gate, and the top end of the etch stop layer has a cross section. The manufacturing method of claim 9, wherein the ratio of the rate at which the selected gas etches the first dielectric layer to the rate at which the mask layer is etched is greater than 5 when the first etching step is performed. The manufacturing method of claim 9, wherein the ratio of the rate at which the selected gas etches the first dielectric layer to the rate at which the mask layer is etched is less than 5 when the second etching step is performed.