CN101859700B - Polycrystalline silicon deposition process - Google Patents
Polycrystalline silicon deposition process Download PDFInfo
- Publication number
- CN101859700B CN101859700B CN2009100490758A CN200910049075A CN101859700B CN 101859700 B CN101859700 B CN 101859700B CN 2009100490758 A CN2009100490758 A CN 2009100490758A CN 200910049075 A CN200910049075 A CN 200910049075A CN 101859700 B CN101859700 B CN 101859700B
- Authority
- CN
- China
- Prior art keywords
- polycrystalline silicon
- etching
- polysilicon
- hole
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Chemical Vapour Deposition (AREA)
Abstract
The invention discloses a polycrystalline silicon deposition process which is used for filling holes with high aspect ratio. The process comprises a plurality of process cycles, and each process cycle comprises the following steps of: depositing polycrystalline silicon with a preset thickness in holes with the high aspect ratio at low temperature, wherein the growth rate of the polycrystalline silicon at the mouths of the holes is greater than that of the polycrystalline silicon at the bottoms of the holes; rising temperature and meanwhile introducing etching gas to etch the polycrystalline silicon in the holes with the high aspect ratio at high temperature, wherein the etching rate of the polycrystalline silicon at the mouths of the holes is greater than that of the polycrystalline silicon at the bottoms of the holes, and the thickness of the etched polycrystalline silicon at the bottoms of the holes is greater than that of the polycrystalline silicon at the mouths of the holes; and reducing the temperature to low temperature, and repeating the process cycles for several times until the holes with the high aspect ratio are filled. The invention adopts the technical scheme of the invention can ensure that the bottoms of the holes are sufficiently filled through repeated filling and etching cycles.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, relate to a kind of polycrystalline silicon deposition process.
Background technology
The deposit polysilicon is an important step in the semiconductor fabrication process in the hole, and polysilicon gets the performance during filling extent has directly determined to the hole.Polysilicon should have following characteristic for the good filling in hole: do not have space or space very little after fill in the hole.
For hole, there is not very little some difficulty in space or space after accomplishing to fill with high-aspect-ratio.Because in the process of filling, owing to the effect of bounce-back, sputter or the like, the speed of growth of the polysilicon in aperture can be greater than the bottom; Under the situation about often being closed in the aperture; Also accomplish to fill the inside in hole, so, will form the space and influence the performance of device.
This situation is especially common in the hole of the high-aspect-ratio more than 4: 1.So, need a kind of can the completion in high quality to carry out the technology that polysilicon is filled for the hole of high-aspect-ratio.
Summary of the invention
The present invention has disclosed a kind of technology that can accomplish well for the polysilicon filling in the hole with high-aspect-ratio.
According to an aspect of the present invention, proposed a kind of polycrystalline silicon deposition process, be used to fill the hole with high-aspect-ratio, this technology comprises:
Several process cycles, each process cycles comprises:
The polysilicon of deposit predetermined thickness in having the hole of high-aspect-ratio, deposit is carried out at low temperatures, and the polycrystalline silicon growth speed in aperture is greater than the polycrystalline silicon growth speed of bottom, hole;
Elevated temperature also feeds etching gas; Polysilicon in the hole of high-aspect-ratio is carried out etching; Etching is at high temperature carried out, and the etching polysilicon speed in aperture is greater than the etching polysilicon speed of hole bottom, and the polysilicon thickness of etching metapore bottom is greater than the polysilicon thickness in aperture;
Reduce temperature to low temperature;
Repeating for several times, process cycles is filled until the hole with high-aspect-ratio.
In one embodiment, in the process of deposit polysilicon, use hydrogen as carrying gas, silane is as silicon source gas.
In one embodiment, etching gas is a hydrogen chloride.
In one embodiment, in each process cycles, also comprise with the hydrogen purge hole to remove the accessory substance that etching produces behind reduction temperature to the low temperature.
Above-mentioned polycrystalline silicon deposition process is particularly suitable for epitaxial device.
Adopt technical scheme of the present invention; Through repetitious filling, etching circulation; The bottom of guaranteeing the hole can access sufficient filling, and, using hydrogen to purge after the etching each time; Can effectively remove accessory substance and prevent that oxide layer from producing, thereby obtain high-quality filling effect.
Description of drawings
Above-mentioned and other characteristic, character and advantage of the present invention will become more obvious through the description below in conjunction with accompanying drawing and embodiment, in the accompanying drawings, identical Reference numeral is represented identical characteristic all the time, wherein:
Fig. 1 has disclosed the sketch map of the technical process of polycrystalline silicon deposition process according to an embodiment of the invention.
Embodiment
The present invention has disclosed a kind of technology that can accomplish well for the polysilicon filling in the hole with high-aspect-ratio.This polycrystalline silicon deposition process is used to fill the hole with high-aspect-ratio, and this technology comprises:
Several process cycles, each process cycles comprises:
The polysilicon of deposit predetermined thickness in having the hole of high-aspect-ratio, deposit is carried out at low temperatures, and the polycrystalline silicon growth speed in aperture is greater than the polycrystalline silicon growth speed of bottom, hole;
Elevated temperature also feeds etching gas; Polysilicon in the hole of high-aspect-ratio is carried out etching; Etching is at high temperature carried out, and the etching polysilicon speed in aperture is greater than the etching polysilicon speed of hole bottom, and the polysilicon thickness of etching metapore bottom is greater than the polysilicon thickness in aperture;
Reduce temperature to low temperature;
Repeating for several times, process cycles is filled until the hole with high-aspect-ratio.
In one embodiment, in the process of deposit polysilicon, use hydrogen as carrying gas, silane is as silicon source gas.
In one embodiment, etching gas is a hydrogen chloride.
In one embodiment, in each process cycles, also comprise with the hydrogen purge hole to remove the accessory substance that etching produces behind reduction temperature to the low temperature.
Above-mentioned polycrystalline silicon deposition process is particularly suitable for epitaxial device.
With reference to shown in Figure 1, Fig. 1 has disclosed the sketch map of the technical process of polycrystalline silicon deposition process according to an embodiment of the invention.
At first, with reference to shown in wherein (a), the certain thickness polysilicon of deposit at low temperatures, the growth rate in aperture is greater than the growth rate of bottom, and the thickness of polysilicon is greater than bottom polysilicon thickness near the aperture.So the polysilicon of deposit forms the tubaeform of downward expansion in the hole.In the process of deposit, can adopt hydrogen as carrying gas, silane is as silicon source gas.
With reference to shown in wherein (b); Feed etching gas behind the elevated temperature polysilicon is carried out etching; Etching is at high temperature carried out, and the etching polysilicon speed in aperture is greater than the etching polysilicon speed of hole bottom, and the polysilicon thickness of etching metapore bottom is greater than the polysilicon thickness in aperture.After etching, polysilicon forms the tubaeform of upwards expansion.In etching process, adopt hydrogen chloride as etching gas.
After accomplishing etching, once more temperature is reduced to low temperature, promptly be suitable for the temperature of polysilicon deposit, and use the hydrogen purge certain hour, remove the accessory substance that etching generates, and prevent that oxide layer from occurring.So just accomplished a process cycles.
With reference to wherein (c) with (d); Repeat the above-mentioned deposit and the process of etching, relatively (a) and (b) with (c), (d) can find, after each process cycles is accomplished; The bottom in hole is just filled fully, and a back process cycles can be regarded as on the hole of " more shallow " carries out.
After several circulations, can obtain the effect shown in (e) so repeatedly, promptly the inside in hole is filled fully.
The technology that this polysilicon is filled can better solve the filling in the hole of high-aspect-ratio, can accomplish the filling of 4: 1 above high-aspect-ratios.On 4: 1 technology of depth-to-width ratio, make an experiment, fill finely in crystal circle center, do not have the slit; At crystal round fringes, there is very little slit, meet the device performance demands fully.
Adopt technical scheme of the present invention; Through repetitious filling, etching circulation; The bottom of guaranteeing the hole can access sufficient filling, and, using hydrogen to purge after the etching each time; Can effectively remove accessory substance and prevent that oxide layer from producing, thereby obtain high-quality filling effect.
The foregoing description provides to being familiar with personnel in this area and realizes or use of the present invention; Being familiar with those skilled in the art can be under the situation that does not break away from invention thought of the present invention; The foregoing description is made various modifications or variation; Thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (5)
1. a polycrystalline silicon deposition process is characterized in that, is used to fill the hole with high-aspect-ratio, and said technology comprises:
Several process cycles, each process cycles comprises:
The polysilicon of deposit predetermined thickness in having the hole of high-aspect-ratio, said deposit is carried out at low temperatures, and the polycrystalline silicon growth speed in aperture is greater than the polycrystalline silicon growth speed of bottom, hole;
Elevated temperature also feeds etching gas; Polysilicon in the hole of high-aspect-ratio is carried out etching; Said etching is at high temperature carried out, and the etching polysilicon speed in aperture is greater than the etching polysilicon speed of hole bottom, and the polysilicon thickness of etching metapore bottom is greater than the polysilicon thickness in aperture;
Reduce temperature to low temperature;
Repeating for several times, said process cycles is filled until said hole with high-aspect-ratio.
2. polycrystalline silicon deposition process as claimed in claim 1 is characterized in that, in the process of deposit polysilicon, uses hydrogen as carrying gas, and silane is as silicon source gas.
3. polycrystalline silicon deposition process as claimed in claim 1 is characterized in that said etching gas is a hydrogen chloride.
4. polycrystalline silicon deposition process as claimed in claim 1 is characterized in that, in said each process cycles, also comprises with the said hole of hydrogen purge to remove the accessory substance that etching produces behind reduction temperature to the low temperature.
5. polycrystalline silicon deposition process as claimed in claim 1 is characterized in that said polycrystalline silicon deposition process is applied to epitaxial device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100490758A CN101859700B (en) | 2009-04-09 | 2009-04-09 | Polycrystalline silicon deposition process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100490758A CN101859700B (en) | 2009-04-09 | 2009-04-09 | Polycrystalline silicon deposition process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101859700A CN101859700A (en) | 2010-10-13 |
| CN101859700B true CN101859700B (en) | 2012-05-30 |
Family
ID=42945509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100490758A Active CN101859700B (en) | 2009-04-09 | 2009-04-09 | Polycrystalline silicon deposition process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101859700B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456634A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103515214A (en) * | 2012-06-25 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN103871880A (en) * | 2012-12-13 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Shallow slot isolation structure manufacturing method |
| CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
| US9761683B2 (en) * | 2015-05-15 | 2017-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN107527814A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
| CN109817637B (en) * | 2017-11-22 | 2020-10-09 | 旺宏电子股份有限公司 | Semiconductor structure for three-dimensional memory element and manufacturing method thereof |
| CN109148276A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The method for improving deep trench filling capacity |
| CN109742026B (en) * | 2019-02-25 | 2024-03-29 | 哈尔滨工业大学 | Method for preparing diamond-assisted heat dissipation silicon carbide substrate GaN-HEMTs by direct growth method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN1466192A (en) * | 2002-07-03 | 2004-01-07 | 旺宏电子股份有限公司 | Method for promoting performance of flash memory by using microcrystalline silicon film as floating gate |
| US7078312B1 (en) * | 2003-09-02 | 2006-07-18 | Novellus Systems, Inc. | Method for controlling etch process repeatability |
| CN1832144A (en) * | 2005-03-10 | 2006-09-13 | 海力士半导体有限公司 | Method for fabricating flash memory device |
| US7163896B1 (en) * | 2003-12-10 | 2007-01-16 | Novellus Systems, Inc. | Biased H2 etch process in deposition-etch-deposition gap fill |
| CN1913122A (en) * | 2005-08-12 | 2007-02-14 | 东部电子株式会社 | Method for forming void-free trench isolation layer |
| CN1979796A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | Method with high seam-filling ability and device structure obtained therefrom |
| CN101084574A (en) * | 2004-12-14 | 2007-12-05 | 应用材料股份有限公司 | Process sequence for doped silicon fill of deep trenches |
| CN101197307A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Oxide deposition method of shallow groove isolation region |
-
2009
- 2009-04-09 CN CN2009100490758A patent/CN101859700B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN1466192A (en) * | 2002-07-03 | 2004-01-07 | 旺宏电子股份有限公司 | Method for promoting performance of flash memory by using microcrystalline silicon film as floating gate |
| US7078312B1 (en) * | 2003-09-02 | 2006-07-18 | Novellus Systems, Inc. | Method for controlling etch process repeatability |
| US7163896B1 (en) * | 2003-12-10 | 2007-01-16 | Novellus Systems, Inc. | Biased H2 etch process in deposition-etch-deposition gap fill |
| CN101084574A (en) * | 2004-12-14 | 2007-12-05 | 应用材料股份有限公司 | Process sequence for doped silicon fill of deep trenches |
| CN1832144A (en) * | 2005-03-10 | 2006-09-13 | 海力士半导体有限公司 | Method for fabricating flash memory device |
| CN1913122A (en) * | 2005-08-12 | 2007-02-14 | 东部电子株式会社 | Method for forming void-free trench isolation layer |
| CN1979796A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | Method with high seam-filling ability and device structure obtained therefrom |
| CN101197307A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Oxide deposition method of shallow groove isolation region |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101859700A (en) | 2010-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101859700B (en) | Polycrystalline silicon deposition process | |
| CN108649034B (en) | Semiconductor structure and forming method thereof | |
| JP2015045082A (en) | Silicon film deposition method, thin film deposition method, and cross section shape controlling method | |
| JP2013082986A (en) | Thin film forming method and film forming apparatus | |
| JP6742477B2 (en) | Epitaxial silicon carbide single crystal wafer manufacturing method and epitaxial silicon carbide single crystal wafer | |
| WO2014152598A1 (en) | Nanocrystalline diamond three-dimensional films in patterned semiconductor substrates | |
| CN107419329A (en) | The preparation method of the full carbon structure of single-crystal diamond surface in situ n-type semiconductorization | |
| EP1734565B1 (en) | Method for manufacturing semiconductor wafer | |
| JP4116790B2 (en) | Method for forming silicon-germanium film | |
| CN107195536A (en) | Self-standing gan layer and preparation method thereof | |
| CN104377123B (en) | The method of growth low stress IGBT groove type grids | |
| CN107331620A (en) | Low pressure super node MOSFET electric leakage of the grid ameliorative way | |
| JP2017085164A (en) | Thin film deposition method | |
| CN101859699A (en) | Polycrystalline silicon deposition process | |
| CN102881570A (en) | Method for manufacturing semiconductor material | |
| CN107564800B (en) | Preparation method of silicon nitride layer | |
| CN104282550B (en) | The manufacture method of Schottky diode | |
| CN106024699B (en) | A kind of preparation method of autoregistration STI | |
| CN103489821A (en) | Method for filling groove with high aspect ratio | |
| CN202076271U (en) | Epitaxial layer structure of back sealing monocrystalline silicon | |
| CN104630744B (en) | A kind of Al/Ti film Atomic layer deposition methods with amino titanium as titanium source | |
| CN103035500A (en) | Formation method of trench gate | |
| CN103077920A (en) | Dry etching method of improving horizontal opening of through silicon hole | |
| CN101692434A (en) | Filling method of deep groove isolation structure of silicon-on-insulator | |
| CN106252210A (en) | A kind of polysilicon preparation method utilizing cap annealing crystallization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 200233, No. 385 Rainbow Road, Shanghai, Xuhui District Patentee after: SHANGHAI ADVANCED SEMICONDUCTO Address before: 200233, 385 Rainbow Road, Shanghai Patentee before: ADVANCED SEMICONDUCTOR MANUFACTURING Co.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210425 Address after: 200120 No.600 Yunshui Road, Pudong New Area, Shanghai Patentee after: Shanghai Jita Semiconductor Co.,Ltd. Address before: 200233, No. 385 Rainbow Road, Shanghai, Xuhui District Patentee before: SHANGHAI ADVANCED SEMICONDUCTO |
|
| TR01 | Transfer of patent right |