CN103515214A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN103515214A CN103515214A CN201210211649.9A CN201210211649A CN103515214A CN 103515214 A CN103515214 A CN 103515214A CN 201210211649 A CN201210211649 A CN 201210211649A CN 103515214 A CN103515214 A CN 103515214A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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Abstract
A manufacturing method of a semiconductor device comprises the following steps: providing a semiconductor substrate on which a grid groove for forming a metal grid structure is formed; performing a first metal depositing step on the grid groove; performing an electrochemical reaction on the grid groove for eliminating projections at the left upper corner and the right upper corner of the grid groove for enlarging opening direction of the grid groove; and performing a second metal depositing step on the grid groove. According to the manufacturing method of the invention, through performing one time or multiple times of process including the steps of metal depositing, performing the electrochemical reaction for eliminating the projections on the left upper corner and the right upper corner of the grid groove and metal depositing, hole generation in a metal clearance filler can be prevented, and furthermore qualified rate reduction of the product can be prevented.
Description
Technical field
The present invention relates to a kind of semiconductor making method, in particular to a kind of manufacture method of the semiconductor device based on gate replacement technique.
Background technology
In gate metal alternative techniques in semiconductor fabrication process, conventionally select polysilicon as false grid, after the source electrode of device has been prepared with drain electrode, utilize dry etching or wet etching technique that false grid are removed, in gate groove, insert afterwards metal charge as the metal gate material of device.
But, along with device feature size is to the even meticulousr structural development of 45 nanometers, to gate metal alternative techniques, the especially filling of metal medium, have higher requirement, one of them challenging difficult problem is exactly that metal is difficult to the filling of even atresia in each gate groove.In metal filled process, cavitation happens occasionally, and these cavities are arranged in gate groove filler, and each gate groove may have cavity to produce.Figure 1A-1C shows the method for inserting metal gate material in prior art in gate groove.As shown in Figure 1A, after forming gate groove shape 101 in Semiconductor substrate 100, deposit a wet metal material layer 102 thereon, shown in metal material can be Ti or Co etc., then as shown in Figure 1B, by physical vapor deposition (PVD) method, while using aluminum metal to fill gate groove, in the gate groove upper left corner and the upper right corner, there will be projection 103 and 104, and along with the carrying out of filling, the projection 103 in the left upper right corner can connect together with 104, and hinder aluminum metal and be further packed in gate groove 101, finally occur as the phenomenon of Fig. 1 C, in aluminum metal packed layer 106, formed a cavity 105.
This cavity that is arranged in the metal charge of gate groove can cause performance of semiconductor device to reduce, and may in follow-up operation, produce defect, and then reduce the qualification rate of product, so the cavity in the metal charge of gate groove becomes one of problem that industry must solve.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, is formed with the gate groove that is used to form metal gate structure; Described gate groove is carried out to the first metal deposition step; Described gate groove is carried out to the step that electrochemical reaction is removed the projection in the described gate groove upper left corner and the upper right corner, to expand the opening size of described gate groove; Described gate groove is carried out to the second metal deposition step.
Further, this manufacture method also comprises and repeatedly repeats step, the second metal deposition step that described the first metal deposition step, described execution electrochemical reaction are removed the projection in the described gate groove upper left corner and the upper right corner.
Further, in described electrochemical reaction, the anion of the electrolyte using is one of following two kinds of ions or its combination: chloride ion, fluorine ion.
Further, in described electrochemical reaction, the electrolyte using comprises one of following two kinds of organic substances or its combination: methyl alcohol and glycerol.
Further, in described electrochemical reaction, the volume of described methyl alcohol is 800-900 milliliter.
Further, in described electrochemical reaction, the volume of described glycerol is 126-300 milliliter.
Further, in described electrochemical reaction, the electrolyte using comprises NaBF
4.
Further, in described electrochemical reaction, the decomposition voltage using lies prostrate for 50-100.
Further, in described electrochemical reaction, electrolysis time is 5-60 second.
Further, described the first metal deposition step and/or the second metal deposition step are used one of following methods: physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Further, described gate groove is carried out before described the first metal deposition step, be also included in the step of deposition one wet metal material layer in described gate groove.
Further, described wet metal material is Ti or Co.
Further, the step metal of described deposition being refluxed be also included in settling chamber or heating furnace in described the first metal deposition step and/or the second metal deposition step in.
Further, the temperature of using in described reflow step is 300-500 degree Celsius, and the duration of reflow step is 20 minutes-2 hours.
According to the present invention, in the process with formation grid when using aluminum metal to fill gate groove, " metal deposition step-execution electrochemical reaction is removed the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " process of carrying out taking turns or taking turns more, can avoid in filling of metal gap, producing cavity, and then reduce the problem of the qualification rate of product.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-1C shows the method for inserting metal gate material in prior art in gate groove;
Fig. 2 A-2H shows the schematic cross sectional view of each step of the method for inserting metal gate material in gate groove that the present invention proposes;
The flow chart of the method for inserting metal gate material in gate groove that Fig. 3 the present invention proposes.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, with reference to Fig. 2 A-Fig. 2 H and Fig. 3, the method for inserting metal gate material in gate groove that the present invention proposes is described.
With reference to Fig. 2 A-Fig. 2 H, wherein show the schematic cross sectional view of each step of the method for inserting metal gate material in gate groove that the present invention proposes.
First, as shown in Figure 2 A, provide Semiconductor substrate 200, the constituent material of described Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.In one embodiment of the invention, Semiconductor substrate 200 selects single crystal silicon material to make.Although several examples of having described the material that can form substrate 200 at this, any material that can be used as Semiconductor substrate all falls into spiritual scope of the present invention.At described Semiconductor substrate 200 upper surface growth one deck grid oxic horizons 201, grid oxic horizon 201 is as gate dielectric layer, and its material can be SiO
2, SiON etc., can use ald, chemical vapor deposition (CVD) or other applicable method, above only as example, be not limited to this.In different situations, grid oxic horizon 201 can adopt different materials and different thickness.
Then, deposit spathic silicon layer 202 on the grid oxic horizon 201 of described Semiconductor substrate 200, as shown in Figure 2 B.The material of polysilicon layer 202 can be the polysilicon of polysilicon or doping metals impurity, and described metal impurities at least comprise a kind of metal (for example titanium, tantalum, tungsten etc.) and metal silicide.The method that forms polysilicon layer 202 comprises that ald, chemical vapor deposition (CVD), plasma strengthen shape chemical meteorology deposition (PECVD) or other applicable method, then at polysilicon layer surface using plasma enhancing chemical vapour deposition (CVD) (PECVD) process deposits silicon nitride or silicon oxynitride, forms hard mask layer.
In ensuing processing step, at above-mentioned hard mask layer surface-coated photoresist layer, then utilize conventional photoetching process, art pattern CAD photoresist layers such as exposure, development, cleaning, to form false grid 205, as shown in Figure 2 B.
Before carrying out the follow-up step that removes false grid, can carry out any other technique, other technique, including but not limited to forming side wall layer in described Jia Shan both sides, form the common semiconductor fabrication process such as source/drain regions (as low-doped source/drain regions) in substrate, is not repeated herein.
Then form dielectric layer if interlayer dielectric layer (ILD) is on substrate, the formation method of interlayer dielectric layer 206 can be CVD, PECVD or other appropriate method.The composition of interlayer dielectric layer 206 contains silica, silicon oxynitride or other suitable material.In one embodiment, the dielectric layer that interlayer dielectric layer 206 forms for PECVD method.Then by its planarization, use for example chemical and mechanical grinding method (CMP), remove the dielectric layer material of deposition on false grid 205, until expose false grid 205 upper surfaces, as shown in Figure 2 C.
Then remove false grid 205, to form gate groove 207, as shown in Figure 2 D.In one embodiment, can utilize false grid 205 etchings shown in general such as one of dry etching or wet etching technique etc. to remove, thereby form gate groove 207.In another embodiment, can utilize dry etching or wet etching technique further grid oxic horizon 201 to be removed, to form the groove 207 that exposes substrate, redeposited high k gate dielectric layer (not shown) then, this high k gate dielectric layer (for example adopts high K medium material, compare with silica, the material with high-k), the example of high K medium material comprises metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, the nitrogen oxide of metal, the combination of metal aluminate or other suitable compositions.
Then in gate groove 207, insert metal gate material.In one embodiment, can be first at wet metal material layer 208 of gate groove 207 surface deposition, described metal material can be Ti or Co etc.Then, in one embodiment, by the deposition process of methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), use aluminum metal to fill gate groove.This deposition step can also be included in the step in settling chamber or heating furnace, the metal of described deposition being refluxed, and in this reflow step, the temperature of use can be 300-500 degree Celsius, and the duration of reflow step is 20 minutes-2 hours.In the process of using aluminum metal to fill gate groove, can there will be projection 209 and 210 in gate groove 207 upper left corners and the upper right corner, obstruction aluminum metal continues to fill gate groove by the upper shed of gate groove 207, as shown in Figure 2 E.
Therefore, next, need to remove the projection 209 in gate groove 207 upper left corners and the upper right corner and 210 step, as shown in Figure 2 F.In removing the projection 209 and 210 step in gate groove 207 upper left corners and the upper right corner, can use electrochemical method.In this electrochemical method, wafer is put into electrolyte 213 as anode, this electrolyte 213 can contain anion, such as chloride ion, fluorine ion etc., aluminum metal can be partly dissolved in electrolyte 213.In one embodiment, in electrolyte 213, can contain the methyl alcohol of 800-900 milliliter, the glycerol of 126-300 milliliter and appropriate NaBF
4.Use the decomposition voltage of 50-100 volt, the about 5-60 of electrolysis time second, can make the projection 209 and 210 in gate groove 207 upper left corners and the upper right corner be dissolved in electrolyte, thereby expand the opening size of gate groove, as shown in Figure 2 G.
Then, by the deposition process of methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), continuation is to the interior filling metal gate material 212 of gate groove 207, until complete the step that aluminum metal is filled, and avoid the cavity in the metal charge of gate groove shape completely, as shown in Fig. 2 H.The step of this continuation deposition can also be included in the step in settling chamber or heating furnace, the metal of described deposition being refluxed, and in this reflow step, the temperature of use can be 300-500 degree Celsius, and the duration of reflow step is 20 minutes-2 hours.In one embodiment of the invention, the process of " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " that can carry out taking turns, can complete gate replacement technique, and avoid producing cavity in gate groove filler.In other embodiment of the present invention, can repeatedly repeat " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner ", just can avoid producing cavity in gate groove filler.
So far, whole processing steps that method is implemented have according to an exemplary embodiment of the present invention been completed.Next, can by subsequent technique, complete the making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device.
With reference to Fig. 3, wherein show the flow chart of the method for inserting metal gate material in gate groove of the present invention's proposition, for schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided, in described Semiconductor substrate, be formed with the gate groove that is used to form metal gate structure;
In step 302, described gate groove is carried out to the step of the first metal deposition;
In step 303, use electrochemical method to remove the projection in the described gate groove upper left corner and the upper right corner, to expand the opening size of described gate groove;
In step 304, described gate groove is carried out to the second metal deposition step.Can be as required, repeatedly repeat " step-metal deposition step that metal deposition step-use electrochemical method is removed the projection in the described gate groove upper left corner and the upper right corner ", until complete metal filled step, and avoid the cavity in filling of metal gap completely.
According to the present invention, in the process with formation grid when using aluminum metal to fill gate groove, " metal deposition step-execution electrochemical reaction is removed the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " process of carrying out taking turns or taking turns more, can avoid in filling of metal gap, producing cavity, and then reduce the problem of the qualification rate of product.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with the gate groove that is used to form metal gate structure;
Described gate groove is carried out to the first metal deposition step;
Described gate groove is carried out to the step that electrochemical reaction is removed the projection in the described gate groove upper left corner and the upper right corner, to expand the opening size of described gate groove;
Described gate groove is carried out to the second metal deposition step.
2. method according to claim 1, also comprises and repeatedly repeats step, the second metal deposition step that described the first metal deposition step, described execution electrochemical reaction are removed the projection in the described gate groove upper left corner and the upper right corner.
3. method according to claim 1, is characterized in that, in described electrochemical reaction, the anion of the electrolyte using is one of following two kinds of ions or its combination: chloride ion, fluorine ion.
4. method according to claim 1, is characterized in that, in described electrochemical reaction, the electrolyte using comprises one of following two kinds of organic substances or its combination: methyl alcohol and glycerol.
5. method according to claim 4, is characterized in that, in described electrochemical reaction, the volume of described methyl alcohol is 800-900 milliliter.
6. method according to claim 4, is characterized in that, in described electrochemical reaction, the volume of described glycerol is 126-300 milliliter.
7. method according to claim 1, is characterized in that, in described electrochemical reaction, the electrolyte using comprises NaBF
4.
8. method according to claim 1, is characterized in that, in described electrochemical reaction, the decomposition voltage using lies prostrate for 50-100.
9. method according to claim 1, is characterized in that, in described electrochemical reaction, electrolysis time is 5-60 second.
10. method according to claim 1, is characterized in that, described the first metal deposition step and/or the second metal deposition step are used one of following methods: physical vapour deposition (PVD) or chemical vapour deposition (CVD).
11. methods according to claim 1, is characterized in that, described gate groove is carried out before described the first metal deposition step, are also included in the step of deposition one wet metal material layer in described gate groove.
12. according to the method for claim 11, it is characterized in that, described wet metal material is Ti or Co.
13. methods according to claim 1, is characterized in that, the step metal of described deposition being refluxed be also included in settling chamber or heating furnace in described the first metal deposition step and/or the second metal deposition step in.
14. methods according to claim 13, is characterized in that, the temperature of using in described reflow step is 300-500 degree Celsius, and the duration of reflow step is 20 minutes-2 hours.
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| CN201210211649.9A CN103515214A (en) | 2012-06-25 | 2012-06-25 | Manufacturing method of semiconductor device |
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| CN201210211649.9A CN103515214A (en) | 2012-06-25 | 2012-06-25 | Manufacturing method of semiconductor device |
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| US20010049198A1 (en) * | 1998-09-03 | 2001-12-06 | Moore John T. | Methods of forming materials within openings, and methods of forming isolation regions |
| CN1950970A (en) * | 2004-05-10 | 2007-04-18 | 株式会社日本触媒 | Material for electrolytic solution, ionic material-containing composition and use thereof |
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Application publication date: 20140115 |