CN103515214A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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CN103515214A
CN103515214A CN 201210211649 CN201210211649A CN103515214A CN 103515214 A CN103515214 A CN 103515214A CN 201210211649 CN201210211649 CN 201210211649 CN 201210211649 A CN201210211649 A CN 201210211649A CN 103515214 A CN103515214 A CN 103515214A
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metal
step
gate
method according
trench
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CN 201210211649
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Chinese (zh)
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周鸣
平延磊
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中芯国际集成电路制造(上海)有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al

Abstract

A manufacturing method of a semiconductor device comprises the following steps: providing a semiconductor substrate on which a grid groove for forming a metal grid structure is formed; performing a first metal depositing step on the grid groove; performing an electrochemical reaction on the grid groove for eliminating projections at the left upper corner and the right upper corner of the grid groove for enlarging opening direction of the grid groove; and performing a second metal depositing step on the grid groove. According to the manufacturing method of the invention, through performing one time or multiple times of process including the steps of metal depositing, performing the electrochemical reaction for eliminating the projections on the left upper corner and the right upper corner of the grid groove and metal depositing, hole generation in a metal clearance filler can be prevented, and furthermore qualified rate reduction of the product can be prevented.

Description

一种半导体器件的制造方法 A method of manufacturing a semiconductor device

技术领域 FIELD

[0001] 本发明涉及一种半导体制造方法,具体而言涉及一种基于栅极替代工艺的半导体器件的制造方法。 [0001] The present invention relates to a method for manufacturing a semiconductor, based on the gate to a semiconductor device manufacturing method of alternative process specifically.

背景技术 Background technique

[0002] 在半导体制造工艺中的栅极金属替代工艺中,通常选用多晶硅作为假栅,当器件的源极和漏极制备完后,利用干法刻蚀或者湿法刻蚀技术将假栅去掉,之后在栅沟槽内填入金属填充物作为器件的金属栅材料。 [0002] In the alternative process the gate metal in semiconductor manufacturing process, it is generally chosen as a dummy polysilicon gate, the source and drain when the device after the preparation, using a dry or wet etching techniques remove the dummy gate after the filler metal is filled in trench gate devices as a metal gate material.

[0003] 但是,随着器件特征尺寸向45纳米甚至更精细的结构发展,对栅极金属替代工艺,尤其是金属介质的填充,提出了更高的要求,其中一个具有挑战性的难题就是金属在各个栅沟槽中难以均匀无孔的填充。 [0003] However, as device feature sizes to 45 nm and the development of a finer structure, metal replacement gate process, in particular filler metal medium, a higher claims, wherein a challenging problem is the metal in each gate trench is difficult to uniformly filled with non-porous. 在金属填充过程中,空洞现象时有发生,这些空洞位于栅沟槽填充物中,每一个栅沟槽都可能有空洞产生。 In the metal filling process, there occurs the phenomenon of the hollow, which is located in the gate trench fill voids, each may have a trench gate of voids. 图1A-1C示出了现有技术中在栅沟槽内填入金属栅材料的方法。 Figures 1A-1C illustrate a method of the prior art metal gate material is filled in the gate trench. 如图1A所示,半导体衬底100上形成栅沟槽形101以后,在其上沉积一个湿金属材料层102,所示金属材料可以为Ti或者Co等,然后如图1B所示,通过物理气相沉积(PVD)方法,使用铝金属对栅沟槽进行填充时,在栅沟槽左上角和右上角会出现突起103和104,并且随着填充的进行,左右上角的突起103和104会连接到一起,并阻碍铝金属进一步填充入栅沟槽101内,最终出现如图1C的现象,在铝金属填充层106中形成了一个空洞105。 After 1A, the gate 101 formed on a channel-shaped semiconductor substrate 100 on which is deposited a wet metal material layer 102, a metal material may be shown like Ti or Co, and shown in Figure 1B, the physical vapor deposition (PVD) method, aluminum is used for metal gate trench is filled, the projections 103 and 104 appears in the upper left corner of the gate trench and the upper right corner, and the projections 103 and 104 with the filling, the upper right corner will be left connected together, and further hinder the aluminum filled in the trench gate 101, as shown in FIG. 1C eventually phenomenon, a hole 105 is formed in the aluminum metal layer 106 is filled.

[0004] 这种位于栅沟槽的金属填充物中的空洞会导致半导体器件性能降低,并可能在后续的工序中产生缺陷,进而降低产品的合格率,所以栅沟槽的金属填充物中的空洞成为业界必须解决的问题之一。 [0004] Such a metal of the gate trench fill voids in the semiconductor device can lead to reduced performance and may cause defects in the subsequent step, thereby reducing the yield of products, so that the gate metal filling the trenches voids become one of the industry must be addressed.

发明内容 SUMMARY

[0005] 针对现有技术的不足,本发明提供一种半导体器件的制造方法,包括:提供半导体衬底,在所述半导体衬底上形成有用于形成金属栅极结构的栅沟槽;对所述栅沟槽执行第一金属沉积步骤;对所述栅沟槽执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤,以扩大所述栅沟槽的开口尺寸;对所述栅沟槽执行第二金属沉积步骤。 [0005] for the deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a gate trench for forming a metal gate structure on the semiconductor substrate; of their said gate trench performing a first metal deposition step; said gate trench for performing an electrochemical reaction step of removing said gate projection trench top left and right, in order to expand the size of the opening of the gate trench; of their performing a second of said gate trench metal deposition step.

[0006] 进一步地,该制造方法还包括多次重复执行所述第一金属沉积步骤、所述执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤、第二金属沉积步骤。 [0006] Further, the manufacturing method further comprises repeatedly performing the step of depositing a first metal, said step of performing an electrochemical reaction removing said gate projection of the upper left corner and upper right corner of the trench, the second metal deposition step .

[0007] 进一步地,所述电化学反应中,所使用的电解液的阴离子为以下两种离子之一或者其组合:氯离子、氟离子。 [0007] Further, the electrochemical reaction, the electrolyte solution used in one of the following anions, or a combination of both ions: chloride ions, fluoride ions.

[0008] 进一步地,所述电化学反应中,所使用的电解液包括以下两种有机物之一或者其 [0008] Further, the electrochemical reaction, the electrolyte used comprises one of the following two organic compounds, or

组合:甲醇和丙三醇。 A combination of: Methanol and glycerol.

[0009] 进一步地,所述电化学反应中,所述甲醇的体积为800-900毫升。 [0009] Further, the electrochemical reaction, the methanol in a volume of 800-900 ml.

[0010] 进一步地,所述电化学反应中,所述丙三醇的体积为126-300毫升。 [0010] Further, the electrochemical reaction, the glycerol volume 126-300 ml.

[0011] 进一步地,所述电化学反应中,所使用的电解液包括NaBF4。 [0011] Further, the electrochemical reaction, the electrolyte used comprises NaBF4. [0012] 进一步地,所述电化学反应中,所使用的电解电压为50-100伏。 [0012] Further, the electrochemical reaction, the electrolysis voltage used is 50-100 volts.

[0013] 进一步地,所述电化学反应中,电解时间为5-60秒钟。 [0013] Further, the electrochemical reaction, the electrolysis time is from 5 to 60 seconds.

[0014] 进一步地,所述第一金属沉积步骤和/或第二金属沉积步骤使用以下方法之一:物理气相沉积或化学气相沉积。 [0014] Further, the first metal deposition step and / or the second metal deposition step using one of the following: physical vapor deposition or chemical vapor deposition.

[0015] 进一步地,对所述栅沟槽执行所述第一金属沉积步骤前,还包括在所述栅沟槽内沉积一湿金属材料层的步骤。 [0015] Furthermore, execution of the trench gate prior to said first step of metal deposition further comprises the step of depositing a layer of wet metal material within the gate trenches.

[0016] 进一步地,所述湿金属材料为Ti或者Co。 [0016] Further, the wet metal material is Ti or Co.

[0017] 进一步地,在所述第一金属沉积步骤和/或第二金属沉积步骤中还包括在沉积室或加热炉中对所述沉积的金属进行回流的步骤。 [0017] Further, in the first metal deposition step and / or the second metal deposition step further includes the step of refluxing the deposited metal to be deposited in a chamber or furnace.

[0018] 进一步地,所述回流步骤中使用的温度为300-500摄氏度,回流步骤的持续时间为20分钟-2小时。 [0018] Further, the temperature of the reflow step used is 300-500 ° C, the duration of step is refluxed for 20 minutes to 2 hours.

[0019] 根据本发明,通过在使用铝金属对栅沟槽进行填充时以形成栅极的过程中,进行一轮或者多轮的“金属沉积步骤-执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤-金属沉积步骤”过程,可以避免在金属间隙填充物中产生空洞,进而降低产品的合格率的问题。 [0019] According to the present invention, by using the aluminum metal during the process of filling the trench to form a gate in the gate, or for a "multiple rounds of metal deposition step - removing the electrochemical reaction performed upper left gate trench projection step and the top right corner - metal deposition step "process, to avoid the formation of voids in the metal filling in the gap, thereby reducing the yield of product problems.

附图说明 BRIEF DESCRIPTION

[0020] 本发明的下列附图在此作为本发明的一部分用于理解本发明。 [0020] The following figures of the present invention is used herein as part of the present invention to understand the invention. 附图中示出了本发明的实施例及其描述,用来解释本发明的原理。 In the embodiment shown and described embodiments of the present invention are shown, serve to explain the principles of the invention.

[0021] 附图中: [0021] In the drawings:

[0022] 图1A-1C示出了现有技术中在栅沟槽内填入金属栅材料的方法; [0022] Figures 1A-1C illustrate a method of the prior art metal gate material is filled in the gate trench;

[0023] 图2A-2H示出了本发明提出的在栅沟槽内填入金属栅材料的方法的各步骤的示意性剖面图; [0023] FIGS. 2A-2H illustrate a schematic cross-sectional view the steps of the method of the metal gate material is filled in the trench gate by the present invention;

[0024] 图3本发明提出的在栅沟槽内填入金属栅材料的方法的流程图。 [0024] The method of flowchart fill metal gate material within the gate trenches of the present invention presented in Fig.

具体实施方式 detailed description

[0025] 在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。 [0025] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. 然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。 However, those skilled in the art will be apparent that the present invention may be practiced without one or more of these details are implemented. 在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。 In other examples, in order to avoid confusion with the present invention, known in the art for some of the technical features are not described.

[0026] 为了彻底理解本发明,将在下列的描述中提出详细的步骤,以便阐释本发明提出的半导体器件的制造方法。 [0026] For a thorough understanding of the invention will be set forth in detail in the following in the description, to explain the method of manufacturing a semiconductor device proposed by the present invention. 显然,本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。 Obviously, the purposes of the present invention is not limited to the specific details of the semiconductor skilled in the art are familiar with. 本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。 As described in detail preferred embodiments of the present invention, however, in addition to the detailed description, the present invention also may have other embodiments.

[0027] 应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。 [0027] It should be appreciated that, when used in the present specification "comprises" and / or "including" when that specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0028] 下面,参照图2A-图2H和图3来描述本发明提出的在栅沟槽内填入金属栅材料的方法。 [0028] Next, with reference to Figure 3. The method of 2H and a metal gate material is filled in the trench made in the gate of the present invention is described in FIGS. 2A- FIG. [0029] 参照图2k_图2H,其中示出了本发明提出的在栅沟槽内填入金属栅材料的方法的各步骤的示意性剖面图。 [0029] Referring to FIG 2k_ FIG 2H, which shows a schematic sectional view the steps of the method of the metal gate material is filled in the trench gate by the present invention.

[0030] 首先,如图2A所示,提供半导体衬底200,所述半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)等。 [0030] First, as shown in FIG. 2A, a semiconductor substrate 200, the material constituting the semiconductor substrate 200 may employ undoped silicon, doped with impurities of silicon, silicon on insulator (SOI )Wait. 在本发明的一个实施例中,半导体衬底200选用单晶硅材料制成。 In one embodiment of the present invention, a semiconductor substrate 200 made of single crystal silicon material chosen. 虽然在此描述了可以形成衬底200的材料的几个实例,但是可以作为半导体衬底的任何材料均落入本发明的精神范围。 Although several examples described herein may be formed of a material of the substrate 200, but any material may be used as the semiconductor substrate fall within the spirit and scope of the present invention. 在所述半导体衬底200上表面生长一层栅极氧化层201,栅极氧化层201作为栅极电介质层,其材料可以是Si02、Si0N等,可以使用原子层沉积、化学气相沉积(CVD)或其它适合的方法,以上仅作为示例,不局限于此。 Growing a gate oxide layer surface on the semiconductor substrate 200 201, gate oxide layer 201 as the gate dielectric layer, which material can be Si02, Si0N the like, using an atomic layer deposition, chemical vapor deposition (CVD) or other suitable methods, the above example only, is not limited thereto. 在不同的情况中,栅极氧化层201可以采用不同的材料和不同的厚度。 In different situations, the gate oxide layer 201 may be of different materials and different thicknesses employed.

[0031] 然后,在所述半导体衬底200的栅极氧化层201上沉积多晶硅层202,如图2B所示。 [0031] Then, a polysilicon layer 202 is deposited on the gate oxide layer 201 of the semiconductor substrate 200, shown in Figure 2B. 多晶硅层202的材料可以为多晶硅或者掺杂金属杂质的多晶硅,所述金属杂质至少包括一种金属(例如钛,钽、钨等)以及金属硅化物。 The polysilicon material layer 202 may be doped polysilicon or polycrystalline metal impurity, the metal impurity comprises at least one metal (e.g. titanium, tantalum, tungsten, etc.) and a metal silicide. 形成多晶硅层202的方法包括原子层沉积、化学气相沉积(CVD)、等离子增强形化学气象沉积(PECVD)或其它适合的方法,接着在多晶硅层表面采用等离子体增强化学气相沉积(PECVD)工艺沉积氮化硅或氮氧化硅形成硬掩膜层。 The method of forming a polycrystalline silicon layer 202 comprises atomic layer deposition, chemical vapor deposition (CVD), plasma enhanced-shaped chemical vapor deposition (PECVD) or other suitable method, followed by plasma enhanced chemical vapor deposition (PECVD) process for depositing on the surface of the polycrystalline silicon layer silicon nitride or silicon oxide hard mask layer.

[0032] 在接下来的工艺步骤中,在上述硬掩膜层表面涂布光致抗蚀剂层,然后利用常规光刻工艺,例如曝光、显影、清洗等工艺图案化光致抗蚀剂层,以形成假栅205,如图2B所 [0032] In the next process step, the hard mask layer above the surface of coating a photoresist layer, and then using a conventional photolithographic process, such as exposure, development and cleaning processes patterned photoresist layer to form a dummy gate 205, as shown in FIG. 2B

/Jn ο / Jn ο

[0033] 在进行后续的移除假栅的步骤之前,可以进行任何其它的工艺,其它的工艺包含但不限于在所述假栅的两侧形成侧壁层、在衬底中形成源极/漏极区(如低掺杂的源极/漏极区)等常见半导体制造工艺,在此不赘述。 [0033] Before carrying out the subsequent step of removing the dummy gate may be any other process, other processes include, but are not limited to form sidewall layers on both sides of the dummy gate, a source in the substrate / drain regions (such as low-doped source / drain regions), and other common semiconductor fabrication process, which is not repeated herein.

[0034] 接着形成介电层如层间介电层(ILD)于衬底上,层间介电层206的形成方法可以为CVD、PECVD或其它合适方法。 [0034] Next a dielectric layer an interlayer dielectric (ILD) layer on a substrate, such as, a method of forming an interlayer dielectric layer 206 may be CVD, PECVD, or other suitable methods. 层间介电层206的组成含有氧化硅、氮氧化硅或其它合适的材料。 The interlayer dielectric layer 206 consisting of silicon oxide, silicon oxynitride, or other suitable material. 在一个实施例中,层间介电层206为PECVD方法形成的介电层。 In one embodiment the dielectric layer embodiment, an interlayer dielectric layer 206 is formed of a PECVD method. 然后将其平坦化,使用例如化学机械研磨方法(CMP),去除假栅205上沉积的介电层材料,直至暴露出假栅205上表面,如图2C所示。 Then planarized, for example, chemical mechanical polishing method (the CMP), the removal of the dielectric layer material deposited on the dummy gate 205, until the upper surface of dummy gate 205 is exposed, as shown in FIG. 2C.

[0035] 然后去除假栅205,以形成栅沟槽207,如图2D所示。 [0035] The dummy gate 205 is then removed to form a gate trench 207, shown in Figure 2D. 在一个实施例中,可以利用干法刻蚀或者湿法刻蚀技术等之一将所示假栅205刻蚀去除,从而形成栅沟槽207。 In one embodiment, one can use a dry or wet etching technique or the like as shown in the dummy gate 205 is removed by etching, whereby the gate trench 207 is formed. 在另一个实施例中,可以利用干法刻蚀或者湿法刻蚀技术进一步将栅极氧化层201去除,以形成暴露衬底的沟槽207,而后重新沉积高k栅介电层(未示出),该高k栅介电层采用高k介质材料(例如,和氧化硅相比,具有高介电常数的材料),高k介质材料的例子包括金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐,金属的氮氧化物、金属铝酸盐的组合或者其他合适的组成。 In another embodiment, the method may be a dry or wet etching techniques further gate oxide layer 201 is removed to form a trench exposing the substrate 207, and then re-deposited high-k gate dielectric layer (not shown out), the high-k gate dielectric layer of high-k dielectric material (e.g., compared with silicon oxide, a material having a high dielectric constant), examples of high-k dielectric materials include metal oxides, metal nitrides, metal silicon salts, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitride, metal aluminates, or other combinations of suitable composition.

[0036] 接着在栅沟槽207内填入金属栅材料。 [0036] Next filled metal gate material within the gate trenches 207. 在一个实施例中,可以首先在栅沟槽207表面沉积一个湿金属材料层208,所述金属材料可以为Ti或者Co等。 In one embodiment, the metal may be deposited first a wet surface of the gate material layer 207 in the trench 208, the metallic material may be Ti or Co and the like. 然后,在一个实施例中,通过例如物理气相沉积(PVD)或化学气相沉积(CVD)等方法的沉积方法,使用铝金属对栅沟槽进行填充。 Then, in one embodiment, by a deposition method, for example, a method of physical vapor deposition (PVD) or chemical vapor deposition (CVD) and the like, aluminum metal gate trench is filled. 该沉积步骤还可以包括在沉积室或者加热炉中对所述沉积的金属进行回流的步骤,该回流步骤中,使用的温度可以为300-500摄氏度,回流步骤的持续时间为20分钟-2小时。 The depositing step may further comprise the step of refluxing in the deposition chamber or furnace for the deposition of metal, the reflow step, the temperature of 300-500 degrees Celsius may be used, the duration of step is refluxed for 20 minutes to 2 hours . 在使用铝金属对栅沟槽填充的过程中,会在栅沟槽207左上角和右上角会出现突起209和210,阻塞铝金属通过栅沟槽207的上开口来继续填充栅沟槽,如图2E所示。 In using an aluminum metal gate in the trench is filled, the protrusion 209 will occur in the gate trench 210 and 207 top left and right, blocking aluminum metal to continue to fill the gate trench 207 by the gate trench openings, such as FIG. 2E.

[0037] 因此,接下来,需要进行去除栅沟槽207左上角和右上角的突起209和210的步骤,如图2F所示。 [0037] Accordingly, next, the need for removing the gate trench 207 projections 209 and top left and right of the step 210 shown in Figure 2F. 在去除栅沟槽207左上角和右上角的突起209和210的步骤中,可以使用电化学的方法。 In the step of removing the gate trench 207 and the upper left corner of the upper right corner of the projections 209 and 210, the electrochemical method may be used. 在该电化学方法中,将晶圆放入电解液213作为阳极,该电解液213可以含有阴离子,例如氯离子、氟离子等,则铝金属会部分溶解到电解液213中。 In the electrochemical process, the wafer 213 as the anode into the electrolyte, the electrolyte 213 may contain an anion such as chloride, fluoride, etc., aluminum is partially dissolved in the electrolytic solution 213. 在一个实施例中,电解液213中可以含有800-900毫升的甲醇、126-300毫升的丙三醇以及适量的NaBF4。 In one embodiment, the electrolytic solution may contain 213 ml of methanol 800-900, 126-300 ml of glycerol and an appropriate amount of NaBF4. 使用50-100伏的电解电压,电解时间大约5-60秒钟,则可以使栅沟槽207左上角和右上角的突起209和210溶解到电解液中,从而扩大栅沟槽的开口尺寸,如图2G所示。 Using an electrolytic voltage of 50-100 V, electrolysis time of about 5-60 seconds, the gate trench 207 may be protrusions 209 and 210 of the top left and right dissolved in the electrolyte, thereby expanding the size of the opening of the gate trench, shown in Figure 2G.

[0038] 然后,通过例如物理气相沉积(PVD)或化学气相沉积(CVD)等方法的沉积方法,继续向栅沟槽207内填充金属栅材料212,直至完成铝金属填充的步骤,并且完全避免栅沟槽形的金属填充物中的空洞,如图2H所示。 [0038] Then, by a deposition method, for example, a method of physical vapor deposition (PVD) or chemical vapor deposition (CVD) and the like, continues to fill the metal gate material into the gate trench 207 212, until completion of the step of filling the aluminum metal, and completely avoided shaped gate trench metal filler in the cavity, shown in Figure 2H. 该继续沉积的步骤还可以包括在沉积室或者加热炉中对所述沉积的金属进行回流的步骤,该回流步骤中,使用的温度可以为300-500摄氏度,回流步骤的持续时间为20分钟-2小时。 The continuation of the deposition step may further comprise the step of refluxing in the deposition chamber or furnace for the deposition of metal, the reflow step, the temperature of 300-500 degrees Celsius may be used, the duration of step is refluxed for 20 minutes - 2 hours. 在本发明的一个实施例中,可以进行一轮的“金属沉积步骤-去除所述栅沟槽左上角和右上角的突起的步骤-金属沉积步骤”的过程,即可完成栅极替代工艺,并避免在栅沟槽填充物中产生空洞。 In one embodiment of the present invention may be a "metal deposition step - the step of removing said gate projection of the top left and right corners of the grooves - the metal deposition step" process, alternative processes to complete the gate, and to avoid voids in the gate trench filler. 在本发明的另外的实施例中,可以多次重复执行“金属沉积步骤-去除所述栅沟槽左上角和右上角的突起的步骤-金属沉积步骤”,才能避免在栅沟槽填充物中产生空洞。 In a further embodiment of the present invention may be performed repeatedly "metal deposition step - the step of projecting the top left and right corners of removing the trench gate - metal deposition step", in order to avoid filling the gate trench voids.

[0039] 至此,完成了根据本发明示例性实施例的方法实施的全部工艺步骤。 [0039] This completes the process all the method steps according to an exemplary embodiment of the present invention embodiment. 接下来,可以通过后续工艺完成整个半导体器件的制作,所述后续工艺与传统的半导体器件加工工艺完全相同。 Subsequently, the entire semiconductor device can be accomplished by making a subsequent process, the subsequent process of a semiconductor device with a conventional process identical.

[0040] 参照图3,其中示出了本发明提出的在栅沟槽内填入金属栅材料的方法的流程图,用于简要示出整个制造工艺的流程。 [0040] Referring to FIG 3, which illustrates a flowchart of a metal gate material is filled in the trench gate by the present invention, illustrating a schematic overall flow of the manufacturing process.

[0041] 在步骤301中,提供半导体衬底,在所述半导体衬底上形成有用于形成金属栅极结构的栅沟槽; [0041] In step 301, a semiconductor substrate, forming a gate trench for forming a metal gate structure on the semiconductor substrate;

[0042] 在步骤302中,对所述栅沟槽执行第一金属沉积的步骤; [0042] In step 302, the step of performing a first gate metal deposition of the trench;

[0043] 在步骤303中,使用电化学方法去除所述栅沟槽左上角和右上角的突起,以扩大所述栅沟槽的开口尺寸; [0043] In step 303, using an electrochemical method of removing the upper left corner of the gate trench and the upper right corner of the projection, to expand the size of the opening of the gate trench;

[0044] 在步骤304中,对所述栅沟槽执行第二金属沉积步骤。 [0044] In step 304, the step of depositing a second metal gate trench performed. 可以根据需要,多次重复执行“金属沉积步骤-使用电化学方法去除所述栅沟槽左上角和右上角的突起的步骤-金属沉积步骤”,直至完成金属填充的步骤,并且完全避免金属间隙填充物中的空洞。 As needed, repeatedly perform "metal deposition step of - using an electrochemical method of removing a protrusion of the step gate trench top left and right of - the metal deposition step", until the metal filling step is completed, and the metal completely avoid gaps filler voids.

[0045] 根据本发明,通过在使用铝金属对栅沟槽进行填充时以形成栅极的过程中,进行一轮或者多轮的“金属沉积步骤-执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤-金属沉积步骤”过程,可以避免在金属间隙填充物中产生空洞,进而降低产品的合格率的问题。 [0045] According to the present invention, by using the aluminum metal during the process of filling the trench to form a gate in the gate, or for a "multiple rounds of metal deposition step - removing the electrochemical reaction performed upper left gate trench projection step and the top right corner - metal deposition step "process, to avoid the formation of voids in the metal filling in the gap, thereby reducing the yield of product problems.

[0046] 本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。 [0046] The present invention has been described by the above embodiments, it should be understood that the above examples are only for purposes of illustration and description, and are not intended to limit the invention within the scope of the described embodiments. 此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。 Moreover, those skilled in the art will be appreciated that the present invention is not limited to the above embodiment, in accordance with the teachings of the present invention may be made more of the variations and modifications, all such variations and modifications fall within the invention as claimed within the range. 本发明的保护范围由附属的权利要求书及其等效范围所界定。 The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (14)

  1. 1.一种半导体器件的制造方法,包括: 提供半导体衬底,在所述半导体衬底上形成有用于形成金属栅极结构的栅沟槽; 对所述栅沟槽执行第一金属沉积步骤; 对所述栅沟槽执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤,以扩大所述栅沟槽的开口尺寸; 对所述栅沟槽执行第二金属沉积步骤。 A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a gate trench for forming a metal gate structure on the semiconductor substrate; performing a first step of depositing metal on said gate trench; performing a second step of depositing said metal gate trench; electrochemical performs the step of removing the gate trench gate upper left corner of the projection and the upper right corner of the trench, to expand the size of the opening of the gate trench reaction.
  2. 2.根据权利要求1所述的方法,还包括多次重复执行所述第一金属沉积步骤、所述执行电化学反应去除所述栅沟槽左上角和右上角的突起的步骤、第二金属沉积步骤。 2. The method according to claim 1, further comprising repeatedly performing the step of depositing a first metal, said step of performing an electrochemical reaction removing said gate projection of the upper left corner and upper right corner of the trench, the second metal depositing step.
  3. 3.根据权利要求1所述的方法,其特征在于,所述电化学反应中,所使用的电解液的阴离子为以下两种离子之一或者其组合:氯离子、氟离子。 3. The method according to claim 1, characterized in that, the electrochemical reaction, the electrolyte used in one of two anionic ion, or a combination thereof: chloride ions, fluoride ions.
  4. 4.根据权利要求1所述的方法,其特征在于,所述电化学反应中,所使用的电解液包括以下两种有机物之一或者其组合:甲醇和丙三醇。 4. The method according to claim 1, wherein the electrochemical reaction, the electrolyte used in the organic material comprises one or combinations of two: methanol and glycerol.
  5. 5.根据权利要求4所述的方法,其特征在于,所述电化学反应中,所述甲醇的体积为800-900 毫升。 The method according to claim 4, characterized in that, the electrochemical reaction, the volume of 800-900 ml of methanol.
  6. 6.根据权利要求4所述的方法,其特征在于,所述电化学反应中,所述丙三醇的体积为126-300 毫升。 6. The method as claimed in claim 4, wherein said electrochemical reaction, the glycerol volume 126-300 ml.
  7. 7.根据权利要求1所述的方法,其特征在于,所述电化学反应中,所使用的电解液包括NaBF4O The method according to claim 1, wherein the electrochemical reaction, the electrolyte used comprises NaBF4O
  8. 8.根据权利要求1所述的方法,其特征在于,所述电化学反应中,所使用的电解电压为50-100 伏。 8. The method according to claim 1, wherein the electrochemical reaction, the electrolysis voltage used is 50-100 volts.
  9. 9.根据权利要求1所述的方法,其特征在于,所述电化学反应中,电解时间为5-60秒钟。 9. The method according to claim 1, wherein the electrochemical reaction, the electrolysis time is from 5 to 60 seconds.
  10. 10.根据权利要求1所述的方法,其特征在于,所述第一金属沉积步骤和/或第二金属沉积步骤使用以下方法之一:物理气相沉积或化学气相沉积。 10. The method according to claim 1, wherein the first metal deposition step and / or the second metal deposition step using one of the following: physical vapor deposition or chemical vapor deposition.
  11. 11.根据权利要求1所述的方法,其特征在于,对所述栅沟槽执行所述第一金属沉积步骤前,还包括在所述栅沟槽内沉积一湿金属材料层的步骤。 11. The method according to claim 1, wherein prior to said gate of said trench performing a first metal deposition step, further comprising the step of depositing a layer of wet metal material within the gate trenches.
  12. 12.根据权利要求11的方法,其特征在于,所述湿金属材料为Ti或者Co。 12. The method according to claim 11, wherein said metallic material is a wet Ti or Co.
  13. 13.根据权利要求1所述的方法,其特征在于,在所述第一金属沉积步骤和/或第二金属沉积步骤中还包括在沉积室或加热炉中对所述沉积的金属进行回流的步骤。 13. The method according to claim 1, wherein the first metal deposition step and / or the second metal deposition step further includes the deposition of metal at reflux in the deposition chamber of the furnace or step.
  14. 14.根据权利要求13所述的方法,其特征在于,所述回流步骤中使用的温度为300-500摄氏度,回流步骤的持续时间为20分钟-2小时。 14. The method according to claim 13, wherein the temperature of the reflow step used is 300-500 ° C, the duration of step is refluxed for 20 minutes to 2 hours.
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