CN106024699B - A kind of preparation method of autoregistration STI - Google Patents
A kind of preparation method of autoregistration STI Download PDFInfo
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- CN106024699B CN106024699B CN201610367958.3A CN201610367958A CN106024699B CN 106024699 B CN106024699 B CN 106024699B CN 201610367958 A CN201610367958 A CN 201610367958A CN 106024699 B CN106024699 B CN 106024699B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Abstract
The invention discloses the preparation methods of autoregistration STI a kind of, by using boiler tube LPCVD technique on shallow trench oxidation layer on inner wall one layer of certain thickness of regrowth and polysilicon sidewall layer in homogeneous thickness, steam consumption substrate silicon and the multi-crystal silicon floating bar silicon in steam annealing can effectively be prevented, change the edge thickness of tunnel oxide silicon layer not, it ensure that the quality of tunnel oxide silicon layer, and then improve the reliability of product.
Description
Technical field
The present invention relates to microelectronic fields, more particularly, to a kind of new autoregistration STI (Shallow Trench
Isolation, shallow trench isolation) technique.
Background technique
In the manufacture of Flash Product Process, STI corner has a significant impact to device performance.If turning is too sharp or oxygen
Change layer, which was recessed big city, causes electric field to be assembled, component failure.It is common to solve in order to reduce influence of the STI corner to device
Scheme is with autoregistration STI technique.This technology is simple with processing step, grid oxygen reliability is high and channel width uniformity
It the features such as good, is widely adopted, and provides low cost, high reliability, high storage density and voltage for flash memory fabrication and couple journey
The integrated technique spent.
STI is used to be isolated the storage unit of Flash.The structure of Flash storage unit successively includes tunnelling oxygen from the inside to surface
SiClx layer, floating gate layer, ONO (silicon oxide/silicon nitride/silicon oxide) layer and control grid layer, the wherein thickness pair of tunnel oxide silicon layer
Data retention and erasing/writing speed of data have important influence.In autoregistration STI technique, tunnel oxide silicon layer is
It grows at first, how to reduce influence of the subsequent process to tunnel oxide silicon layer thickness and quality, have great importance.
Fig. 1 a to Fig. 1 d embodies existing autoregistration STI processing step, as follows:
Firstly, successively growing tunnel oxide silicon layer 102, polycrystalline from inside to outside on the N-well substrate 101 doped with phosphorus
Silicon floating gate layer 103 and silicon nitride layer 104, such as Fig. 1 a,
Wherein tunnel oxide silicon layer 102 is using high-temperature thermal oxidation technique or moisture-generation process (ISSG, In in situ
Situ Steam Generation) preparation, then use N2O annealing；Floating polysilicon grid layer 103 is heavy using boiler tube low pressure chemical phase
Product technique (LPCVD technique)；Silicon nitride layer 104 uses boiler tube low-pressure chemical vapor deposition process (LPCVD technique)；
Secondly, by photoetching process formed mask graph, and be sequentially etched silicon nitride layer 104, floating polysilicon grid layer 103,
Tunnel oxide silicon layer 102 and silicon substrate 101 form shallow trench 110 as shown in Figure 1 b；
Third is grown shallow by quick thermal treatment process (RTP, Rapid Thermal Process) or ISSG technique
Trenched side-wall oxide layer 106, as illustrated in figure 1 c；
4th, shallow trench 110 is filled by high-aspect-ratio technique (HARP, High Aspect Ratio Process)
Silicon dioxide layer 105, anneals again after filling, autoregistration STI technique is completed, such as Fig. 1 d.
In above-mentioned four steps, there are a step steam annealing steps in the annealing of HARP technique, for removing HARP work
The gap of skill generallys use the method for raising annealing temperature to improve removal gap ability to realize, i.e., temperature is higher, empty
Gap improvement is better, and the temperature of general steam annealing is greater than 600 degree, and the time of steam annealing is greater than 30 minutes.In this mistake
Cheng Zhong, steam are spread in loose HARP, penetrate shallow trench sidewall oxide 106, and (are greater than 600 degree) and lining at high temperature
The silicon in silicon and floating polysilicon grid layer 103 in bottom 101 reacts, and generates silica product, i.e. steam consumes substrate
Silicon and multi-crystal silicon floating bar generate silica.This phenomenon causes 102 marginal portion of tunnelling silicon dioxide layer to thicken, such as circle in Fig. 1 d
The part of label is enclosed, the siliceous quantitative change of tunnel oxide is poor, therefore has seriously affected the reliability of product.
Summary of the invention
In order to achieve the object of the present invention, the present invention provides a kind of new autoregistration STI techniques, for solving existing skill
The technical issues of tunnel oxide silicon layer edge thickens in art, and quality is deteriorated.
To achieve the above object, technical scheme is as follows:
A kind of preparation method of new autoregistration STI, as shown in Fig. 2 and Fig. 3 a to Fig. 3 e, which is characterized in that including as follows
Step:
Step S01: semi-conductive substrate 201 is provided, and successively grows tunnel oxide silicon layer in the semiconductor substrate 201
202, floating polysilicon grid layer 203 and silicon nitride layer 204, as shown in Figure 3a；
Step S02: mask graph is formed by photoetching process, and is sequentially etched silicon nitride layer 204, floating polysilicon grid layer
203, tunnel oxide silicon layer 202 and silicon substrate 201 form the shallow trench 210 being deep in silicon substrate 201, as shown in Figure 3b；
Step S03: oxide layer 206 is grown in 210 inner wall surface of shallow trench, as shown in Figure 3c；
Step S04: in the long one layer of polysilicon sidewall layer 207 of above-mentioned shallow ditch groove structure surface regeneration, as shown in Figure 3c；
Step S05: being filled 205 to shallow trench 210, such as Fig. 3 d, and anneals, final structure is obtained, such as Fig. 3 e.
Further, in step S04, with SixHyFor reactant, polysilicon sidewall layer is formed using boiler tube LPCVD technique
207。
Further, the polysilicon sidewall layer 207 with a thickness of 20~40 angstroms.
Further, the boiler tube LPCVD technological temperature is 400~450 degree, and pressure is less than 0.5 support.
Further, the SixHyFor Si2H6。
Further, in step S01, using ISSG technique or low pressure free-radical oxidation technique (Low Pressure
Radical Oxidization, LPRO) preparation tunnel oxide silicon layer 202, then use N2O annealing.
Further, in step S01, floating polysilicon grid layer 203 is prepared using boiler tube low-pressure chemical vapor deposition process.
Further, in step S01, silicon nitride layer 204 is prepared using boiler tube low-pressure chemical vapor deposition process.
Further, in step S03, oxide layer is grown in shallow trench inner wall surface using RTP technique or ISSG technique
206。
Further, in step S05, shallow trench oxide filling 205 is carried out using HARP technique.
New autoregistration STI technique of the invention, by growth shallow trench sidewall oxide 206 and then in the oxygen
The method for changing one layer of polysilicon sidewall layer 207 of regrowth on layer, is not only effectively guaranteed the thickness of polysilicon sidewall layer 207
The uniformity, and steam is prevented (consumption) by polysilicon sidewall layer 207, i.e., and substrate silicon 201 and polysilicon is no longer consumed in steam
Floating gate 203,202 edge thickness of tunnel oxide silicon layer no longer thicken, and ensure that the reliability of product, and therefore, the present invention has aobvious
Work feature.
Detailed description of the invention
Fig. 1 a to Fig. 1 d is the autoregistration STI process diagram of the prior art；
Fig. 2 is autoregistration STI processing step of the invention；
Fig. 3 a to Fig. 3 e is autoregistration STI process diagram of the invention.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
Those skilled in the art can be understood easily other advantages and function of the invention by content disclosed by this specification
Effect.The present invention can also be embodied or applied by other different embodiments, the various details in this specification
Various modifications or alterations can also be without departing from the spirit of the present invention carried out based on different viewpoints and application.
In specific embodiment of the invention below, Fig. 2 and Fig. 3 a to Fig. 3 e is please referred to, Fig. 2 is of the invention from right
Quasi- STI processing step, Fig. 3 a to Fig. 3 e are autoregistration STI process diagrams of the invention.As shown, its show it is of the invention new
Autoregistration STI preparation method, steps are as follows:
Step S01: semi-conductive substrate 201 is provided, and successively grows tunnel oxide silicon layer in the semiconductor substrate 201
202, floating polysilicon grid layer 203 and silicon nitride layer 204, as shown in Figure 3a；
Semiconductor substrate 201 in the step can be original or extension semiconductor material, including pure monocrystalline silicon, p
It type silicon, n-type silicon, group Ⅲ-Ⅴ compound semiconductor material, group Ⅱ-Ⅵ compound semiconductor material and is wrapped in above-mentioned material
Semiconductor material etc. containing electronic device.As a preferred embodiment, semiconductor base is the N-well substrate doped with phosphorus.
In the step, as a preferred embodiment, tunnel oxide silicon layer 202 is prepared using ISSG technique or LPRO technique,
N is used again2O annealing.ISSG technique or LPRO technique are that a kind of New Low Voltage quickly aoxidizes thermal annealing technology, are currently used primarily in super
Thin oxide film growth, the preparation of sacrificial oxide layer and nitrogen oxygen film.ISSG technique is the reaction in a kind of reaction chamber, is used
The oxygen of a small amount of hydrogen is mixed as reaction atmosphere, hydrogen and oxygen generate the chemical reaction for being similar to burning at high temperature, raw
At a large amount of gas-phase activity free radical, wherein mainly elemental oxygen, due to the strong oxidation of elemental oxygen, finally obtained oxidation
Defect is few in object thin-film body, and interface state density is also smaller.LPRO technique is the reaction in a kind of boiler tube, reaction mechanism and ISSG
Technique is identical, and therefore not to repeat here.
In the step, as a preferred embodiment, floating polysilicon grid layer 203 uses boiler tube low-pressure chemical vapor deposition process,
It is passed through silane in the process cavity of equipment, silane decomposes, and polycrystalline silicon growth or is deposited on silicon chip surface.
In the step, as a preferred embodiment, silicon nitride layer 204 uses boiler tube low-pressure chemical vapor deposition process, is setting
Ammonia reacts with dichlorosilane in standby cavity, growth or deposit silicon nitride layer on the surface of silicon wafer.
Above-mentioned tunnel oxide silicon layer 202, floating polysilicon grid layer 203 and the growth of silicon nitride layer 204 and preparation method are all made of
Oxidation well known to those skilled in the art and chemical vapor deposition process.
Above-mentioned tunnel oxide silicon layer 202, the thickness of floating polysilicon grid layer 203 and silicon nitride layer 204 and the phase between them
Comparative example, it is different with effect according to process, have different ranges, thickness shown in the drawings and comparing between them
Example cannot function as limitation of the present invention.
Step S02: mask graph is formed by photoetching process, and is sequentially etched silicon nitride layer 204, floating polysilicon grid layer
203, tunnel oxide silicon layer 202 and silicon substrate 201 form the shallow trench 210 being deep in silicon substrate 201, as shown in Figure 3b；
The entire photoetching process that the step is completed is needed using complicated multistep process, including the manufacture of reprint graphic mask,
The processes such as coating, preliminary drying, exposure, development, rear baking, burn into and the photoresist removal of silicon substrate surface photoresist, are all made of
Technique well known to those skilled in the art, this will not be repeated here.
Step S03: oxide layer 206 is grown in 210 inner wall surface of shallow trench, as shown in Figure 3c；
In the step, oxide layer is grown in shallow trench inner wall surface using RTP technique or ISSG technique, usually in normal pressure
Under be passed through O2Or N2Diluted O2, the oxide layer 206 that oxidation forms silica membrane is carried out under 800~1000 DEG C of high temperature, such as
Shown in Fig. 3 c.Growing the oxide layer is the i.e. reparation step S02 in order to improve the interfacial characteristics between silicon and trench fill oxide
The silicon of semiconductor base 201 is damaged in etching process, while repairing 210 wedge angle of groove, keeps groove 210 more smooth, favorably
In subsequent being sufficient filling with to groove 210.It is technique well known to those skilled in the art, and this will not be repeated here.
Step S04: in the long one layer of polysilicon sidewall layer 207 of above-mentioned shallow ditch groove structure surface regeneration, as shown in Figure 3c；
In the step, the Chemical Vapor Depo-sition Method for being formed by low-temp low-pressure of polysilicon sidewall layer 207 is realized, 400
SixHy gas, such as SiH are passed through at a temperature of~600 degree of degree4Gas or Si2H6Gas, under the chamber pressure less than 0.5 support
It reacts, when being passed through SiH4When gas, pyrolysis occurs, in the growth of sidewall oxidation layer surface or depositing polysilicon, instead
It should be as follows:
SiH4→SiH2+H2
SiH4+SiH2→Si2H6
Si2H6→2Si+3H2
When being passed through Si2H6When gas, react as follows:
Si2H6→2Si+3H2
The step can grow the uniform polysilicon sidewall layer 207 of a layer thickness on whole figure surface, i.e. shallow trench is each
207 consistency of thickness of polysilicon sidewall layer of position.Preferably, 400 degree~450 degree at a temperature of be passed through Si2H6Gas, small
It reacts under the chamber pressure of 0.5 support, better thickness uniformity and controllable thickness can be obtained.
The thickness of the polysilicon sidewall layer 207 cannot be too thin, too thin effectively to prevent steam, can not be too
Thickness, the too thick difficulty that will increase HARP filling, and generates groove gap, i.e., the thickness of polysilicon sidewall layer 207 not only with annealing
Temperature and time wants corresponding, also to take into account HARP filling.Preferably, the polysilicon sidewall layer 207 with a thickness of 20~40
Angstrom.
It is step S05 in order to prevent in the effect of the long one layer of polysilicon sidewall layer 207 of above-mentioned shallow ditch groove structure surface regeneration
Silicon in the steam consumption substrate silicon and multi-crystal silicon floating bar of middle generation, changes the thickness of tunnel oxide silicon layer, to reduce production
The reliability of product.
Step S05: shallow trench 210 is filled, and is annealed, as shown in Figure 3d.
In the step, as shown in Figure 3d, silicon dioxide layer 205 is filled to shallow trench using HARP technique, and be respectively adopted
Steam annealing and n 2 annealing, complete autoregistration STI technique.HARP technique and the subsequent anneal processing used in the step is adopted
With technique well known to those skilled in the art, this will not be repeated here.When using steam annealing, raising annealing temperature is generallyd use
Method come improve removal gap ability, temperature is higher, and gap improvement is better.In the step, the temperature of steam annealing
Greater than 600 degree, the time of steam annealing is greater than 30 minutes.The polysilicon sidewall layer 207 generated in steam and step S04 is changed
Learn reaction:
H2O+Si→SiO2+H2
Polysilicon sidewall layer 207 is consumed, steam infiltration consumption substrate silicon and multi-crystal silicon floating bar silicon are prevented, therefore,
The thickness of tunnel oxide silicon layer 202 does not change, and as shown in Figure 3 e, the quality of tunnel oxide silicon layer has been effectively ensured.
New autoregistration STI technique of the invention, using the Si of boiler tube low-temp low-pressure2H6Technique makes increased polysilicon side
Consistency of thickness and thickness of the parietal layer in each position of shallow trench are controllable；Increased polysilicon sidewall layer, by limiting its thickness model
It encloses, can not only effectively prevent steam consumption substrate silicon and the multi-crystal silicon floating bar silicon in annealing, make the side of tunnel oxide silicon layer
Edge thickness does not change, and ensure that the quality of tunnel oxide silicon layer, and then ensure that the reliability of product, and takes into account HARP and fill out
It fills, avoids generating groove gap.Therefore, the present invention has outstanding feature.
Above-described to be merely a preferred embodiment of the present invention, the patent that the embodiment is not intended to limit the invention is protected
Range is protected, therefore all with the variation of equivalent structure made by specification and accompanying drawing content of the invention, similarly should be included in
In protection scope of the present invention.
Claims (8)
1. a kind of preparation method of autoregistration STI, which comprises the steps of:
Step S01: semi-conductive substrate is provided, and successively grows tunnel oxide silicon layer, floating polysilicon in the semiconductor substrate
Grid layer and silicon nitride layer；
Step S02: mask graph is formed by photoetching process, and is sequentially etched silicon nitride layer, floating polysilicon grid layer, tunnel oxide
Silicon layer and silicon substrate form the shallow trench being deep in silicon substrate；
Step S03: oxide layer is grown in shallow trench inner wall surface；
Step S04: it is passed through SiH4Gas or Si2H6Gas, using boiler tube LPCVD technique in above-mentioned shallow ditch groove structure surface regeneration
Long one layer of polysilicon sidewall layer, when being passed through SiH4When gas, pyrolysis occurs, grows or deposits in sidewall oxidation layer surface
Polysilicon reacts as follows:
SiH4→SiH2+H2
SiH4+SiH2→Si2H6
Si2H6→2Si+3H2
When being passed through Si2H6When gas, react as follows:
Si2H6→2Si+3H2；
Step S05: being filled shallow trench, and anneals.
2. the preparation method of autoregistration STI according to claim 1, which is characterized in that the thickness of the polysilicon sidewall layer
Degree is 20~40 angstroms.
3. the preparation method of autoregistration STI according to claim 1 or 2, which is characterized in that the boiler tube LPCVD technique
Temperature is 400~450 degree, and pressure is less than 0.5 support.
4. the preparation method of autoregistration STI according to claim 1, which is characterized in that in step S01, using ISSG work
Skill or LPRO technique prepare tunnel oxide silicon layer, then use N2O annealing.
5. the preparation method of autoregistration STI according to claim 1, which is characterized in that low using boiler tube in step S01
Pressure chemical vapor deposition technique prepares floating polysilicon grid layer.
6. the preparation method of autoregistration STI according to claim 1, which is characterized in that low using boiler tube in step S01
Pressure chemical vapor deposition technique prepares silicon nitride layer.
7. the preparation method of autoregistration STI according to claim 1, which is characterized in that in step S03, using RTP technique
Or ISSG technique grows oxide layer in shallow trench inner wall surface.
8. the preparation method of autoregistration STI according to claim 1, which is characterized in that in step S05, using HARP work
Skill carries out shallow trench oxide filling.
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| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
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| US6358796B1 (en) * | 1999-04-15 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation |
| US6451654B1 (en) * | 2001-12-18 | 2002-09-17 | Nanya Technology Corporation | Process for fabricating self-aligned split gate flash memory |
| CN104091780A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Self-alignment STI forming method |
| CN105097570A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Passivation layer manufacturing method and high-voltage semiconductor power device |
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- 2016-05-30 CN CN201610367958.3A patent/CN106024699B/en active Active
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|---|---|---|---|---|
| US6358796B1 (en) * | 1999-04-15 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation |
| US6451654B1 (en) * | 2001-12-18 | 2002-09-17 | Nanya Technology Corporation | Process for fabricating self-aligned split gate flash memory |
| CN105097570A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Passivation layer manufacturing method and high-voltage semiconductor power device |
| CN104091780A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Self-alignment STI forming method |
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