CN1466192A - Method for promoting performance of flash memory by using microcrystalline silicon film as floating gate - Google Patents

Abstract

This invention relates to a method for adding Hydrogen into silane when it forms polysilicon to turn it to micro crystal lattice. When the micro crystal-lattice of polysilicon is used in the floating gate of a flash memory, it can improve its element property.

Description

Method for using microcrystalline silicon film as floating gate to promote flash memory performance

(1) Field of the invention

The present invention relates to a flash memory, and more particularly, to a method for improving the performance of a flash memory by using a floating gate of a microcrystalline silicon film.

(2) Background of the invention

A typical flash memory device includes a memory array arranged in rows and columns as a plurality of memory cells, each cell including a floating gate field effect transistor for storing charge, the cells being generally grouped into blocks, each cell in each block being operable by charging of the floating gate as a random electrical operation process by which charge can be removed from the floating gate by a block eraseprocess, the presence or erasure of charge in the floating gate determining the storage of data in the cell.

Fig. 1 is a cross-sectional view of a typical memory cell 5 used in a flash memory. The memory cell 5 comprises an emitter 60 region and a collector 70 region, the emitter 60 and the collector 70 being separated by a channel region 80. The memory cell 5 further includes: a floating gate 30 formed of a first polysilicon layer, a control gate 50 formed of a second polysilicon layer, the floating gate 30 and the control gate 50 being separated by an interpoly dielectric layer 40, the floating gate 30 and the channel 80 region being separated by a thin oxide (tunnel oxide) 20 of about 100 angstroms thickness.

Fig. 2 is a cross-sectional view of a floating gate formed using a polysilicon layer 84 over a substrate 82, such as a tunnel oxide layer. The polysilicon layer 84 is formed by low pressure chemical vapor deposition at about 600 deg.C using Silane (SiH)₄) Polysilicon is deposited on the surface of the substrate 82. The large columnar crystals cause surface irregularities of the polycrystalline silicon layer 84, and such surface irregularities make it difficult to obtain a good pattern transfer pattern, resulting in significant deformation of the inside of the photoresist layer due to grain shape of the surface of the polycrystalline silicon layer 84 and non-uniform reflection during the pattern transfer, resulting in poor etching pattern due to non-uniform reflection of the photoresist layer, and easily causing residue of the polycrystalline silicon layer 25.

Fig. 3 is a cross-sectional view of another polysilicon layer 88 as a floating gate formed on a substrate 86, such as a tunnel oxide layer. Polysilicon layer 88 is formed by depositing silicon on the surface of substrate 86 using low pressure chemical vapor deposition at a temperature of about 550 c. Depositing silicon at such low temperatures produces amorphous silicon because grains cannot be formed at such low temperatures. The amorphous silicon is then recrystallized by exposure to a temperature of about 600 ℃. The final recrystallized structure is shown in FIG. 3, which has large grain formation. While the polysilicon layer 88 shown in fig. 3 also has the disadvantage of surface irregularities as shown in fig. 2, the large grain size in the polysilicon layer 88 reduces the grain boundary density in the film. In addition, because polysilicon layer 88 is deposited at low temperatures, the deposition rate is relatively reduced, resulting in slow throughput cycles.

The storage or erase operation of a flash memory is usually performed by Fowler-Nordheim mode, as shown in fig. 1, in which electrons tunnel through a thin tunnel oxide layer, typically 100 angstroms thick, between the floating gate and the channel. For the charge mode of flash memory, hot carriers can also be used to tunnel through the tunnel to the floating gate and be stored in the floating gate. In the hot carrier writing action of the flash memory, the control gate and the collector are connected with positive charges, and the emitter is connected with the ground wire. The erasing operation is performed by applying a high voltage between the control gate and the channel by Fowler-Nordheim method.

The overerase operation of the memory cell has a shorter cycle erase speed, meaning that higher current flows through the tunnel oxide. When large-grained polysilicon floating gates are used, a wider range of threshold voltage (Vt) distributions are induced. If the overerased region exists, there will be a tail-like distribution and a large variation value outside the distribution range of the erase initiation voltage. On the other hand, a wider erase threshold voltage distribution is associated with large grain polysilicon.

In the conventional flash memory process, theuse of large-grained polysilicon film as floating gate causes many defects, such as the problems of over-Fast Erase (Fast Erase) or over-write (Fast program), wide threshold voltage distribution and the associated tail-like distribution, the degradation of tunneling oxide layer, the higher resistance of polysilicon and the poor etching appearance, which results in polysilicon residue.

(3) Summary of the invention

The present invention provides a method for improving the performance of a flash memory by using microcrystalline silicon as a floating gate of a memory cell, so as to overcome the problems of wide erase threshold voltage distribution and tailing distribution of the memory cell, overerase of the memory cell, improve the performance of a tunnel oxide layer of the memory cell, improve the etching appearance of the floating gate, and reduce the resistance of the floating gate.

The method for improving the performance of the flash memory by using microcrystalline silicon as a floating gate comprises the following steps: providing a substrate, wherein the substrate comprises an emitter region and a collector region, and is separated by a channel region; a tunnel oxide layer formed on the substrate; forming a microcrystalline silicon layer on the tunneling oxide layer by using a low-pressure chemical vapor deposition method, selecting silane or disilane as a material, and introducing hydrogen gas to form the microcrystalline silicon layer; an interpoly dielectric layer formed on the microcrystalline silicon layer; a polysilicon layer as control gate formed on the interpoly dielectric layer; finally, the polysilicon layer, the interpoly dielectric layer, the microcrystalline silicon layer and the tunnel oxide layer are etched to form a base electrode to form a memory cell.

The memory cell of theinvention uses microcrystalline silicon as the floating gate material, the low electron affinity is the characteristic used in the flash memory, and the microcrystalline grain shows the low electron affinity more obviously. Using low electron affinity materials as floating gates provides reduced barrier to tunnel oxide interfaces, reducing the tunneling distance generally increases the electron tunneling probability. These problems can be solved by using a floating gate with low electron affinity, so that a low barrier promotes electron escape or removal by punch-through. The lower voltage required for low barrier, similar to the tunneling distance, results in faster erase times and reduced damage as a result of the erase operation.

For further explanation of the objects, structural features and effects of the present invention, the present invention will be described in detail with reference to the accompanying drawings.

(4) Description of the drawings

Fig. 1 is a cross-sectional view of a prior art memory cell;

FIG. 2 is an enlarged cross-sectional view of a substrate using a polysilicon film floating gate;

FIG. 3 is an enlarged cross-sectional view of a substrate with a floating gate of recrystallized silicon film;

FIG. 4 is a cross-sectional view of a memory cell of the present invention in which a microcrystalline silicon film is used as a floating gate;

FIG. 5 is an enlarged cross-sectional view of a substrate with a microcrystalline silicon film as a floating gate according to the present invention;

FIG. 6A is a schematic diagram of an oxide gap showing a large grain and a small oxide gap formed in a memory cell;

FIG. 6B is a schematic diagram of an oxide gap showing small grains and multiple oxide gaps formed in one memory cell;

FIG. 7 shows a comparison of breakdown voltage values of tunnel oxide layers using microcrystalline silicon and polysilicon floating gates;

FIG. 8 is a graph showing a comparison of electron trapping rates of tunnel oxide layers using microcrystalline silicon and polysilicon floating gates.

(5) Detailed description of the preferred embodiments

The present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, a method for improving the performance of a flash memory by using microcrystalline silicon (microcrystalline silicon film) as a floating gate is provided.

Fig. 4 shows a cross-sectional view of a memory cell 100 in which a prior art polysilicon film floating gate is replaced by a microcrystalline silicon film floating gate 120. The memory cell 100 includes an emitter 150 region and a collector 160 region, the emitter 150 and collector 160 being separated by a channel 170 region. The memory cell 100 further includes: a floating gate 120 formed of a microcrystalline silicon film; a control gate 140 formed of a polysilicon layer; the floating gate 120 and the control gate 140 are separated by an interpoly dielectric layer 130, such as an oxide-nitride-oxide (ONO layer), the floating gate 120 and the channel 170 regions are separated by a gate dielectric layer 110, such as silicon oxide, the interpoly dielectric layer 130 and the gate dielectric layer 110 are insulating layers, and the gate dielectric layer functions as an electron tunneling oxide.

FIG. 5 is an enlarged cross-sectional view of the embodiment using a microcrystalline silicon film 174 as a floating gate, wherein the microcrystalline silicon film 174 is formed on a substrate 172, and the microcrystalline silicon film 174 is formed by introducing hydrogen into a silicon deposition chamber. In the present embodiment, silane is used as a material and hydrogen is simultaneously introduced to deposit a microcrystalline silicon film, and in another embodiment, disilane is used as a material and hydrogen is simultaneously introduced to deposit a microcrystalline silicon film. The average size of the grains of the microcrystalline silicon film 174 is between about 500 a and about 1000 a, and the grain size of the microcrystalline silicon film 174 is defined by the average diameter of the grains.

The grains cannot have a uniform profile, but have an average diameter of about 500 to 1000 angstroms. Low pressure chemical vapor deposition or other deposition methods can be used to deposit thin films. In this embodiment, the parameters of the low pressure chemical vapor deposition method are as follows: the pressure is controlled to be 200-400 torr, the temperature is controlled to be 700-750 ℃, and the flow ratio of the hydrogen and the nitrogen is 5-60% (5-60% hydrogen/100% (hydrogen + nitrogen)). The floating gate can be formed by the same processes as pattern transfer and etching in the conventional polysilicon floating gate forming method.

The main reaction process is . In conventional polysilicon films, the high surface diffusion rate of silicon atoms outperforms the nucleation rate, resulting in large grains and growth rates. In contrast, microcrystalline silicon can be suppressed to have a slower diffusion rate and a slower grain growth rate, but does not affect the nucleation rate. Thus, nucleation rates outweigh diffusion rates will result in smaller grain size formation.

Note that in this embodiment,the grain boundary density of the microcrystalline silicon film 174 is significantly increased compared to the large columnar grains of fig. 2 or compared to fig. 3, and the grain size of the microcrystalline silicon film 174 is significantly reduced. Since the grain boundary density of the microcrystalline silicon film 174 is significantly greater than that of a polycrystalline silicon film, such as the polycrystalline silicon film of fig. 2, the diffusion of the dopant in the microcrystalline silicon film 174 can be improved, and the dopant penetrating close to the surface of the microcrystalline silicon film 174 can easily penetrate the microcrystalline silicon film 174 along the grain boundary of high density. As a result, the dopant concentration penetrating the microcrystalline silicon film 174 promotes the conductivity of the microcrystalline silicon film 174, which is more uniform in electric field than the recrystallized amorphous silicon film shown in fig. 3.

On the other hand, the microcrystalline silicon film 174 has a reduced average crystal grain size compared to the conventional polycrystalline silicon film shown in fig. 2, and the planarization of the surface of the microcrystalline film 174 is further promoted. The grain size miniaturization of the microcrystalline silicon film 174 is a significant effect on the film surface in the present invention. In addition, as the microcrystalline silicon film 174 process parameters are adjusted to increase or decrease the average grain size, the surface irregularities of the film increase or decrease, respectively. By planarizing the surface of the microcrystalline silicon film 174, the variation in the internal thickness of the photoresist during photolithography is relatively reduced, resulting in more uniform reflection than the conventional polysilicon film shown in FIG. 2, thereby improving the resolution of the base edge.

Finally, this can be illustrated in tunnel oxide layers 180, 180A by "oxide valley", as shown in FIGS. 6A and 6B. In a conventional process, a high concentration of phosphorus is doped in the silicon oxide region, and an oxide gap 194 is formed at the interface of the polysilicon grains 192. All of the polysilicon grains 192 are relative to the total length of the oxide gap 194. When polysilicon with large-sized grains is used, only a few grains exist in one erase unit, for example, when only five polysilicon grains exist in one erase unit, each polysilicon grain 192 accounts for 20% of erase operations, so that one polysilicon grain 192 has a large error in erase speed and a wide erase start voltage distribution.

Second, as shown in FIG. 6B, the plurality of oxide slits 194A can achieve substantially the same erase speed for each cell of the memory array. On the other hand, with microcrystalline silicon using small grains 192A, there are many grains 192A present in one erase unit. For example, when fifty microcrystalline silicon grains 192A exist in one erase unit, the erase operation of each microcrystalline silicon grain 192A is only 2%. Therefore, each of the grains 192A has the same erase speed, a narrower erase threshold voltage can be achieved, a large erase region with a large distribution range contains a large number of microcrystalline silicon grains 192A, and a uniform erase speed and narrow erase threshold voltage distribution can be obtained.

The base voltage directly determines the magnitude of the base current and the base current is the most significant contributor to breakdown due to breakdown caused by breakdown of the tunnel oxide dielectric in the process. In this embodiment, the charge-to-breakdown voltage (Qbd) and the electron trapping rate (trapping rate) of the tunnel oxide layer were measured using the microcrystalline silicon floating gate and the polysilicon floating gate of the prior art, respectively. As shown in table one, the thicknesses of tunnel oxidelayers using microcrystalline silicon and polycrystalline silicon were the same as measured by CV and FV methods, and each data in the table was an average value obtained by three tests per wafer.

As shown in fig. 7, the a pillar is a tunnel oxide layer using a microcrystalline silicon floating gate, and the B pillar is a tunnel oxide layer using a polysilicon floating gate, which shows that the tunnel oxide layer has a higher electron injection efficiency and a larger breakdown voltage value using the microcrystalline silicon floating gate according to the present invention. In addition, as shown in fig. 8, the C pillar is a tunnel oxide layer using a microcrystalline silicon floating gate, and the D pillar is a tunnel oxide layer using a polysilicon floating gate, it can be seen that the tunnel oxide layer using the microcrystalline silicon floating gate of the present invention has a lower electron trapping rate, and thus better device reliability of the flash memory can be obtained. The use of microcrystalline silicon with a smaller size, with multiple grains present in the floating gate, can reduce the electron trapping rate of the tunnel oxide layer, thereby improving the functionality of the flash memory.

The first table shows the test data of the thickness, breakdown voltage, and electron capture rate of each tunnel oxide layer using microcrystalline silicon and polysilicon floating gates.

Watch 1

Wafer with a plurality of chips	Film	Thickness (CV) (Angstrom)	Thickness (FV) (Angstrom)	Breakdown voltage	Electronic capture Rate of change
						Coulomb/square Centimeter	Electron/billion
				1	Using a microcrystalline silicon film			105.0	103.6	23.50	0.030
2	104.2	103.6	23.02			0.033
				3			104.6	103.6	22.04	0.033
4	104.6	103.6	21.66			0.027
				11			Using a polycrystalline silicon film	104.8	103.6	13.82	0.028
12	104.6	103.6	14.14		0.031
				13		104.6		103.6	14.74	0.031
14	104.8	103.6	14.94		0.032
				15		104.6		103.6	14.47	0.031
16	104.4	103.6	15.12		0.035
				17		104.8		103.6	16.34	0.037
18	104.4	103.6	13.70		0.036
				19		104.8		103.6	16.10	0.036
20	104.4	103.6	16.02		0.035
				21		104.4		103.6	15.79	0.035

Of course, those skilled in the art will recognize that the above-described embodiments are illustrative only, and not intended to be limiting, and that changes and modifications of the above-described embodiments are intended to be within the scope of the appended claims, as they fall within the true spirit and scope of the present invention.

Claims (6)

1. A method for improving the performance of a flash memory by using a microcrystalline silicon film as a floating gate, comprising:

providing a substrate; and

forming a polysilicon layer on the substrate, and decomposing silane and introducing hydrogen to make the polysilicon layer microcrystalline silicon.

2. The method of claim 1, wherein the method comprises using a low pressure chemical vapor deposition process.

3. The method of claim 2, comprising controlling the temperature to about 700 ℃ to about 750 ℃.

4. The method of claim 2, comprising controlling the pressure to about 200 torr to 400 torr.

5. The method of claim 1, wherein the gas flow rate in the method is 5-60% hydrogen/(hydrogen + nitrogen).

6. The method of claim 1, wherein the decomposition substance is selected from the group consisting of silane and disilane.

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