KR20080041478A - Non-volatile memory device having charge trapping layer and method for fabricating the same - Google Patents

Abstract

An NVM(non-volatile memory) device with a charge trap layer is provided to improve a program speed by including a charge trap layer having a large quantity of uniform trap sites. A tunneling layer(210) is formed on a semiconductor substrate(200). A charge trap layer(220) is disposed on the tunneling layer, having a trap site doped with donor impurities. A shield layer(230) is disposed on the charge trap layer to shield the transfer of charges. A control gate electrode(250) is disposed on the shield layer to apply a predetermined bias to a cell. The charge trap layer can be a stack structure composed of a lower trap layer doped with donor impurities and an upper trap layer.

Description

Non-volatile memory device having a charge trap layer and a method of manufacturing the same {Non-volatile memory device having charge trapping layer and method for fabricating the same}

1 is a cross-sectional view illustrating a nonvolatile memory device having a general charge trap layer.

2 is a cross-sectional view illustrating a nonvolatile memory device having a charge trap layer according to an embodiment of the present invention.

3 to 6 are cross-sectional views illustrating an example of a method of manufacturing a nonvolatile memory device having a charge trap layer according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same. In particular, a nonvolatile memory device having a charge trap layer having a large amount of uniform trap sites formed therein and having greatly improved program and erase characteristics thereof, and a manufacturing method thereof It is about a method.

Nonvolatile memory devices are widely used in electronic components that require information maintenance even when power is cut off. An important dielectric film structure in a nonvolatile memory device is an ONO (Oxide-Nitride-Oxide) structure. One nonvolatile device using such an ONO structure is a device including a cell having a silicon-oxide-nitride-oxide-silicon (SONOS) type. In addition, another nonvolatile memory device using the ONO structure is a floating gate type nonvolatile memory device, and generally, an ONO structure is formed on a floating gate of a polysilicon type.

The SONOS device is a nonvolatile memory device having a charge trapping layer. A silicon film, a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode having a channel region therein are included. It has a structure laminated sequentially.

1 is a cross-sectional view of a nonvolatile memory device having a charge trap layer.

Referring to FIG. 1, a tunneling layer 110 made of an oxide film is formed on a semiconductor substrate 100 such as a silicon substrate. In the semiconductor substrate 100, impurity regions 102 such as source / drain regions are disposed to be spaced apart from each other by a predetermined distance, and channel regions 104 are disposed therebetween. The silicon nitride film 120 is formed as a charge trap layer on the tunneling layer 110, and an insulating film 130 as a shielding layer and a control gate electrode 140 are sequentially formed thereon.

The operation of the nonvolatile memory device having such a structure is as follows. First, when the control gate electrode 140 is positively charged and an appropriate bias voltage is applied to the impurity region 102, hot electrons are transferred from the semiconductor substrate 100 to the trap site of the silicon nitride film 120, which is a trap layer. Trapped. This is an operation of writing data to a memory cell or programming a memory cell. Similarly, when the control gate electrode 140 is negatively charged and an appropriate bias is applied to the impurity region 102, holes are trapped from the semiconductor substrate 100 to the trap site of the silicon nitride film 120, which is a charge trap layer. As a result, the trapped holes recombine with the extra electrons already in the trap site. This is the operation of erasing the programmed memory cell.

The nonvolatile memory device having such a general charge trap layer has excellent reliability in terms of interference and data retention compared to the existing floating gate type device. However, compared to the floating gate type device, the low and nonuniform trap density of the silicon nitride film 120 exhibits a disadvantage in that the erase operation is particularly slow. That is, in the above structure, since the trap site in the silicon nitride film 120 which is the charge trap layer is not sufficient, a high voltage is required during the program operation. Electrons trapped by this high voltage are trapped in a relatively deep trap site or trapped at an interface between the tunnel insulating film 110 and the silicon nitride film 120, which makes the erase operation difficult and erases. Slow down the operation. Therefore, in order to improve the speed of the program and erase operation of the device, it is necessary to uniformly form trap sites in the silicon nitride film trap layer, and implement a large amount of stable defect sites having the same trap energy level in the silicon nitride film.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having an improved program speed by including a charge trap layer having a large amount of uniform trap sites.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of improving a program speed by including a charge trap layer having a uniform trap side.

In order to achieve the above technical problem, a nonvolatile memory device having a charge trap layer according to the present invention includes a semiconductor substrate, a tunneling layer formed on the semiconductor substrate, and a trap disposed on the tunneling layer and doped with donor impurities. And a charge trap layer having a site, a shielding layer disposed on the charge trap layer to block charge movement, and a control gate electrode disposed on the shielding layer for applying a predetermined bias to the cell. do.

The charge trap layer has a structure in which a lower trap layer doped with donor impurities and an upper trap layer are stacked. The lower trap layer is made of a silicon nitride film having a chemical formula of Si _N N _Y (X is 0 to 5 and Y is 0 to 7), and has a thickness of 1 to 20 kPa. The upper trap layer is formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 10 to 1,000 ∼.

The donor impurities doped in the charge trap layer are phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), chlorine (Cl), fluorine (F), selenium (Se), It may be any one of tellurium (Te), iodine (I), astatin (At), or polonium (Po).

The shielding layer may include aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₃ ), hafnium oxide (HfO ₂ ), radium oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), strontium titanium oxide (SrTiO). ₃ ) or an oxide film having a perovskite structure.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device having a charge trap layer according to the present invention, including forming a tunneling layer on a semiconductor substrate and a lower trap doped with donor impurities on the tunneling layer. Forming a layer, annealing the lower trap layer such that the donor impurities are concentrated at the interface of the lower trap layer and the knurling layer, forming an upper trap layer on the lower trap layer, and Forming a shielding layer for blocking charge transfer on the trap layer, forming a control gate electrode for applying a predetermined bias on the shielding layer, and patterning the control gate electrode to the annealing layer in this order To form a gate stack.

The lower trap layer may be formed of a silicon nitride film having a chemical formula of Si _N N _Y (X is 0 to 5 and Y is 0 to 7).

In addition, the upper trap layer may be formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 10 ~ 1,000Å.

In the forming of the lower trap layer, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), chlorine (Cl), fluorine (F), Any one of selenium (Se), tellurium (Te), iodine (I), asatin (At), or polonium (Po) can be used.

After the annealing of the lower trap layer, the method may further include etching a portion of the lower trap layer.

In the etching of part of the lower trap layer, an etchant based on phosphoric acid (H ₃ PO ₄ ) is used.

In the etching of a portion of the lower trap layer, the lower trap layer is etched so as to remain in a thickness of 1 to 20 kPa.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

2 is a cross-sectional view showing an example of a nonvolatile memory device having a charge trap layer according to the present invention.

Referring to FIG. 2, an example of a nonvolatile memory device having a charge trap layer according to the present invention includes a tunneling layer disposed sequentially from a semiconductor substrate 200 on which an impurity region 202 and a channel region 204 are formed. 210, a charge trap layer 220, a shielding layer 230, a barrier layer 240, a control gate electrode 250, a low resistance layer 260, and a hard mask layer 270.

The semiconductor substrate 200 may be a conventional silicon (Si) substrate, and in some cases, another substrate such as a silicon on insulator (SOI) substrate may be used. The impurity region 202 becomes a source / drain region of the device.

The tunneling layer 210 allows charge carriers, such as electrons or holes, to be tunneled and injected into the charge trap layer 220 under a predetermined bias, and is typically made of an insulating film, such as silicon oxide film (SiO ₂ ). Since the tunneling layer 210 may be degraded by repeated tunneling of charge carriers, and thus the stability of the device may be degraded, the tunneling layer 210 may have a thickness that can be prevented as much as possible.

The charge trap layer 220 is a layer for trapping electrons or holes injected through the tunneling layer 210. The uniform energy level and the number of trap sites result in better trapping of charge, thereby making it easier to program and erase the device. Speed may increase. The charge trap layer 220 of the present invention is a silicon nitride film (Si _N N _Y ; donor impurity doped with silicon) (Si _N N _Y ; the lower trap layer 222 consisting of 0 to 0, Y is 0 ~ and silicon nitride film (Si ₃ N) ₄ ) the upper trap layer 224. The lower trap layer has a thickness of about 1 to 20 kPa, and the upper trap layer of about 10 to 1,000 kPa.

The lower trap layer 222 is doped with donor impurities in order to provide a uniform and many trap sites. For example, the donor impurities include phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), It may be any one of sulfur (S), chlorine (Cl), fluorine (F), selenium (Se), tellurium (Te), iodine (I), asatin (At), or polonium (Po).

Since the lower trap layer 222 is formed so that the impurities are concentrated through an annealing process after depositing a silicon nitride film doped with donor impurities, a large amount of trap sites are uniformly generated, and thus, compared with a conventional silicon nitride film. You have an increased trap site. In addition, the donor-type impurity has excellent characteristics of capturing electrons, so electrons to be compensated for charge are easily trapped in large quantities, and thus the program speed may be increased rapidly.

The shielding layer 230 is for blocking the movement of charge from the charge trap layer 220 toward the upper control gate electrode 250, and is formed of a high dielectric material to improve the operation speed of the cell. The shielding layer 230 may be, for example, an aluminum oxide layer (Al ₂ O ₃ ), a zirconium oxide layer (ZrO ₃ ), a hafnium oxide layer (HfO ₂ ), a radium oxide layer (La ₂ O ₃ ), or a tantalum oxide layer (Ta ₂ O ₅ ). , Strontium titanium oxide film (SrTiO ₃ ) or perovskite oxide film.

The control gate electrode 250 applies a bias of a predetermined size so that electrons or holes are trapped from the channel region 204 of the substrate 200 to the trap site in the charge trap layer 220. The control gate electrode 250 may be formed of a polysilicon film or a metal film doped with n-type.

A barrier layer 240 is further provided between the shielding layer 230 and the control gate electrode 250 to prevent charge from moving from the control gate electrode 250 toward the shielding layer 230 during an erase operation. During the erase operation, a high bias is applied to the substrate 200 and the control gate electrode 250 is grounded. At this time, electrons are transferred from the control gate electrode to the substrate, thereby making it difficult to erase. Therefore, the barrier layer is formed of a metal having a high work function in order to prevent this and facilitate an erase operation. The barrier layer 240 is made of, for example, any one of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or radium nitride (LaN).

A low resistance layer 260 is disposed on the control gate electrode 250 to reduce the resistance of the gate line. In some cases, the low resistance film may be omitted. When the control gate electrode 250 is made of a polysilicon film, the low resistance film 260 may be formed of tungsten silicide.

According to the nonvolatile memory device having the charge trap layer of the present invention having such a structure, by providing a lower trap layer doped with a donor-type impurity having excellent characteristics of capturing electrons, charge compensation is performed. The electrons are easily trapped in large quantities, so that the program speed can be dramatically increased.

3 to 6 are cross-sectional views schematically illustrating a method of manufacturing a nonvolatile memory device having a charge trap layer according to the present invention.

Referring to FIG. 3, an impurity region 202 and a channel region 204 are formed in an active region of the semiconductor substrate 200 through impurity ion implantation and activation. Next, a tunneling layer 210 is formed by depositing or growing an oxide film having a predetermined thickness on the semiconductor substrate 200, and then depositing a silicon nitride film on the tunneling layer 210 to form a lower trap layer for charge trapping ( 222 is formed.

The lower trap layer 222 is formed of a silicon nitride film doped with a donor type impurity (Si _N N _Y , X is 0 to 5 and Y is 0 to 7) to improve the program speed of the device. . The donor-type impurities are, for example, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), chlorine (Cl), fluorine (F), selenium (Se), tellurium ( Te), iodine (I), asatin (At), polonium (Po), or the like can be used. The lower trap layer 222 may be formed using any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). It is formed in the thickness of 5-1,000 mm.

The lower trap layer 222 may be doped with a donor-type impurity, for example, by a diffusion or ion implantation method. When the lower trap layer 222 is formed by a diffusion method, a silicon nitride film is deposited and then a diffusion process is performed in-situ. As the diffusion energy, thermal energy and plasma energy may be used. When thermal energy is used as the diffusion energy, the process is performed at a temperature of about 450 to 1,500 ° C. using a rapid heating method (RTP). At this time, the semiconductor substrate or the element formed on the semiconductor substrate is carried out in a reducing gas atmosphere to suppress the oxidation, and suitable reducing gases include argon (Ar), neon (Ne), nitrogen (N ₂ ) and the like.

When the lower trap layer 222 is formed in a diffusion method and plasma energy is used as the diffusion energy, the gas for generating plasma includes reduction of argon (Ar), neon (Ne), nitrogen (N ₂ ), and the like. Gas can be used and proceeds at a temperature in the range from 450 to 1,000 ° C. The energy for activating the plasma is preferably in the range of 10 to 3,000 W, and the pressure is preferably 0.1 mtorr to 500 tor.

When the lower trap layer 222 doped with the donor type impurity is formed by ion implantation, first, a silicon nitride film is deposited on the tunneling layer 210 to a thickness of about 5 to 1,000 占 퐉, and then the impurity is formed. Inject at an energy of ˜50 KeV.

Referring to FIG. 4, annealing is performed on a semiconductor substrate on which a lower trap layer 222 doped with donor-type impurities is formed at a predetermined temperature so that donor impurities implanted by diffusion or ion implantation are lower trap layer 222. To be concentrated at the interface between the tunneling layer 210 and the Thus, since a large amount of uniform trap sites are formed at the interface between the tunneling layer 210 and the lower trap layer 222, the program speed of the device can be improved.

Referring to FIG. 5, a portion of the lower trap layer is removed using an etchant based on a nitride film etchant, for example, phosphoric acid (H ₃ PO ₄ ). The portion where the donor impurities are uneven due to the annealing process is removed from the nitride film and most of the areas in which the damage is generated in the ion implantation process for doping the nitride film is removed, and the donor impurities are concentrated by the annealing process 222a. ) Will remain. The lower trap layer 222a doped with donor impurities provides a trap site that allows charge carriers in the channel region 204 in the substrate 200 to trap through the tunneling layer 210. Therefore, the etching amount is adjusted so that the thickness of the lower trap layer 222a remaining after the etching becomes about 1 to about 20 kPa.

Next, a silicon nitride film Si ₃ N ₄ is deposited on the resultant portion of the lower trap layer etched to form the upper trap layer 224. The upper trap layer 224 is formed of a silicon nitride film (Si ₃ N ₄ ) to a thickness of 10 ~ 1,000Å by chemical vapor deposition (CVD) or atomic layer deposition (ALD method) using thermal energy. The trap layer 222a and the upper trap layer 224 constitute a charge trap layer 220.

Referring to FIG. 6, a shielding layer 230 is formed by depositing a material having a high dielectric constant on the upper trap layer 224. The shielding layer 230 may be formed of an oxide film by chemical vapor deposition (CVD). Alternatively, in order to improve the characteristics of the device, a material having a high dielectric constant, such as an aluminum oxide film (Al ₂ O ₃ ), a zirconium oxide film (ZrO ₃ ), a hafnium oxide film (HfO ₂ ), a radium oxide film (La ₂ O ₃ ), A tantalum oxide film (Ta ₂ O ₅ ), a strontium titanium oxide film (SrTiO ₃ ), or the like may be formed of an oxide film having a perovskite structure.

Next, a barrier metal 240 is deposited on the shielding layer 230 to form a barrier layer 240. The barrier layer 240 is formed of a metal having a high work function to prevent the electrons from flowing from the control gate electrode to the substrate during the erasing operation and to facilitate the erasing operation. Materials for forming the barrier layer 240 include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) or radium nitride (LaN).

Next, a control gate electrode 250 is formed on the barrier layer 240, and a low resistance layer 260 is formed thereon. The control gate electrode 250 may be formed of a polysilicon film doped with n-type impurities. The low resistance layer 260 is for reducing the resistance of the control gate electrode and may be formed of a tungsten silicide layer WSi.

Next, a hard mask layer 270 to be used as a mask is formed on the low resistance layer 260 by, for example, depositing a nitride film to form a gate stack.

Subsequently, the hard mask layer 270, the low resistance layer 260, the control gate electrode 250, the barrier layer 240, the shielding layer 230, and the trap layer 220 and the tunneling layer 210 are sequentially etched to complete the gate stack as shown in FIG. 2.

As described above, according to the nonvolatile memory device having the charge trap layer according to the present invention and a method of manufacturing the same, a uniform silicon layer in which a charge can be trapped in the trap layer by forming a silicon film in which the donor-type impurities are doped and concentrated in the trap layer. By forming a large amount of one trap site, the electrons can be rapidly trapped in large quantities so that the program and erase speeds of the device can be dramatically increased.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (14)

Semiconductor substrates; A tunneling layer formed on the semiconductor substrate; A charge trap layer disposed on the tunneling layer and having a trap site doped with donor impurities; A shielding layer disposed on the charge trap layer to block the movement of charge; And And a control gate electrode disposed on the shielding layer, the control gate electrode for applying a predetermined bias to the cell. The method of claim 1, wherein the charge trap layer, A nonvolatile memory device having a charge trap layer having a structure in which a lower trap layer doped with donor impurities and an upper trap layer are stacked. The method of claim 2, wherein the lower trap layer, A nonvolatile memory device having a charge trap layer comprising a silicon nitride film having a chemical formula of Si _N N _Y (X is 0 to 5 and Y is 0 to 7). The method of claim 2, wherein the lower trap layer, Nonvolatile memory device having a charge trap layer, characterized in that having a thickness of 1 ~ 20 ∼. The method of claim 2, wherein the upper trap layer, Non-volatile memory device having a charge trap layer, characterized in that the silicon nitride film (Si ₃ N ₄ ) having a thickness of 10 ~ 1,000 ∼. The donor impurity doped in the charge trap layer, Phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), chlorine (Cl), fluorine (F), selenium (Se), tellurium (Te), iodine (I), Non-volatile memory device having a charge trap layer, characterized in that any one of astaxin (At), or polonium (Po). The method of claim 1, The shielding layer may include aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₃ ), hafnium oxide (HfO ₂ ), radium oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), strontium titanium oxide (SrTiO). ₃ ) or a nonvolatile memory device having a charge trap layer, characterized in that it is made of any one of an oxide film having a perovskite structure. Forming a tunneling layer on the semiconductor substrate; Forming a lower trap layer doped with donor impurities on the tunneling layer; Annealing the lower trap layer such that the donor impurities are concentrated at the interface between the lower trap layer and the knurling layer; Forming an upper trap layer on the lower trap layer; Forming a shielding layer on the upper trap layer to block the transfer of charge; Forming a control gate electrode on the shielding layer to apply a predetermined bias to the cell; And And forming a gate stack by sequentially patterning the control gate electrode and the tunneling layer. The method of claim 8, The lower trap layer is formed of a silicon nitride film having a chemical formula of Si _N N _Y (X is from 0 to 5, Y is from 0 to 7). The method of claim 8, And the upper trap layer is formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 10 to 1,000 Å. The method of claim 8, wherein in the forming of the lower trap layer, The donor impurities include phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), chlorine (Cl), fluorine (F), selenium (Se), tellurium (Te) and iodine A method for manufacturing a nonvolatile memory device having a charge trap layer, characterized in that any one of (I), asatin (At), or polonium (Po) is used. The method of claim 8, After annealing the lower trap layer, And etching a portion of the lower trap layer. The method of claim 12, In the etching of a portion of the lower trap layer, A method of manufacturing a nonvolatile memory device having a charge trap layer, characterized by using an etchant based on phosphoric acid (H ₃ PO ₄ ). The method of claim 12, In the etching of a portion of the lower trap layer, And etching the lower trap layer so as to remain at a thickness of 1 to 20 microseconds.

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