CN1246890C - Method for mfg. MOS transistor with low grid depletion phenomenon - Google Patents
Method for mfg. MOS transistor with low grid depletion phenomenon Download PDFInfo
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- CN1246890C CN1246890C CN 02103355 CN02103355A CN1246890C CN 1246890 C CN1246890 C CN 1246890C CN 02103355 CN02103355 CN 02103355 CN 02103355 A CN02103355 A CN 02103355A CN 1246890 C CN1246890 C CN 1246890C
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Abstract
The present invention provides a method for making a metal oxide semiconductor (MOS) transistor, which prevents the MOS transistor in a nitride read only memory (NROM) from generating a gate depletion phenomenon and simultaneously increases the grid drive capability of the MOS transistor. In the method of the present invention, a semiconductor chip with a memory array region and a peripheral circuit region is firstly defined on a substrate surface; then, a gate electrode comprising a silica layer, an amorphous silicon layer and a silicon germanium layer is formed on the surface of the peripheral circuit zone, and a side wall, a source electrode and a drain electrode of the MOS transistor are formed around the gate electrode; finally, a nickel (Ni) layer is formed on the top surface of the gate electrode, and a fast heating annealing making process of 400 to 500 DEG C is carried out, so the nickel layer and the silicon germanium layer on the top surface of the gate electrode form a nickel-silicon layer.
Description
FIELD OF THE INVENTION
The present invention relates to a kind of method of making MOS transistor, especially refer to a kind of metal-oxide semiconductor transistor generation grid vague and general (Gate Depletion) phenomenon that prevents in the nitride ROM, improve the method for making MOS transistor of the gate driving ability (gate drivability) of this MOS transistor simultaneously.
Background note
Nitride ROM (nitride read only memory, NROM) be a kind of semiconductor element that is used for storage data, it is made up of a plurality of memory cell (memory cell), and each memory cell all includes the gate dielectric of a control grid and an ONO structure.Because the silicon nitride layer in the ONO gate dielectric has the compactness of height, therefore can make the hot electron that enters in the silicon nitride layer via MOS transistor tunnelling (tunneling) sink into (trap) wherein, be used for being used as floating grid to reach the purpose of storage data.
Please refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is the existing method schematic diagram of making the mononitride read-only memory, and this nitride ROM include a storage array (memory array) with and peripheral circuit (periphery circuits).As shown in Figure 1, existing method is that semiconductor chip 10 is provided earlier, and the silicon base 12 surface definition of semiconductor chip 10 have a storage array (memory array) district's 11 and one peripheral circuit (periphery circuits) district 13.
At first form an ONO dielectric layer of being formed by bottom oxide 14, silicon nitride layer 16 and top oxide layer 18 in silicon base 12 surface.Wherein, bottom oxide 14 is for utilizing about 750～1000 ℃ thermal-oxidative production process of a temperature, the silicon oxide layer of about 50～150 of thickness that form in silicon base 12 surfaces, the thickness of silicon nitride layer 16 is about 20～150 , is about oxidized silicon nitride layer or the silicon oxide layer deposited of 50～250 and top oxide layer 18 is a thickness.
Then as shown in Figure 2, in storage array district 11, form the photoresist floor 20 of a patterning, to define the position of bit line 22.Utilize photoresist layer 20 as mask (mask) subsequently, carry out an anisotropic dry etch manufacture craft, to remove top oxide layer 18 and the silicon nitride layer 16 that is not covered, until bottom oxide 14 or silicon base 12 surfaces by photoresist layer 20.And then carry out an ion and inject manufacture craft, in silicon base 12, form a plurality of doped regions, with bit line 22 as memory.Wherein, the dopant dosage of this ion injection manufacture craft is about 2～4 * 10
5/ cm
2, and the injection energy is about 50KeV.
As shown in Figure 3, remove photoresist layer 20 subsequently, and utilize about 800～950 ℃ thermal oxidation method of a temperature (thermal oxidation), to form the oxide layer 24 of about 500 of a thickness in surface, bit line 22 tops, as the isolation between each ONO dielectric layer.Simultaneously, this thermal-oxidative production process can activate the dopant in the doped region.
On the other hand, the formation of the metal oxide semiconductor transistor on the periphery circuit region 13, can utilize a photomask that includes memory array area pattern and periphery circuit region region pattern earlier, as shown in Figure 4, periphery circuit region 13 is carried out an etching and oxidation manufacture craft in regular turn, previous to remove in the silicon base 12 surperficial ONO dielectric layers that form, and form a grid oxic horizon 26.That is to say, utilize photomask 11 to form a photoresist floor (not shown) earlier as mask in the storage array district, the ONO dielectric layer that utilizes periphery circuit region 13 again is as a sacrifice layer, carry out an ion of adjusting starting voltage with transistor and inject manufacture craft periphery circuit region 13, then utilize a dry ecthing manufacture craft to remove a layer oxide layer 18 and a silicon nitride layer 16 in regular turn, and utilize a wet etching manufacture craft to remove bottom oxide 14.Remove this photoresist layer at last, and carry out a thermal-oxidative production process to form the silicon oxide layer that a thickness is about 100～150 , as transistorized grid oxic horizon 26 in the periphery circuit region 13 in silicon base 12 surfaces.And in storage array district 11, because the relation that silicon nitride layer 16 exists, this thermal-oxidative production process can't obviously have influence on the thickness of top oxide layer 18.
After grid oxic horizon 26 forms, then in silicon base 12 surface depositions one polysilicon layer, with as the word line in the storage array district 11 28, as shown in Figure 5, and transistorized grid conducting layer 30 in the periphery circuit region 13.Carry out a standard manufacture craft subsequently to finish the transistorized making of periphery circuit region 13: at first in periphery circuit region 13, carry out an ion and inject manufacture craft, with the lightly doped drain 32 that forms each MOS transistor, and form sidewall 33 in each MOS transistor side wall deposition, then carry out another ion and inject manufacture craft, in the silicon base 12 of each MOS transistor both sides, to form one source pole 35 and drain electrode 37, form a metal silicide layer 38 in grid conducting layer 30 end faces more at last, as shown in Figure 6.Wherein, the polysilicon layer that constitutes grid conducting layer 30 also can be in the source electrode 35 of each MOS transistor and the ion injection manufacture craft of drain electrode 37, being injected into simultaneously is a doped polysilicon layer, and utilize the follow-up annealing of carrying out (anneal) manufacture craft, so that dopant is spread in the polysilicon layer equably.
Because the MOS transistor of the periphery circuit region of NROM is as the metal material that forms metal silicide layer with cobalt, titanium or molybdenum now, so can consume silicon atom more in the grid conducting layer, cause dopant can't be uniformly distributed in the grid conducting layer, and make part of grid pole lack dopant, so-called grid vague and general (gate depletion) phenomenon takes place, and then causing the delay of grid transmitting signals, the ammeter that seriously reduces this element is existing.
Summary of the invention
Therefore, purpose of the present invention promptly is to provide a kind of metal-oxide semiconductor transistor generation grid vague and general (Gate Depletion) phenomenon that prevents in the nitride ROM, improves the method for making MOS transistor of the gate driving ability (gate drivability) of this MOS transistor simultaneously.
In most preferred embodiment of the present invention, the inventive method is to provide substrate surface definition that the semiconductor chip of one a storage array district and a periphery circuit region is arranged earlier, then on this periphery circuit region surface, form one and include the grid of a silica layer, an amorphous silicon layer and a silicon germanide layer, and around this grid, form sidewall, source electrode and the drain electrode of this MOS transistor.Form a nickel dam at this grid end face at last, and carry out one 400～500 ℃ flash annealing manufacture craft, so that the silicon germanide layer of this nickel dam and this grid end face forms a nisiloy layer.
MOS transistor compared to existing periphery circuit region, the MOS transistor of utilizing the inventive method made is as the metal material that forms metal silicide layer with a nickel dam, therefore the grid end face phase reaction of this nickel dam and this MOS transistor and when forming this nisiloy layer, can consume a spot of silicon atom.On the other hand, because the MOS transistor that the present invention makes, be to utilize an amorphous silicon layer and a silicon germanide layer stacked on top to constitute grid, this also can increase the active adulterant matter concentration (activedopant concentration) in this grid, therefore utilize the MOS transistor of the inventive method made can effectively avoid the generation of the vague and general phenomenon of grid, and have higher gate driving ability simultaneously.
According to an aspect of the present invention, a kind of method of making MOS transistor is provided, in order to prevent the vague and general phenomenon of metal oxide semiconductor transistor generation grid in the nitride ROM, improve the gate driving ability of this MOS transistor simultaneously, this method includes the following step: provide the semiconductor chip, and the definition of the substrate surface of this semiconductor chip has a storage array district and a periphery circuit region; On this periphery circuit region surface, form a silica layer; On this silica layer surface, form an amorphous silicon layer; Form a silicon germanide layer on this amorphous silicon layer surface; This silicon germanide layer of patterning and this amorphous silicon layer are to form the grid of this MOS transistor on this substrate surface; Around this grid, form sidewall; Carry out one first ion and inject manufacture craft, on this substrate surface of the relative both sides of this grid, to form two doped regions; Carry out a thermal annealing manufacture craft,, form the one source pole and a drain electrode of this MOS transistor to drive in the dopant in this two doped region; Form a nickel dam at this grid end face; And carry out a flash annealing manufacture craft, so that the silicon germanide layer of this nickel dam and this grid end face forms a nisiloy layer, wherein being used for driving in the germanium atom that this thermal annealing manufacture craft of the dopant of this two doped region can spread in this silicon germanide layer enters in this amorphous silicon layer, so that this amorphous silicon layer changes into SiGe, and then suppress the vague and general phenomenon of this MOS transistor generation grid.
According to another aspect of the present invention, provide a kind of method of making MOS transistor, in order to reduce the vague and general phenomenon of grid and to improve the gate driving ability, this method includes the following step: the semiconductor chip is provided; On the silicon base surface of this semiconductor chip, form a silica layer; On this silica layer surface, form an amorphous silicon layer; Carry out the chemical vapour deposition (CVD) manufacture craft of mixing simultaneously, to form a silicon germanide layer on this amorphous silicon layer surface, the composition of this silicon germanide layer is Si
1-xGe
x, x=0.05～1.0 wherein; This silicon germanide layer of patterning and this amorphous silicon layer are to form the grid of this MOS transistor on this silicon base surface; Around this grid, form sidewall; Carry out one first ion and inject manufacture craft, on this silicon base surface of the relative both sides of this grid, to form two doped regions; Carry out a thermal annealing manufacture craft,, form the one source pole and a drain electrode of this MOS transistor to drive in the dopant in this two doped region; Form a nickel dam at this grid end face; And carry out a flash annealing manufacture craft, so that the silicon germanide layer of this nickel dam and this grid end face forms a nisiloy layer, wherein being used for driving in the germanium atom that this thermal annealing manufacture craft of the dopant of this two doped region can spread in this silicon germanide layer enters in this amorphous silicon layer, so that this amorphous silicon layer changes into SiGe, and then suppress the vague and general phenomenon of this MOS transistor generation grid.
The simple declaration of accompanying drawing
Fig. 1 to Fig. 6 is the existing method schematic diagram of making the mononitride read-only memory.
Fig. 7 to Fig. 9 makes the method schematic diagram of MOS transistor for the present invention in nitride ROM.
The reference numeral explanation
10 semiconductor chips, 12 silicon base
11 storage array districts, 13 periphery circuit regions
14 bottom oxides, 16 silicon nitride layers
18 top oxide layers, 20 photoresist layers
22 bit lines, 24 oxide layers
26 grid oxic horizons, 28 character lines
30 grid conducting layers, 32 lightly doped drains
33 sidewalls, 35 source electrodes
37 drain electrodes, 38 metal silicide layers
51 periphery circuit regions, 52 silicon base
54 grid oxic horizons, 56 grids
59 sidewalls, 60 source electrodes
62 drain electrodes, 64 nisiloy layers
The description of specific embodiment
Please refer to Fig. 7 to Fig. 9, Fig. 7 to Fig. 9 is that the present invention is in nitride ROM (nitride readonly memory, NROM) middle metal-oxide semiconductor (MOS) (metal-oxide semiconductor, MOS) the transistorized method schematic diagram made.
In most preferred embodiment of the present invention, at first provide the semiconductor chip, and the silicon base 52 surface definition of semiconductor chip there are a storage array (memory array) district's (not shown) and a peripheral circuit (periphery circuits) district 51.The storage array district is used for forming a plurality of NROM memory cell (NROM memory cell), and periphery circuit region 51 then is to be used for forming MOS transistor of the present invention.Wherein, the manufacture method of the NROM in storage array district is the ONO dielectric layer that carries out a patterning prior to silicon base 52 surfaces, then in silicon base 52, form many bit lines and field oxide, adjust the transistorized starting voltage value of periphery circuit region 51 at last, and remove the ONO dielectric layer on periphery circuit region 51 surfaces.
Then as shown in Figure 7, go up formation one silica layer in periphery circuit region 51 surfaces, in order to grid oxic horizon (gateoxide) 54 as a N type MOS transistor (NMOS) or a P type MOS transistor (PMOS).Then formation one amorphous silicon (amorphous silicon) layer on the silica layer surface, and the utilization mode of (in-situ) simultaneously is Si in this amorphous silicon layer surface formation one chemical composition
1-xGe
xThe SiGe of (x=0.05～1.0) (silicon germanium) layer carries out an etching process subsequently, and this silicon germanide layer of etching, this amorphous silicon layer and this silica layer are to go up the grid (gate) 56 that forms this MOS transistor in silicon base 52 surfaces.Wherein, silicon germanide layer is to utilize a feeding that silicomethane (silane, SiH are arranged
4), germane (germane, GeH4) and hydrogen (hydrogen) and the chemical vapour deposition (CVD) of depositing temperature between 450 ℃～620 ℃ (chemical vapor deposition CVD) forms.
As shown in Figure 8, carry out one first ion subsequently and inject manufacture craft (ion implantation), be used for forming lightly doped drain (lightly doped drain, LDD) 58 of this MOS transistor.Around grid 56, form sidewall 60 then, and carry out one second ion and inject manufacture craft, form two doped regions to go up in silicon base 52 surfaces of the relative both sides of grid 56, carry out a high annealing (annealing) manufacture craft then, driving in the dopant in (driving in) this two doped region, and the one source pole (source) 60 and that in silicon base 52, forms this MOS transistor (drain) 62 that drain.
Subsequently as shown in Figure 9, form a nickel (nickel, Ni) layer (not shown) in grid 56 end faces.Then carry out one 400～500 ℃ flash annealing manufacture craft (rapid thermal annealingprocess, RTA process), so that the silicon germanide layer phase reaction of this nickel dam and grid 56 end faces and form a nisiloy layer 64.Remove unreacted nickel dam at last, to finish the making of this MOS transistor.
Because method of in nitride ROM, making MOS transistor of the present invention, be to utilize the metal material of a nickel dam as the metal silicide layer that forms the grid end face, and this nickel dam with the silicon germanide layer phase reaction of this grid end face when forming this nisiloy layer, only consume the silicon atom in a spot of this silicon germanide layer.On the other hand, this MOS transistor is to utilize an amorphous silicon layer and a silicon germanide layer stacked on top to constitute this grid, enter in this amorphous silicon layer at the germanium atom that spreads in this silicon germanide layer by follow-up high annealing manufacture craft of carrying out then, so that this amorphous silicon layer changes into SiGe, and increase the interior active adulterant matter concentration of this grid.Therefore compared to existing MOS transistor, the MOS transistor that the present invention makes is the phenomenon of suppressor grid vague and general (Gate Depletion) effectively, and then significantly improves the gate driving ability (gate drivability) of this MOS transistor.
The above only is the preferred embodiments of the present invention, and all equivalences of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (15)
1. a method of making MOS transistor in order to prevent the vague and general phenomenon of metal oxide semiconductor transistor generation grid in the nitride ROM, improves the gate driving ability of this MOS transistor simultaneously, and this method includes the following step:
Provide the semiconductor chip, and the definition of the substrate surface of this semiconductor chip there are a storage array district and a periphery circuit region;
On this periphery circuit region surface, form a silica layer;
On this silica layer surface, form an amorphous silicon layer;
Form a silicon germanide layer on this amorphous silicon layer surface;
This silicon germanide layer of patterning and this amorphous silicon layer are to form the grid of this MOS transistor on this substrate surface;
Around this grid, form sidewall;
Carry out one first ion and inject manufacture craft, on this substrate surface of the relative both sides of this grid, to form two doped regions;
Carry out a thermal annealing manufacture craft,, form the one source pole and a drain electrode of this MOS transistor to drive in the dopant in this two doped region;
Form a nickel dam at this grid end face; And
Carry out a flash annealing manufacture craft, so that the silicon germanide layer of this nickel dam and this grid end face forms a nisiloy layer,
Wherein being used for driving in the germanium atom that this thermal annealing manufacture craft of the dopant of this two doped region can spread in this silicon germanide layer enters in this amorphous silicon layer, so that this amorphous silicon layer changes into SiGe, and then suppress the vague and general phenomenon of this MOS transistor generation grid.
2. method as claimed in claim 1, wherein this substrate is a silicon base.
3. method as claimed in claim 1, wherein the chemical composition of this silicon germanide layer is Si
1-xGe
x, x=0.05～1.0.
4. method as claimed in claim 1, wherein this silicon germanide layer of patterning also can this silica layer of patterning.
5. method as claimed in claim 1, wherein this silica layer is intended for the grid oxic horizon of this MOS transistor, and this silicon germanide layer and this nisiloy layer are intended for the grid conducting layer of this MOS transistor.
6. method as claimed in claim 1, wherein this MOS transistor is a N type MOS transistor or a P type MOS transistor.
7. method as claimed in claim 1 also includes one second ion and injects manufacture craft, is used for forming the lightly doped drain of this MOS transistor.
8. method as claimed in claim 1 when wherein the silicon germanide layer of this nickel dam and this grid end face forms this nisiloy layer, consumes the silicon atom in a spot of this silicon germanide layer, with the vague and general phenomenon of suppressor grid, and then improves the driving force of this MOS transistor.
9. method as claimed in claim 1, wherein this nisiloy layer is to utilize a feeding to have silicomethane, germane and hydrogen and the chemical vapour deposition (CVD) of depositing temperature between 450 ℃～620 ℃ to form.
10. method of making MOS transistor, in order to reduce the vague and general phenomenon of grid and to improve the gate driving ability, this method includes the following step:
The semiconductor chip is provided;
On the silicon base surface of this semiconductor chip, form a silica layer;
On this silica layer surface, form an amorphous silicon layer;
Carry out the chemical vapour deposition (CVD) manufacture craft of mixing simultaneously, to form a silicon germanide layer on this amorphous silicon layer surface, the composition of this silicon germanide layer is Si
1-xGe
x, x=0.05～1.0 wherein;
This silicon germanide layer of patterning and this amorphous silicon layer are to form the grid of this MOS transistor on this silicon base surface;
Around this grid, form sidewall;
Carry out one first ion and inject manufacture craft, on this silicon base surface of the relative both sides of this grid, to form two doped regions;
Carry out a thermal annealing manufacture craft,, form the one source pole and a drain electrode of this MOS transistor to drive in the dopant in this two doped region;
Form a nickel dam at this grid end face; And
Carry out a flash annealing manufacture craft, so that the silicon germanide layer of this nickel dam and this grid end face forms a nisiloy layer,
Wherein being used for driving in the germanium atom that this thermal annealing manufacture craft of the dopant of this two doped region can spread in this silicon germanide layer enters in this amorphous silicon layer, so that this amorphous silicon layer changes into SiGe, and then suppress the vague and general phenomenon of this MOS transistor generation grid.
11. as the method for claim 10, wherein this silicon germanide layer of patterning also can this silica layer of patterning.
12. as the method for claim 10, wherein this silica layer is used as the grid oxic horizon of this MOS transistor, and this silicon germanide layer and this nisiloy layer are used as the grid conducting layer of this MOS transistor.
13. as the method for claim 10, wherein this MOS transistor is a N type MOS transistor or a P type MOS transistor.
14. as the method for claim 10, also include one second ion and inject manufacture craft, be used for forming the lightly doped drain of this MOS transistor.
15. as the method for claim 10, wherein the manufacture craft gas of this chemical vapour deposition (CVD) manufacture craft of mixing simultaneously includes silicomethane, germane and hydrogen, and the depositing temperature of this chemical vapour deposition (CVD) manufacture craft of mixing simultaneously is between 450 ℃～620 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02103355 CN1246890C (en) | 2002-01-30 | 2002-01-30 | Method for mfg. MOS transistor with low grid depletion phenomenon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02103355 CN1246890C (en) | 2002-01-30 | 2002-01-30 | Method for mfg. MOS transistor with low grid depletion phenomenon |
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| Publication Number | Publication Date |
|---|---|
| CN1435868A CN1435868A (en) | 2003-08-13 |
| CN1246890C true CN1246890C (en) | 2006-03-22 |
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| CN 02103355 Expired - Fee Related CN1246890C (en) | 2002-01-30 | 2002-01-30 | Method for mfg. MOS transistor with low grid depletion phenomenon |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100468780C (en) * | 2006-06-09 | 2009-03-11 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
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2002
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