CN1286170C - Method for manufacturing flash memory - Google Patents
Method for manufacturing flash memory Download PDFInfo
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- CN1286170C CN1286170C CNB031222102A CN03122210A CN1286170C CN 1286170 C CN1286170 C CN 1286170C CN B031222102 A CNB031222102 A CN B031222102A CN 03122210 A CN03122210 A CN 03122210A CN 1286170 C CN1286170 C CN 1286170C
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000010410 layer Substances 0.000 claims abstract description 166
- 239000004020 conductor Substances 0.000 claims abstract description 65
- 230000002093 peripheral effect Effects 0.000 claims abstract description 32
- 239000011241 protective layer Substances 0.000 claims abstract description 26
- 230000005641 tunneling Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 42
- 238000000059 patterning Methods 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000013043 chemical agent Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The present invention relates to a flash memory preparing method. The method provides a basement which is provided with a memory cell region and a peripheral circuit region, a tunneling dielectric layer is formed on the basement of the memory cell region, and a lining layer is formed on the basement of the peripheral circuit region. Subsequently, a patterned grid conductor layer is formed on the basement. A grid gap dielectric layer and a protective layer are orderly formed on the basement. The protection layer, the grid gap dielectric layer, a first conductor layer and the lining layer of the peripheral circuit region are removed, a grid dielectric layer is formed on the basement of the peripheral circuit region, and the protection layer of the memory cell region is changed into an oxide layer. A conductor layer is formed on the basement, the conductor layer, the oxide layer, the grid gap dielectric layer and the grid conductor layer of the memory cell region are patterned to form a memory grid, and a second conductor layer of the peripheral circuit region is patterned to form a grid.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor element, and particularly relevant for the manufacture method of a kind of flash memory (Flash Memory) element.
Background technology
Flash memory (Flash Memory) element can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of non-volatile memory device of extensively adopting.
Typical flash element is to make floating grid (Floating Gate) and control grid (Control Gate) with the polysilicon that mixes.And the control grid is set directly on the floating grid, and floating grid is separated by with dielectric layer with controlling between the grid, and between floating grid and substrate with tunnel oxide (Tunneling Oxide) be separated by (that is so-called stacked gate flash memory).This flash element is to utilize the plus or minus voltage that is applied on the control grid to control the injection and the discharge of the electric charge in the floating grid (Floating gate), to reach the function of storage.
Figure 1A to Fig. 1 D is depicted as the part manufacturing process profile of known a kind of flash element.In Figure 1A to Fig. 1 D, substrate 100 can be divided into memory cell areas 102 and peripheral circuit region 104.
At first, please refer to Figure 1A, in the substrate 100 of memory cell areas 102, form tunneling dielectric layer 106, and in the substrate 100 of peripheral circuit region 104, form lining 108.Then, in whole substrate 100, form one deck conductor layer 110, and the conductor layer on the patterning memory cell areas 102 110, make its layout and form conductor layer 110a into strips.Afterwards, in forming dielectric layer 112 between grid in the substrate 100, the material of dielectric layer 112 is silica/silicon nitride/silicon nitride between these grid.
Then, please refer to Figure 1B, form patterning photoresist layer 114 in substrate 100, this patterning photoresist layer 114 covers memory cell areas 102 and exposes peripheral circuit region 104.Serve as the cover curtain with patterning photoresist layer 114 again, remove dielectric layer 112 between the grid on the peripheral circuit region 104, conductor layer 110 and lining 108.Then, form gate dielectric 116 in peripheral circuit region 104.
Then, please refer to Fig. 1 C, remove patterning photoresist layer 114 after, in whole substrate 100, form conductor layer 118.
Then, please refer to Fig. 1 D, patterning conductor layer 118 and on memory cell areas 102, form control gate conductor layer 118a, then dielectric layer 112, conductor layer 110a and tunneling dielectric layer 106 between patterned gate form gate stack structure to form by dielectric layer 112a, conductor layer 110b and tunneling dielectric layer 106a between control gate conductor layer 118a, grid.Simultaneously, the conductor layer 118 on the patterning peripheral circuit region 104 is to form the grid structure of being made up of gate oxide 116a and conductor layer 118b.
In above-mentioned technology, because dielectric layer 112 is very thin and very fragile between grid, thereby be easy in manufacture process, for example be in the cineration technics of patterning photoresist layer 114 and cleaning, to be subjected to damage.And make the characteristic variation of dielectric layer 112 between grid, and then the data that produce flash memory are kept the problem of characteristic variation.
On the other hand, avoid hurting the top oxide layer in the dielectric layer 112 between grid for above-mentioned, therefore in the photoresistance stripping technology, can't use stronger cleaning agent, thereby cause fully photoresistance to be removed and producing high molecular residue, and then cause the pollution and the grid bad of metal.
Summary of the invention
Therefore, a purpose of the present invention is providing a kind of flash memory making method exactly, makes that dielectric layer is difficult for suffering damage in manufacture process between grid, and can lift elements usefulness.
Another object of the present invention is providing a kind of flash memory making method exactly, can avoid producing in technology high molecular residue, and then can avoid polluting and improving the grid quality.
The invention provides a kind of flash memory making method, the method provides the substrate with memory cell areas and peripheral circuit region, forms tunneling dielectric layer again in the substrate of memory cell areas, and forms lining in the substrate of periphery circuit region.Then, form first conductor layer in substrate, first conductor layer on the patterning memory cell areas again is to form gate conductor layer.Then, in forming dielectric layer between grid in the substrate, on dielectric layer between grid, form protective layer again., remove between the protective layer, grid of peripheral circuit region dielectric layer, first conductor layer and lining, in the substrate of peripheral circuit region, form gate dielectric again, and make the protective layer of memory cell areas change oxide skin(coating) into thereafter.Afterwards, form second conductor layer in substrate, dielectric layer and gate conductor layer are forming a plurality of storage grids between second conductor layer of patterning memory cell areas, oxide skin(coating), grid again, and second conductor layer of patterning peripheral circuit region is to form a plurality of grids.
As mentioned above, owing to be in forming protective layer on the dielectric layer between grid, can avoid therefore that dielectric layer is subjected to infringement between grid in fabrication schedule, and can keep the characteristic of dielectric layer between grid to cover dielectric layer between the grid on the memory cell areas.
And, because the present invention forms protective layer on dielectric layer between grid, therefore can use stronger chemical agent to remove and the step of cleaning, thereby can avoid the generation of high molecular residue with the photoresistance that carries out in the technology.
Description of drawings
Figure 1A to Fig. 1 D is depicted as known a kind of flash memory making method flow process profile.
Fig. 2 A to Fig. 2 F is depicted as a kind of flash memory making method flow process profile of preferred embodiment of the present invention.
100,200: substrate
102,202: memory cell areas
104,204: peripheral circuit region
106,206: tunneling dielectric layer
108,208: lining
110,110a, 110b, 118,118b, 210,210a, 210b, 228,228b: conductor layer
112,212: dielectric layer between grid
114,222: the patterning photoresist layer
116,224: gate dielectric
118a, 228a: control gate conductor layer
214: bottom oxide
216: silicon nitride layer
218: the top oxide layer
220: protective layer
226: oxide layer
Embodiment
Following according to appended graphic, a kind of flash memory making method of detailed description preferred embodiment of the present invention.In Fig. 2 A to Fig. 2 F, substrate 200 can be divided into memory cell areas 202 and peripheral circuit region 204.
At first, please refer to Fig. 2 A, in the substrate 200 of memory cell areas 202, form tunneling dielectric layer 206, and in the substrate 200 of peripheral circuit region 204, form lining 208.Wherein tunnel oxide 206 for example is a silica with the material of lining 208, and its formation method for example is a thermal oxidation method.
Then, in whole substrate 200, form one deck conductor layer 210, the material of conductor layer 210 for example is a doped polycrystalline silicon, and the formation method of this conductor layer 210 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it.Then, the conductor layer 210 on the patterning memory cell areas 202 makes its layout and form conductor layer 210a (gate conductor layer) into strips.Afterwards, in forming dielectric layer 212 between grid in the substrate 200, the material of dielectric layer 212 for example is silica/silicon nitride/silicon nitride between these grid, the formation method of dielectric layer 212 for example is earlier with silicon oxide layer 214 at the bottom of thermal oxidation method formation one deck between these grid, then, utilize the silicon nitride layer 216 of chemical vapour deposition technique formation again, on silicon nitride layer 216, form top silicon oxide layer 218 thereafter again as charge immersing layer.
Then, please refer to Fig. 2 B, form layer protective layer 220 in substrate 200, wherein the material of this protective layer 220 for example is a silicon nitride, and the formation method of this protective layer 220 for example is to utilize chemical vapour deposition technique to form one deck thin silicon nitride layer.
Then, please refer to Fig. 2 C, form one deck patterning photoresist layer 222 in substrate 200, this patterning photoresist layer 222 covers memory cell areas 202 and exposes peripheral circuit region 204.Then, serve as cover curtain with patterning photoresist layer 222, remove dielectric layer 212, conductor layer 210 and lining 208 between protective layer 220 on the peripheral circuit region 204, grid.
Then, please refer to Fig. 2 D, remove patterning photoresist layer 222, and optionally cleaning is carried out in substrate 200, form gate dielectric 224 in peripheral circuit region 204 again, and make the protective layer 220 in memory cell arrays district 202 change oxide layer 226 into.Wherein form gate dielectric 224 and make the method that protective layer 220 changes oxide layer 226 into for example be to use thermal oxidation method.
Remove in the patterning photoresist layer 222 or the step of cleaning above-mentioned; owing on dielectric layer between grid 212, be formed with protective layer 220; therefore can use stronger chemical agent (for example is that hydrofluoric acid or SC-1 cleaning fluid (also are called APM; ammoniacal liquor hydrogen peroxide mixed liquor)) with the removal of carrying out photoresist layer 220 and the cleaning of substrate 200; and can not cause damage, and can reach the purpose that photoresist layer 222 is removed fully to dielectric layer between grid 212.
Then, please refer to Fig. 2 E, form conductor layer 228 in substrate 200, wherein the material of conductor layer 228 for example is a doped polycrystalline silicon, the formation method of this conductor layer 228 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it.
Then, please refer to Fig. 2 F, patterning conductor layer 228 is to form control gate conductor layer 228a, follow dielectric layer 212, conductor layer 210a and tunneling dielectric layer 206 between patterned gate, to form the gate stack structure (that is being meant storage grid) that forms by dielectric layer 212a, conductor layer 210b and tunneling dielectric layer 206a institute storehouse between control gate conductor layer 228a, grid.Simultaneously, the conductor layer 228 on the patterning peripheral circuit region 204 and form the grid structure 232 that forms by gate oxide 224a and conductor layer 228b institute storehouse.The follow-up technology of finishing flash memory is known by those skilled in the art, does not repeat them here.
According to the foregoing description; the present invention is behind dielectric layer 212 between the formation grid; be on dielectric layer between grid 212, to form protective layer 220; cover dielectric layer 212 between the grid on the memory cell areas; therefore can avoid that dielectric layer 212 is subjected to infringement between grid in fabrication schedule, and then can keep the characteristic of dielectric layer 212 between grid.
And, because the present invention forms protective layer 220 on dielectric layer between grid 212, therefore can use stronger chemical agent to remove and the step of cleaning, and then photoresist layer 222 can be removed fully and avoided the generation of high molecular residue to carry out photoresistance.
Claims (12)
1. a flash memory making method is characterized in that, this method comprises the following steps:
Substrate with a memory cell areas and a peripheral circuit region is provided;
In this substrate of this memory cell areas, form a tunneling dielectric layer, and in this substrate of this periphery circuit region, form a lining;
In this substrate, form one first conductor layer;
This first conductor layer on this memory cell areas of patterning is to form a gate conductor layer;
In forming dielectric layer between grid in this substrate;
On dielectric layer between these grid, form a protective layer;
Remove dielectric layer, this first conductor layer and this lining between this protective layer, these grid of this peripheral circuit region;
This substrate in this peripheral circuit region forms a gate dielectric, and makes this protective layer of this memory cell areas change the monoxide layer into;
In this substrate, form one second conductor layer; And
Dielectric layer and this gate conductor layer to be forming a plurality of storage grids between this second conductor layer of this memory cell areas of patterning, this oxide skin(coating), these grid, and this second conductor layer of this peripheral circuit region of patterning is to form a plurality of grids.
2. flash memory making method as claimed in claim 1 is characterized in that dielectric layer comprises the silicon oxide/silicon nitride/silicon oxide layer between these grid.
3. flash memory making method as claimed in claim 1 is characterized in that the material of this gate conductor layer comprises polysilicon.
4. flash memory making method as claimed in claim 1 is characterized in that the material of this protective layer comprises silicon nitride.
5. flash memory making method as claimed in claim 1 is characterized in that, forms this gate dielectric in this substrate of this peripheral circuit region, and makes the method that this protective layer of this memory cell areas changes this oxide skin(coating) into comprise thermal oxidation method.
6. flash memory making method as claimed in claim 1 is characterized in that the material of this second conductor layer comprises polysilicon.
7. a flash memory making method is characterized in that, this method comprises the following steps:
Substrate with a memory cell areas and a peripheral circuit region is provided;
In this substrate of this memory cell areas, form a tunneling dielectric layer, and in this substrate of this periphery circuit region, form a lining;
In this substrate, form one first conductor layer;
This first conductor layer on this memory cell areas of patterning is to form a gate conductor layer;
In this substrate, form a bottom oxide;
On this bottom oxide, form an electric charge capture layer;
On this electric charge capture layer, form a top oxide layer;
On this top oxide layer, form a protective layer;
Remove this protective layer, this top oxide layer, this electric charge capture layer, this bottom oxide, this first conductor layer and this lining of this peripheral circuit region;
This substrate in this peripheral circuit region forms a gate dielectric, and makes this protective layer of this memory cell areas change the monoxide layer into;
In this substrate, form one second conductor layer; And
This second conductor layer of this memory cell areas of patterning, this oxide skin(coating), this top oxide layer, this electric charge capture layer, this bottom oxide and this gate conductor layer are forming a plurality of storage grids, and this second conductor layer of this peripheral circuit region of patterning is to form a plurality of grids.
8. flash memory making method as claimed in claim 7 is characterized in that the material of this electric charge capture layer comprises silicon nitride.
9. flash memory making method as claimed in claim 7 is characterized in that the material of this gate conductor layer comprises polysilicon.
10. flash memory making method as claimed in claim 7 is characterized in that the material of this protective layer comprises silicon nitride.
11. flash memory making method as claimed in claim 7 is characterized in that, forms this gate dielectric in this substrate of this peripheral circuit region, and makes the method that this protective layer of this memory cell areas changes this oxide skin(coating) into comprise thermal oxidation method.
12. flash memory making method as claimed in claim 7 is characterized in that, the material of this second conductor layer comprises polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031222102A CN1286170C (en) | 2003-04-21 | 2003-04-21 | Method for manufacturing flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031222102A CN1286170C (en) | 2003-04-21 | 2003-04-21 | Method for manufacturing flash memory |
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| Publication Number | Publication Date |
|---|---|
| CN1540748A CN1540748A (en) | 2004-10-27 |
| CN1286170C true CN1286170C (en) | 2006-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031222102A Expired - Fee Related CN1286170C (en) | 2003-04-21 | 2003-04-21 | Method for manufacturing flash memory |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456453C (en) * | 2005-09-27 | 2009-01-28 | 力晶半导体股份有限公司 | Production of flash memory |
| KR101075490B1 (en) | 2009-01-30 | 2011-10-21 | 주식회사 하이닉스반도체 | Semiconductor device with buried gate and method for fabricating the same |
| CN106298483B (en) * | 2015-05-31 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | The production method of the production method and embedded flash memory of polysilicon gate |
| CN108598081B (en) * | 2018-04-25 | 2019-12-10 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
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| CN1540748A (en) | 2004-10-27 |
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